Through Silicon Via Process Research Articles

Formation of Through-Silicon-Vias Using Pressure Infiltration of Molten Tin

Formation of through-silicon-via (TSV) was examined by pressure infiltration of molten Sn into Si via-holes with variations of the infiltration pressure, infiltration time and via-hole size. Contrary to the conventional Cu TSV process which requires complicate and long Cu electroplating, the method using pressure infiltration of molten Sn is fast enough to complete via-filling within 5 s regardless of the via-hole size. The ratio of the unfilled volume to the initial volume of a via-hole versus the external infiltration pressure well satisfied the Boyle’s law. TSVs of different diameters in a wide range of 10–200 µm could be easily formed at once by infiltration of molten Sn at an external pressure of 4 MPa for 5 s.

Enhancing the Wettability of High Aspect-Ratio Through-Silicon Vias Lined With LPCVD Silicon Nitride or PE-ALD Titanium Nitride for Void-Free Bottom-Up Copper Electroplating

One of the critical steps toward producing void-free and uniform bottom-up copper electroplating in high aspect-ratio (AR) through-silicon vias (TSVs) is the ability of the copper electrolyte to spontaneously flow through the entire depth of the via. This can be accomplished by reducing the concentration gradient of cupric ions from the via mouth to the via bottom by enhancing the wettability of the vias sidewalls. In this paper, we report on a new dry technique to enhance the hydrophilicity in high AR (~15) TSVs as one of the key solutions to face the mass transport limitation, low pressure chemical vapor deposition silicon nitride and atomic layer deposition titanium nitride of composition SiN0.95 and TiN11, respectively, are used as both barrier layers and wetting surfaces in these vias. Ammonia plasma immersion is used to treat silicon nitride. X-ray photoelectron spectroscopy shows both a partial oxidation and grafting of hydrophilic components. Alternatively, a rapid flood ultraviolet exposure step in order to photocatalytically activate the surface and induce a partially oxidized titanium nitride is used to create a highly wettable interface with a contact angle close to zero. These wettability enhancement steps were incorporated in a TSV process to produce 3-D cross-Kelvin structures using bottom-up copper electroplating. The vias lined with silicon nitride and titanium nitride exhibited a low average resistance of 25 mΩ and 50 mΩ, respectively, making them very suitable for radio-frequency signal transmission. This all-dry technology to achieve superhydrophilic barrier layers can be employed in both high and low thermal budget processing, thus enabling via-last or via-first flowchart schemes for advanced 3-D interconnects.

Integration of Tantalum Pentoxide Capacitors With Through-Silicon Vias

Metal filled through-silicon vias (TSVs) allow devices to be connected using a 3-D approach. Optimizing and refining this technology has been a focus for the semiconductor industry the past few years because of the need for novel integrated circuit (IC) packages that address the issues associated with increased functionality and performance while reducing size and costs for a growing number of defense and consumer electronic applications. Vertical interconnection using TSV technology has emerged as a convenient way to improve system performance. Integration of decoupling capacitors with TSVs represents an attractive alternative to conventional 2-D layouts to achieve miniaturization and increased density. Decoupling capacitors can be brought in close proximity to the active elements, thereby reducing their parasitic inductance and allowing higher clock rates. In this paper, capacitors with anodized tantalum oxide dielectric were integrated with TSVs and their performance was evaluated. Fabricated capacitors were found to exhibit satisfactory electrical properties before and after TSV processing although some changes in their properties were observed. The performance of these capacitors for applications such as high speed decoupling capacitors was evaluated by measuring resonant frequency, parasitic inductance, and parasitic resistance.

Technology Assessment of Through-Silicon Via by Using $C$–$V$ and $C$–$t$ Measurements

C-V characteristics of through-silicon vias (TSVs) manufactured in two different processing lines are compared to demonstrate the reproducibility of the TSV process module in terms of the minimum TSV depletion capacitance in the operating voltage region. TSV C-V and C-t measurements before and after thermocycling are employed for assessing the oxide liner and Ta barrier integrity of the TSV under the influence of temperature. It is observed that TSV C-V and C-t characteristics remain unchanged before and after thermocycling (1000 cycles).

3-D Wafer-Level Packaging Die Stacking Using Spin-on-Dielectric Polymer Liner Through-Silicon Vias

In this paper, we report on the processing and the electrical characterization of a 3-D-wafer level packaging through-silicon-via (TSV) flow, using a polymer-isolated, Cu-filled TSV, realized on thinned wafers bonded to temporary carriers. A Cu/Sn micro-bump structure is integrated in the TSV process flow and used for realizing a two-die stack. Before TSV processing, the Si wafers are bonded to temporary carriers and thinned down to 50 μm. The actual TSV and micro-bump process uses 3 masks, two Si-deep-reactive ion etching steps and a polymer liner as a dielectric. The dimensions of the TSV structure are: 35 μm OTSV, 5 μm thick polymer liner, 25-μm-O Cu TSV, 50 μm deep TSV, and a 60 μm TSV pitch.

Diffusion Resistance of Low Temperature Chemical Vapor Deposition Dielectrics for Multiple Through Silicon Vias on Bumpless Wafer-on-Wafer Technology

Diffusion behavior of Cu in Cu through-silicon-vias (TSVs) fabricated using low-temperature plasma enhanced chemical vapor deposition (LT-PECVD) has been evaluated. Silicon oxynitride (SiON) barrier films were formed by LT-PECVD at 150 °C. Cu diffusion rate was found to increase with decreasing film density. The critical density and thickness for prevention of Cu diffusion into Si substrate have been estimated. In case of a film with density >60% of the bulk value and/or thickness >100 nm, no change of electrical resistance for stacked wafers containing TSVs was observed after 1000 cycles of thermal stress. According to above results, SiON film formed at 150 °C can be used for the TSV process without any degradation of electrical characteristics and reliability, enabling a reduction in total process temperature in the wafer-on-wafer technology.

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

Failure Analysis and Reliability of 3D Integrated Systems

Today 3D integration based on through silicon vias (TSV) is a well-accepted approach to overcome the performance bottleneck and simultaneously shrink the form factor. According to the ITRS road map [1] there is a variety of reasons for application of 3D integration, such as miniaturization, improved circuit performance, lower power consumption and heterogeneous integration. World-wide, several full 3D process flows have been demonstrated. However, there is a strong demand for considering the behaviour and reliability of 3D-integrated systems [2]. Explicitly, the impact of 3D processes on the system, e.g. thermo-mechanical stresses, has to be evaluated before the implementation to production lines. A test chip for reliability evaluation of 3D TSV technologies was designed and fabricated by Fraunhofer EMFT. The 3D-integrated reliability test chip is a 3-level-stack with TSVs through a middle (2nd) device layer to connect structures on the bottom (1st) level with the top (3rd) level device. The layout is modular, so you can test basic assembly processing with the combination of level 1 with level 2 only and the influence of additional processing when adding level 3. For reliability testing, temperature cycling following the JEDEC standard was performed from −55 C ° to +150 °C (at a soak time of 5 minutes). Additionally, analysis was done by cross sectioning and reversed engineering. The 3D-integrated test chips were fabricated by application of Fraunhofer EMFT's TSV SLID technology. The applied 3D TSV process is based on intermetallic compound (IMC) bonding and TSV formation before stacking [3]. Reliability issues related to thermo-mechanical stress caused by the 3D integration process have to be considered. Failures of 3D integrated systems caused by TSV formation and the permanent bonding process were analysed by a novel high rate milling Focussed Ion Beam equipment. Figure 1 schematically shows the application of the novel FIB analysis technique for the areas of interest (IMC bond, TSV cross sections). Compared to classical FIB systems, the new equipment allows to remove material significantly faster while maintaining good resolution at low beam currents, important for the subsequent analysis. Cross sections of the 3-layer stack are shown in Figure 2. The merits of the novel plasma FIB and the resulting failure analysis will be discussed in detail.

High Removal Rate CMP Process on TSV Thick Cu Overburden

AbstractIn 3D packaging, Through Silicon Vias (TSVs) with high aspect ratios and depths measuring tens of microns are filled by advanced Cu electroplating processes. Today's 300mm TSV plating platforms are intended to produce bottom-up via fill, no seam voids, and minimal, controlled overburden. To achieve this, the preceding Cu-seed coverage must be continuous at a constant resistance, and the plating chemistries optimized. However, other factors such as hardware configurations and simple depletion of the plating formulations during the extended TSV process can lead to high Cu overburden thickness requiring a high removal rate (HRR) chemical-mechanical polish (CMP) process to remove the thick Cu layer.Presented here are CMP results of a thick Cu overburden (~6um) resulting from the fill of 5 x 25um TSVs on 300mm wafers. The goal is to uniformly polish the overburden and utilize the tool's endpoint system at Cu clear before the next step of conventional barrier CMP. Slurries were screened for removal rate, uniformity, planarization ability, and defectivity. This study focuses on achieving a removal rate of >2.5um/min through evaluation of several commercial slurries in a multi-step polish application. Cross-sections post-plating show the Cu overburden, barrier and liner layer. Cross-sections post-CMP quantify Cu recess, dielectric loss, and presence/absence of seam defects. The process selected is demonstrated to achieve good planarization results with low occurrence of polish defects, at a rate and selectivity suitable for emerging 3D TSV Cu CMP applications.

3D System-on-Chip technologies for More than Moore systems

3D integration is a key solution to the predicted performance problems of future ICs as well as it offers extreme miniaturization and cost-effective fabrication of More than Moore products. Through silicon via (TSV) technologies enable high interconnect performance compared to 3D packaging. At present TSVs are associated with a relatively high fabrication cost, but research world wide strive to bring the cost down to an acceptable level. An example of a 3D System-on-Chip (3D-SOC) technology is to introduce a post backend-of-line TSV process as an optimized technology for heterogeneous system integration. The introduced ICV-SLID process, that combines both TSVs and bonding, enables 3D integration of fabricated devices. Reliability issues related to thermo-mechanical stress caused by the TSV formation and the bonding are considered. 3D-SOC technology choices made to realize a heterogeneous ultra-small IC stack for a wireless tire pressure monitoring system (TPMS) as an automotive application are described.

Failure Analysis and Process Improvement for Through Silicon Via Interconnects

AbstractThis paper investigates the failure causes for slopped through silicon vias (TSV) and presents process improvement for implementing the slopped TSV for 3D wafer level packaging (WLP). IMEC is developing slopped and scaled generic approaches for 3D WLP. Previously we have reported on the integrated process flow for the slopped (TSV) and showed the feasibility of Parylene N as a dielectric material. In the TSV process discussed here, firstly 200mm device wafer is bonded facedown on a carrier using temporary glue layer and thinned by grinding. TSV's are realized by dry etching from the wafer backside, followed by dielectric deposition and patterning. Dielectric patterning is done at the bottom of the via on 100 microns thin silicon device wafer supported by the carrier. Finally, conformal plating is done inside the via to obtain the interconnections.This paper discusses the yield killer or failure causes in the slopped TSV process. There can be many parameter including silicon etch uniformity, dielectric etching at the bottom of the via and resist residue inside the via that can reduce the yield of the process. We report that one of the main factors contributing to the yield loss is silicon dry etching effects including non-uniformity and notching. Using standard Bosch etching process, notching at the interface between landing oxide and silicon has been observed. The notching cause a discontinuity at the bottom of the via resulting in no plating at the bottom interface.In this paper we report on a new via shape that is a combination of slopped and straight etching sequence to overcome the notching problem. Different parameters including influence of grinding marks, mask opening, wafer thickness variation, etching rate and etching profile across the wafer were investigated. The optimized design rules for mask opening and effect of individual etching parameters on the etching profile will be presented. In etching, firstly a sloped via with slope of 60 degrees is optimized with changing different etching parameters including different gasses and pressure. Slope via facilitates in subsequent dielectric deposition and sputtering processes. Secondly, a straight wall etching process based on Bosch process and soft landing step with longer passivation steps were investigated to obtain the notch free etching profile. The optimized etching process is notch free, very repeatable and total variation across different wafers is less then 2 percent for 100 micron target opening.This paper reports the failure analysis of TSV and discuses the processes improvement to obtain higher yielding vias. Different parameters that reduced the yield are discussed with main focus on notching effects during silicon etching. An improved and characterized, notch free uniform silicon etching across the wafer process based on two step etching is presented. An integration flow implementing the above optimized parameters with electrical yield will be detailed in the paper.

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three-dimensional silicon integration technologies have begun to receive considerable attention. An advanced packaging solution based on a thin silicon carrier has been developed to provide interconnection between integrated circuits (ICs) and other devices at densities. far beyond those of current first-level packaging. The silicon carrier employs fine-pitch Cu damascene wiring, high-density solder interconnections, and through-silicon vias (TSVs). A key enabling technology element is the TSV, which may be naturally scaled to provide vertical interconnection in stacked ICs as well as silicon carriers. In this paper, we discuss the evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10-20 mΩ and yields on the order of 99.99% at wafer level in a research laboratory environment. Two generalized process approaches to forming TSVs are discussed, the vias-first and the vias-last methods, along with related advantages and potential drawbacks of each. Improvement to these process, flows and structures is afforded by simple changes of via geometry from cylindrical to annular or from annular to multibar. While various TSV metallurgies are reviewed, tungsten is shown to be a nearly optimal choice. Results on via resistance, electrical yield, and current-carrying capacity are covered. The use of electrical modeling to predict structures with superior electrical and mechanical properties is also described.