Through Silicon Via Pair Research Articles

Frequency-Dependent Characteristics and Parametric Modeling of the Silicon Substrate in TSV-Based 3-D ICs

This paper presents an in-depth investigation of the silicon substrate characteristics based on frequency-dependent parameters in the through-silicon via (TSV)-based 3-D ICs. It is the first time to define the frequency bands accurately on the ground of a quantitative standard of calibration to represent different characteristics of the silicon substrate. Moreover, by converting the conventional model of a TSV pair into an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> parallel circuit, a simplified model is established which makes the analysis of the silicon substrate concise associated with the frequency variation. To further reveal the influence of silicon substrate on the signal transmission between adjacent TSVs, relevant impedance parameters of the silicon substrate are converted into the impedance ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Z</i> ) matrix for parametric modeling, which is validated by 3D full-wave simulations. This work contributes a systematic examination of the silicon substrate characteristics with the variation of frequency, and provides significant guidance for parametric analysis and modeling in TSV-based 3-D ICs.

Novel De-Embedding Methodology and Broadband Microprobe Measurement for Through-Silicon Via Pair in Silicon Interposer

In this paper, a novel de-embedding methodology is proposed for through silicon via (TSV) characterization by using a set of simple yet efficient test patterns. For all the test patterns, full wave models are developed and the electrical performance of the test patterns is analyzed thoroughly. Furthermore, broadband measurements are performed for the test patterns to verify the accuracy of the developed full wave models up to 40 GHz. Correlation between measurement and simulation results is discussed after optimizing the full wave models based on scanning electron microscope measurement. Analysis of measurement error is available as well. The proposed de-embedding method is applied to both the simulation and measurement results to extract the electrical characteristics of the TSV pair. Good agreement between the de-embedded results with analytical solution and the full-wave simulation for a standalone TSV pair indicates that the proposed de-embedding method works effectively up to 40 GHz. Finally, sensitivity analysis with regard to manufacturing tolerance of the test patterns to the final de-embedded results is performed.

High-Frequency Electrical Modeling and Characterization of Differential TSVs for 3-D Integration Applications

This letter makes a fast and efficient analysis of the scalable differential through-silicon via (TSV) configuration in 3-D integrated circuits. The equivalent-circuit model of a differential TSV pair is described. The critical differential characteristics are analyzed and calculated in terms of a lumped-circuit model and the effective loop parameters of multi-TSVs. The calculated results are validated by the 3-D full-wave field solver high frequency simulator structure (HFSS) over a wide frequency range.

TEM-Like Launch Geometries and Simplified De-embedding for Accurate Through Silicon Via Characterization

Novel de-embedding launch geometries and a simplified analytical procedure are proposed to extract the exact electromagnetic behavior of a through silicon via (TSV) pair from measured data. First, the most recent de-embedding method is reviewed and it is deeply investigated using both 3-D simulation and vector network analyzer measurements to accurately evaluate its residual error. Then, some potential sources of error are hypothesized and overcome by the proposed launch geometries based on a de-embedding plane that is able to ensure a TEM (or quasi-TEM) mode propagation. The novel launches are studied through 3-D simulations; the previous de-embedding procedure is updated to consider the fringing effect of the open-end launch, and it is simplified reducing the launch standards from three to two. The proposed launch geometries and algorithm are shown to be more accurate in the TSV pair de-embedding with respect to the method currently employed.

TSV Replacement and Shield Insertion for TSV–TSV Coupling Reduction in 3-D Global Placement

Through silicon via (TSV) cross coupling can seriously degrade circuit performance of 3-D ICs if it is not considered during design. In this paper, we propose two algorithms which combine coupling-aware TSV placement with shield insertion to yield better results than either technique alone. We first introduce an algorithm for TSV placement assuming a fixed standard cell placement. The result of this algorithm is a 13% reduction in worst case coupling across all TSV pairs and a 90% reduction in the total number of TSV pairs violating an imposed coupling threshold. We then introduce a second algorithm that perturbs a given standard cell and TSV placement to improve coupling. This second algorithm yields a 17% reduction in worst case coupling and removes all coupling violations. Both algorithms cause wirelength (WL) to increase no more than 5%. Our algorithms offer a large improvement to TSV-TSV coupling at the expense of only a meager degradation of total WL, and in many designs and applications this trade-off is well justified.

Synthesis of TSV Fault-Tolerant 3-D Clock Trees

In through-silicon-via (TSV) based 3-D integrated chips (ICs), synthesizing 3-D clock tree is one of the most challenging tasks. Since the clock signal is delivered to clock sinks (e.g., latches, flip-flops) through TSVs, any fault on a TSV in the clock tree may cause a chip failure. Therefore, ensuring the reliability of clock TSVs in 3-D ICs is highly important. To cope with clock TSV reliability problem effectively, we propose a new circuit cell called slew-controlled TSV fault-tolerant unit (SC-TFU) which overcomes the limited capability of the conventional TFUs and propose a full solution to the problem of designing and synthesizing 3-D TSV fault-tolerant clock tree based on SC-TFUs. Precisely, for a presynthesized 3-D clock tree, we solve the problem in three steps: 1) performing a comprehensive TSV pairing algorithm to maximally allocate SC-TFUs; 2) replacing TSV pairs obtained in step 1 with SC-TFUs followed by TSV tripling to maximize TSV fault-tolerance under wire and time constraints; and 3) performing a global clock skew tuning process on the SC-TFU embedded 3-D clock tree produced in step 2. Through out experiments, two outstanding benefits are confirmed: 1) our synthesis using SC-TFUs enables a large number of clock TSVs to be paired or tripled to ensure a very high degree of TSV fault-tolerance and 2) our synthesis flow effectively performs tuning of global clock skew whose variation is caused by the inclusion of TSV fault-tolerant cells into 3-D clock trees.

Magnetic Current Imaging of a TSV short in a 3D IC

In this paper we show Magnetic Field Imaging (MFI) is the best method for Electric Fault Isolation (EFI) of short failures in 2.5/3D Through Silicon Via (TSV) devices in a true non-destructive way by imaging the current path. To confirm the failing locations and to do Physical Failure Analysis (PFA), a Dual Beam-Plasma FIB (DB-PFIB) system was used for cross sectioning and volume analysis of the TSV structures and high resolution imaging of the identified defects. Magnetic Current Imaging (MCI) is a sub technique of MFI which has been used by the semiconductor industry for more than a decade to find electrical shorts and leakage paths and which has the capability to “look through” all materials typically used in the semiconductor industry, allowing global imaging without the need for physical de-processing [1, 2, 3]. MCI utilizes two types of sensors: a Superconducting Quantum Interference Device (SQUID) sensor for low current and large working distances and a Giant Magneto Resistance (GMR) sensor for sub micron resolution current imaging at wafer/die level [3]. The sample investigated in this work is a triple-layer stack, in which 2 layers of 50 μm thick test chip (Chip 1 and Chip 2 in Figure 1) were assembled on a 200 μm thick bottom chip (Chip 0 in Figure 1). The test chips were manufactured by imec's standard 65 nm CMOS Back End of Line (BEOL) process, 5×50 μm via-middle TSV technology [4], and fine pitch micro bumping process [6]. Further details of the test vehicle and assembly process can be found elsewhere [5]. The sample had a short between daisy chain a1 and a2, which were supposed to be electrically separated. The probe tests that was used for this experiment is shown in Table 1. The signal was injected into the respective daisy chains by probing V+ to V− on the bottom chip. To send a signal between daisy chain a1 and a2 one could probe V− to V− and V+ to V+. The MCI scans were done using the GMR sensor only. The sample was attached to a vacuum chuck and raster scanned. From Fig. 2 one can see that the current enters the top layer (Chip 2) at TSV 18 and goes back down again to Chip 1 at TSV 28. Since the sample clearly has multiple shorts, the short located at TSV pair 23 was chosen for PFA using the PFIB. A short is found between the 2 BEOL layers of Chip 1, causing the current to leak into Chip 2 (Fig. 3).

New de-embedding structures for extracting the electrical parameters of a through-silicon-via pair

Two innovative de-embedding methods are proposed for extracting an electrical model for a through-silicon-via (TSV) pair consisting of a ground-signal (GS) structure. In addition, based on microwave network theory, a new solution scheme is developed for dealing with multiple solutions of the transfer matrix during the process of de-embedding. A unique solution is determined based on the amplitude and the phase characteristic of S parameters. In the first de-embedding method, a typical “π“ type model of the TSV pair is developed, which illustrates the need to allow for frequency dependence in the equivalent TSV pair Spice model. This de-embedding method is shown to be effective for extracting the electrical properties of the TSVs. The feasibility of a second de-embedding method is also investigated.

Modeling and Application of Multi-Port TSV Networks in 3-D IC

Through-silicon-via (TSV) enables vertical connectivity between stacked chips or interposer and is a key technology for 3-D integrated circuits (ICs). While arrays of TSVs are needed in 3-D IC, there only exists a frequency-dependent resistance, inductance, conductance and capacitance circuit model for a pair of TSVs with coupling between them. In this paper, we develop a simple yet accurate circuit model for a multiport TSV network (e.g., coupled TSV array) by decomposing the network into a number of TSV pairs and then applying circuit models for each of them. We call the new model a pair-based model for the multiport TSV network. It is first verified against a commercial electromagnetic solver for up to 20 GHz and subsequently employed for a variety of examples for signal and power integrity analysis.

Modeling and Analysis of a Power Distribution Network in TSV-Based 3-D Memory IC Including P/G TSVs, On-Chip Decoupling Capacitors, and Silicon Substrate Effects

In this paper, we propose a model for 3-D stacked on-chip power distribution networks (PDNs) in through silicon via (TSV)-based 3-D memory ICs that includes the effects of power/ground TSVs (P/G TSVs), on-chip decoupling capacitors (on-chip decaps), and the silicon substrate. In the modeling procedure of 3-D stacked on-chip PDNs, the distributed RLGC-lumped model of an on-chip PDN, including the effects of the on-chip decaps and silicon substrate, is proposed. Additionally, the RLGC-lumped model of a P/G TSV pair is introduced. The proposed model of the 3-D stacked on-chip PDN combines the proposed models of on-chip PDNs with the models of P/G TSV pairs in a hierarchical order with a segmentation method. The proposed models of the on-chip PDN and 3-D stacked on-chip PDN are successfully validated by simulations and measurements up to 20 GHz. Additionally, with these models, the impedances of the 3-D stacked on-chip PDNs are analyzed with respect to the variations in the number of P/G TSV pairs, the capacitance of on-chip decaps, and the height of an interlayer dielectric layer between the on-chip PDN and silicon substrate. These variations critically affect the impedance of the 3-D stacked on-chip PDN by changing the capacitance and inductance of the PDN.

ELECTROTHERMAL EFFECTS IN HIGH DENSITY THROUGH SILICON VIA (TSV) ARRAYS

Electrothermal effects in various through silicon via (TSV) arrays are investigated in this paper. An equivalent lumped-element circuit model of a TSV pair is derived. The temperature-dependent TSV capacitance, silicon substrate capacitance and conductance are examined for low-, medium-, and high-resistivity silicon substrates, respectively. The partial-element equivalent-circuit (PEEC) method is employed for calculating per-unit-length (p.u.l.) resistance, inductance, insertion loss and characteristic impedances of copper and polycrystalline silicon (poly-Si) TSV arrays, and their frequencyand temperature-dependent characteristics are treated rigorously. The modified time-domain finite-element method (TD-FEM), in the presence of a set of periodic differential-mode voltage pulses, is also employed for studying transient electrothermal responses of 4and 5-TSV arrays made of different materials, with their maximum temperatures and thermal crosstalk characterized thoroughly.