Through Silicon Via Design Research Articles

Internal defect identification method of TSV 3D packaging based on built-in integrated sensor

TSV (Through Silicon Via) is a key technology for three-dimensional (3D) packaging due to its unique vertical interconnection method. However, its particular manufacturing process of-ten leads to internal defects, such as gaps, bottom voids, filling missing, which are usually difficult to be detected by common means. In order to discover the internal defect of TSV packaging effectively, a novel non-destructive inspection method based on built-in integrated temperature sensor array is proposed. The relationship between temperature distribution and internal defect is dis-covered and then corresponding sensor array layout is designed. The simulation analysis shows that this kind of sensor array can recognize the internal TSV defect. And supervised machine learning is used to construct the classification model by which different defects can be found and classified with relatively high accuracy, and the classification accuracy rate can reach 95.625%. Experiments were conducted and the rationality of this built-in sensing array was verified. The research provides a non-destructive testing method for TSV internal defects based on bulit-in-integrated sensors, and verifies the feasibility of sensor arrangement through simulation, laying a foundation for the realization of later TSV design optimization.

(Invited) Through-Silicon Via Copper Plating and Endpoint Detection

Heterogenous, 2.5D, and 3D integration provide solutions for making microelectronics systems more compact and improving their performance. Cu-filled through-silicon vias (TSVs) are an important interconnect technology for these advanced integration techniques. TSV design and geometry (overall size, aspect ratio, and pitch) depend on the intended microelectronics application. Standard integrated circuit (IC) approaches often utilize high density vias that are achieved through substrate thinning; however, some applications need large-scale vias (≥ 600 µm deep). For example, some microelectromechanical systems (MEMS) applications need full wafer thickness vias due to die thickness specifications, and high-power devices can either employ large-scale vias or via arrays for current requirements and thermal management constraints. Cu deposition fill profile is sensitive to applied voltage or current, electrolyte composition and concentrations, and feature geometry; therefore, deposition processes must be tuned specifically for each via geometry. This work outlines Cu deposition process development and filling results for full wafer thickness TSV geometries in a suppressor-based electrolyte consisting of copper sulfate, sulfuric acid, potassium chloride, and Tetronic 701 suppressor, [i] according to the S-shaped Negative Differential Resistance (S-NDR) mechanism. [ii],[iii] During these TSV filling experiments, unique features in the electrical data were observed that signify completion of Cu plating in the vias. A novel endpoint detection method was derived from these data to determine when vias are filled. [i] Analogous endpoint detection through electrical signals has been previously observed for bottom-up Au filling of high aspect ratio trenches. [iv] During voltage-controlled via filling, as the Cu electrodeposit approaches the top of the TSVs, current can be monitored for a slight rise (due to increased metal ion transport and plating rate high up in the features), followed by a current local minimum (caused by adsorbed suppressor molecules that impede Cu deposition at the top of the vias). These characteristic features in the electrical data can be used to determine via filling completion. A similar technique can be used during current-controlled filling, where voltage data are monitored for a voltage maximum, which indicates that the Cu electrodeposit has reached the top of the features. Current work involves development of an automated method to recognize these electrical endpoint signals and terminate deposition when the vias are filled. This endpoint detection method has potential to greatly enhance microelectronics manufacturing by providing geometry-independent process control, improving manufacturing repeatability, decreasing sensitivity to changes in electrolyte over time, and reducing the time involved in subsequent processing steps through minimizing Cu overburden formation.Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. SAND2021-5013 A [i] R. P. Schmitt et al 2020 J. Electrochem. Soc. 167 162517. [ii] D. Josell and T. P. Moffat 2016 ECS Trans. 75 15. [iii] D. Josell and T. P. Moffat 2018 J. Electrochem. Soc. 165 D23. [iv] S. Ambrozik et al 2019 J. Electrochem. Soc. 166 D443.

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the through-silicon vias (TSVs) defect tend to be clustered, reducing the yield of 3-D integrated circuit significantly. To tackle this fault clustering problem, the existing TSV repair methods adopt the TSV redundancy idea, which brings a major cost to 3-D integration. In this brief, a honeycomb-TDMA TSV design is proposed to mitigate the impact of multiple clustered faults without the need of redundant TSVs (RTSVs), thereby decreasing the area overhead and enhances the yield. The yield of the honeycomb-TDMA architecture can achieve 91.38%-99.67% for different benchmark circuits from IWLS 2005, which has the highest yield. Furthermore, our design achieves total additional hardware (timing delay overhead) reduction by 83.70%-86.85% (46.01%-55.96%), 66.89%-73.25% (29.41%-38.49%), 68.02%-74.20% (41.40%-52.20%), 60.60%-68.18% (18.09%-33.18%), and 75.86%-80.52% (3.05%-20.91%), respectively, compared with router-based, ring-based, group-based, cellular-based, and honeycomb-based methods. Therefore, the proposed architecture is the best choice in terms of yields, hardware overhead, and timing delay.

Robust Microfabrication of Highly Parallelized Three-Dimensional Microfluidics on Silicon

We present a new, robust three dimensional microfabrication method for highly parallel microfluidics, to improve the throughput of on-chip material synthesis by allowing parallel and simultaneous operation of many replicate devices on a single chip. Recently, parallelized microfluidic chips fabricated in Silicon and glass have been developed to increase the throughput of microfluidic materials synthesis to an industrially relevant scale. These parallelized microfluidic chips require large arrays (>10,000) of Through Silicon Vias (TSVs) to deliver fluid from delivery channels to the parallelized devices. Ideally, these TSVs should have a small footprint to allow a high density of features to be packed into a single chip, have channels on both sides of the wafer, and at the same time minimize debris generation and wafer warping to enable permanent bonding of the device to glass. Because of these requirements and challenges, previous approaches cannot be easily applied to produce three dimensional microfluidic chips with a large array of TSVs. To address these issues, in this paper we report a fabrication strategy for the robust fabrication of three-dimensional Silicon microfluidic chips consisting of a dense array of TSVs, designed specifically for highly parallelized microfluidics. In particular, we have developed a two-layer TSV design that allows small diameter vias (d < 20 µm) without sacrificing the mechanical stability of the chip and a patterned SiO2 etch-stop layer to replace the use of carrier wafers in Deep Reactive Ion Etching (DRIE). Our microfabrication strategy allows >50,000 (d = 15 µm) TSVs to be fabricated on a single 4” wafer, using only conventional semiconductor fabrication equipment, with 100% yield (M = 16 chips) compared to 30% using previous approaches. We demonstrated the utility of these fabrication strategies by developing a chip that incorporates 20,160 flow focusing droplet generators onto a single 4” Silicon wafer, representing a 100% increase in the total number of droplet generators than previously reported. To demonstrate the utility of this chip for generating pharmaceutical microparticle formulations, we generated 5–9 µm polycaprolactone particles with a CV < 5% at a rate as high as 60 g/hr (>1 trillion particles/hour).

Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. The temperature changed in the processes of TSV manufacturing and chip using, due to the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials used in TSV structure, significant thermal stress will be induced under the thermal load. These stresses may lead to various reliability issues. Dimension parameters and defects are the two factors affecting the thermal behavior of TSV. In order to optimize TSV design and the quality of via filling, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of diameter, aspect ratio (AR) and defects on TSV thermal stress and deformation in this paper. Simulation results show that the equivalent stress and total deformation of TSV increases as the increase of the diameter of TSV. The effect of aspect ratio on equivalent stress is very little; however, it has a great impact on total deformation, especially for the large diameter of the TSV. Additionally, the effects of shape, size and location of defect on thermal stress were also investigated.

Development of high-yield and high-reliability design for high-performance ultra large scale 3DLSI processor

With LSI micro-fabrication technology reaching its scaling limits, miniaturizing LSIs based on Moore's Law is unable to satisfy the CPU/memory module performance for high-speed, low-power, high-end servers, an alternative integration technology such as three-dimensional integration (3DI) is becoming mainstream. With the development of 3D stacked high-performance processors, specifications that excel in power consumption (200 to 300 W), heat generation, number of electrodes and large die area are required, necessitating a major technical leap from the conventional 3D packaging technologies. A guarantee of reliability and the yield loss is very severe, because of the high-performance processor's needing 30 times or more the both die area and the number of pins compared with the combinational high band width memory stacking. We were the first to verify 3D logic device operation by integrating the following technologies: through-silicon via (TSV) technologies, in which signals are connected in the shortest distance between a top and bottom stacked ultra-large die area processor die; novel redundancy signal transmission design technology; super multi-pins connection technology for high-yield signal transmission with high bandwidth; and high reliability solder joint materials considering power integrity (PI) between stacked dies. To achieve the high-yield TSV connection, the TSV redundant circuit was designed and installed into the stack dies due to the difficulty of the avoidance of defect density (D0) increasing such as large die area. Novel logic macro design with one redundant TSV for 16 signal node enabled the accurate switching selection to redundant defective TSV by using the execution of a pre-test sequence to find bad TSV. In addition, a redundant logic circuit of top and bottom interconnect is a design that gives control signal the redundancy. As a result, the higher operation guarantee was given to the operation execution of controlling circuit. This redundant circuit design technology demonstrated without yield loss of TSV interconnect. For high-reliability fine pitch bump (40-μm pitch) and 10-μm TSV interconnect formation technologies, a large-current, high-heat dissipation and high-precision stacking technology were required. We have developed a process technology for fine-pitch micro bump junctions supporting large current and high-precision I/O bumps stacking dies with 200,000 or more pins using by Ni-Sn intermetallic compound (IMC) solder materials. We also have developed a high accuracy of large die stacking process to be used in fine TSV in which large amounts of current flow and connection terminal sections on dies, achieving stable supply of 300-Watt-class power consumption. Compared with the current density for a 10-year guaranteed lifetime, the case of IMC alloy joining achieves a current density resistance of 4 times more than that of conventional Sn-Ag solder materials, and this has proven to be effective for a high-performance processor. By developing 3DLSI packaging technology compatible with ultra large dies for a high-performance processor and overcoming the issue of yield and reliability, we have achieved a redundancy design technology and micro bump materials of high-yield at product level stacked logic processor with over 750 mm square as full reticle shot size. In this paper, we will discuss the important key redundancy TSV design method and micro bump material technologies; in 3D packaging technology for realizing high-performance ultra large scale processor.

Admittance extraction and analysis for through silicon vias near edge and at corner of silicon substrate

Due to the charge at the interfaces between the silicon substrate and its outer region, the admittance of the through silicon vias (TSVs) near the edge and at the corner of the silicon is different from that of the centre case, which is hardly calculated by conventional empirical formulas. Utilising the method of moment combined with the image method in this study, those admittances can be easily extracted. The difference on the admittance between edge/corner and centre cases is discussed with the frequency and the wave propagation mode. The influence of the distance to the silicon-outer region interfaces and pitches of the TSVs on the admittance are also evaluated and compared in edge and corner cases. The scope of the conventional empirical formulas is also given for the admittance calculation of TSVs in edge/corner case, in order to offer help for the TSVs design.

A Study on Electrical Reliability Criterion on Through Silicon Via Packaging.

Three-dimensional (3D) structure with through silicon via (TSV) technology is emerging as a key issue in microelectronic packaging industry, and electrical reliability has become one of the main technical subjects for the TSV designs. However, criteria used for TSV reliability tests have not been consistent in the literature, so that the criterion itself becomes a technical argument. To this end, this paper first performed several different reliability tests on the testing packaging with TSV chains, then statistically analyzed the experimental data with different failure criteria on resistance increasing, and finally constructed the Weibull failure curves with parameter extractions. After comparing the results, it is suggested that using different criteria may lead to the same failure mode on Weibull analyses, and 65% of failed devices are recommended as a suitable termination for reliability tests.

Low-Capacitance Through-Silicon-Vias With Combined Air/SiO2Liners

Through-silicon-vias (TSVs) with air-gap insulators have the advantages of low capacitance and low thermal stress. This paper reports the design, fabrication, and characterization of new TSVs with combined air/SiO2 insulators. Sacrificial technologies based on heat decomposition of poly(propylene carbonate) and reactive ion etching of benzocyclobutene have been developed to fabricate uniform and high aspect-ratio air gaps. Air gaps with a thickness of 0.8 $\mu \text{m}$ and an aspect ratio of 62.5:1 have been successfully fabricated. Measurement results show that the SiO2 liner is able to eliminate the impacts of residues of the sacrificial polymers, and the TSVs with air/SiO2 have low capacitances and leakage currents at both room temperature and high temperature, constant minimum capacitance, and good temperature stability.

Modeling and Electromagnetic Analysis of Multilayer Through Silicon Via Interconnect for 3D Integration

Convergence of multiple functions in a single device is the main thought behind the development of the current electronic trends. So, the requirement for higher integration in electronic devices has become more important in present days than in the past. Through silicon via (TSV) is the latest interconnect technology proposed mainly for higher integration and higher frequency. Therefore, cross talk will be an essential issue that needs to be taken into consideration. In this paper, we study the electrical property of a GSSG (S-Signal, G-Ground) TSV structure and propose the accurate lumped model which can be used to predict the TSV performance. Since more dies are used within one chip, the single layer TSV cannot satisfy the requirement. Hence, we propose the multilayer TSV structure and study how the bump radius, bump height, and underfill material affect the TSV transmission performance and coupling issue, so that we can conduct a good TSV design. Furthermore, three multilayer 4 × 4 TSV array models are proposed with different GS distribution to analyze the detailed coupling results.

Enabling Resist Processing Technologies for Advanced Packaging

The increasing adoption of advanced wafer-level packaging (WLP) technologies and high density interposer concepts clearly reflect the permanent need for form factor reduction, smaller process geometries and higher-count I/O on ICs. Currently, several strategies are being pursued to achieve these goals. The most promising approaches are summarized under the concept of three-dimensional integrated circuits (3D-IC) and three-dimensional wafer level packaging (3D-WLP) technology. A key component for 3D device integration schemes is the requirement of vertical through-silicon-via (TSV) interconnections that enables electrical through-chip communication through stacks of vertically integrated layers on the wafer scale. Ultimately, the use of TSVs also enables higher performance and smaller package sizes. In order to realize TSV connections, a series of process steps is required such as the thinning and bonding of the wafer to a carrier prior to the formation of through-wafer vias, followed by the passivation and metallization of the vias. Despite the potential benefits associated with the integration of TSVs also significant challenges have to be overcome. One of the greatest challenges for present and even more for upcoming TSV design strategies still remains the processing of photoresist and other functional polymers at and within TSV geometries. To this day, it is still very difficult to achieve a conformal polymer coating in deep cavities, along steep side walls and especially within the extreme aspect ratios of TSV. Mainly this is due to the fact that standard surface coating methods such as spin coating were just not developed to meet the requirements posed by these high aspect ratio microstructures. New and innovative approaches are needed to meet these new challenges. Spray coating is one of the most promising technologies to overcome current barriers. However, even most of the available spray deposition equipment is facing its limits with steadily decreasing via diameters and increasing aspect ratios on the other hand. Successively, the multitude of these challenging technological developments in the 3D-IC and wafer-level packaging area has created the demand for innovative manufacturing approaches, new equipment and related tools. Herein we present our new EVG ®NanoSprayTM coating technology with unique capabilities to overcome the present limits of conformal resist coating over extreme topography. We demonstrate one particularly promising application for conformal polymer coatings; as an annular lining at the interface between the conducting metal filling in the TSV and the silicon wafer. The intrinsic properties of the polymer allow a TSV design solution that is more forgiving on coefficient of thermal expansion (CTE) mismatch-induced stress between the silicon substrate and the interfacing metal. Consequently, this new type of polymer buffered TSV interconnect design promises to significantly reduce thermal stress-induced TSV delamination as one of the dominant failure modes for 3-D interconnects. We further demonstrate the application of EVG ®NanoSprayTM as enabling coating technology for llithographic processing of conformal coated TSVs. The patterning of thin photoresist layers at the bottom of vias and along the steep sidewalls of deep cavities allows for more degrees of freedom in electrical contact formation. The presented EVG ®NanoSprayTM coating technology opens new dimensions in advanced wafer level packaging and provokes reconsidering prevailing limitations in interconnect design.

Air-gap-based RF coaxial TSV and its characteristic analysis

Many 3D IC applications such as MEMS and RF systems require Through-Silicon Via (TSV) with operations for high-speed vertical communication. In this paper, we introduce a novel air-gap coaxial TSV that is suiTab. for such RF applications. Firstly, the detailed fabrication process is described to explain how to acquire such a structure. Then, an Resistor Inductance Conductance Capacitance (RLGC) model is developed to profile the transverse electromagnetic field effect of the proposed air-gap TSV. The model is further verified by a 3D field solver program through the S-parameter comparison. With reference to the numerically simulated results, this analytical model delivers a maximum deviation of less than 6&. on the conditions of varying diameters, outer to inner radius ratios, and SU-8 central angles, etc. Taking advantages of scalability of the model, a number of air-gap-based TSV designs are simulated, providing 1.6∼4.0 times higher bandwidth than the conventional coaxial TSVs and leading to an efficient high frequency vertical RF interconnection solution for 3D ICs.

Thermo-Mechanical Design Rules for the Fabrication of TSV Interposers

The through-silicon-via (TSV) interposer is expected to be the driving vehicle for 2.5-D integrated circuit integration. Although a number of studies have been reported on the thermo-mechanical reliability of TSVs, it remains difficult to justify whether a TSV design or an interposer design is manufacturable or not because we still lack experimental reliability data. This investigation provides important experimental data as well as a series of correlation studies by finite element (FE) simulations. A 2-D analytical solution is also examined to help understand the physics of the problem. Regarding the experimental results, wafer cracking is observed for TSV arrays with large diameters and small pitch-to-diameter ratios after annealing at 300°C. The critical strength to wafer cracking is determined to be 388 MPa from some FE analyses. Through analytical considerations, the influence of TSV diameter on wafer cracking is found to rely on the contributions from the dielectric layer thickness and also the barrier layer thickness. An empirical model for the design of copper-filled TSV interposers is ultimately generated based on the modification of the 2-D solution.

RF-TSV design, modeling and application for 3D multi-core computer systems

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.

GHz EMI Characteristics of 3D Stacked Chip PDN with Through Silicon Via (TSV) Connections

GHz electromagnetic interference (EMI) characteristics are analyzed for a 3dimensional (3D) stacked chip power distribution network (PDN) with through silicon via (TSV) connections. The EMI problem is mostly raised by P/G (power/ground) noise due to high switching current magnitudes and high PDN impedances. The 3D stacked chip PDN is decomposed into P/G TSVs and vertically stacked capacitive chip PDNs. The TSV inductances combine with the chip PDN capacitances produce resonances and increase the PDN impedance level in the GHz frequency range. These effects depend on stacking configurations and P/G TSV designs and are analyzed using the P/G TSV model and chip PDN model. When a small size chip PDN and a large size chip PDN are stacked, the small one's impedance is more seriously affected by TSV effects and shows higher levels. As a P/G TSV location is moved to a corner of the chip PDNs, larger PDN impedances appear. When P/G TSV numbers are enlarged, the TSV effects push the resonances to a higher frequency range. As a small size chip PDN is located closer to the center of a large size chip PDN, the TSV effects are enhanced.

Miniaturization of a Wireless Sensor Node by Means of 3D Interconnects

This work presents an advanced sensor node for direct tire pressure monitoring with an overall size below 1 cm3, where the applied components are arranged in a 3D integrated stack for high compactness, improved thermal behavior, and enhanced robustness for pressure, inertia, and temperature sensing. The utilized through silicon via (TSV) technology is introduced and the wide range of resulting issues for the design of a sensor node are considered. In particular, the radio frequency (RF) characteristics of TSVs are investigated in detail focusing on their electrical efficiency. Finally an optimized TSV design is presented, which allows the connection of a Bulk Acoustic Wave (BAW) resonator with an impedance of 2 kΩ at 2.1 GHz. Thus, all required types of interconnections within the sensor node can be realized by means of the TSV technology.

Enabling Robust Copper Fill of High Aspect Ratio Through Silicon Vias

Today's Through Silicon Via (TSV) processes are limited to aspect ratios of 10:1. High performance logic devices drive the need for aspect ratios approaching 20:1 in order to achieve the desired performance while simultaneously reducing costs. The reduced via area required on the wafer enables the designer to utilize less real estate on the die to reduce cost or to potentially add redundant vias to improve yield. However, current conventional processes and techniques are not capable of achieving robust fill on aspect ratios greater than 12:1. This presentation will highlight the technical challenges in achieving robust copper fill on super high aspect ratio TSV structures. Additionally, a compelling, economic solution pathway will be presented that integrates a low temperature conformal high quality dielectric isolation layer, a high step coverage Cu barrier / seed technology and a void free high speed electroplating process with a wide process window that could accelerate the adoption of the high aspect ratio TSV design schemes.

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

As traditional CMOS scaling becomes progressively more difficult and less beneficial to overall system performance, three-dimensional silicon integration technologies have begun to receive considerable attention. An advanced packaging solution based on a thin silicon carrier has been developed to provide interconnection between integrated circuits (ICs) and other devices at densities. far beyond those of current first-level packaging. The silicon carrier employs fine-pitch Cu damascene wiring, high-density solder interconnections, and through-silicon vias (TSVs). A key enabling technology element is the TSV, which may be naturally scaled to provide vertical interconnection in stacked ICs as well as silicon carriers. In this paper, we discuss the evolution in both TSV design and process flow that has led to TSV technology which produces vias with resistances on the order of 10-20 mΩ and yields on the order of 99.99% at wafer level in a research laboratory environment. Two generalized process approaches to forming TSVs are discussed, the vias-first and the vias-last methods, along with related advantages and potential drawbacks of each. Improvement to these process, flows and structures is afforded by simple changes of via geometry from cylindrical to annular or from annular to multibar. While various TSV metallurgies are reviewed, tungsten is shown to be a nearly optimal choice. Results on via resistance, electrical yield, and current-carrying capacity are covered. The use of electrical modeling to predict structures with superior electrical and mechanical properties is also described.