through-Si Vias Research Articles

Full elastic strain and stress tensor measurements from individual dislocation cells in copper through-Si vias.

Nondestructive measurements of the full elastic strain and stress tensors from individual dislocation cells distributed along the full extent of a 50 µm-long polycrystalline copper via in Si is reported. Determining all of the components of these tensors from sub-micrometre regions within deformed metals presents considerable challenges. The primary issues are ensuring that different diffraction peaks originate from the same sample volume and that accurate determination is made of the peak positions from plastically deformed samples. For these measurements, three widely separated reflections were examined from selected, individual grains along the via. The lattice spacings and peak positions were measured for multiple dislocation cell interiors within each grain and the cell-interior peaks were sorted out using the measured included angles. A comprehensive uncertainty analysis using a Monte Carlo uncertainty algorithm provided uncertainties for the elastic strain tensor and stress tensor components.

High Shear Speed Characteristics of Sub-100 μm Low Alpha SAC105 Solder Bump Directly Fabricated on Cu Filled Through Si Via for 3D Integration

Soft errors in microelectronics devices, responsible for the malfunction of electronic systems, have become a hot issue for miniaturized and high-density packaging like three-dimensional (3D) packaging. Low alpha solder generates very few α-radiation-caused errors and malfunction in electronic devices compared with regular solder. It can improve performance and reliability of through-Si-via (TSV) packaging, prompting the need to adopt low alpha solder for bumping in TSV packaging. TSV technology has emerged as a popular choice for 3D packaging and chip stacking. In this study, the bonding properties of low alpha solder on Cu-filled TSV were investigated. TSVs were fabricated in a Si wafer by deep reactiveion etching, and Cu was filled in the via by electroplating using the periodic pulse-reverse current waveform. Cu filling in the via was achieved in 4 h without any defects at a cathodic current density of −8 mA/cm2. The LC-3 class of a low alpha solder ball (alpha emission < 0.05 cph/cm2) having a composition of Sn-1.0 wt.% Ag-0.5 wt.% Cu (SAC105) and a diameter of 80 μm was reflowed on the Cu-filled TSV to form the solder bump. High-speed shear test was performed on the bumped low alpha solder ball to assess the shear strength and to investigate the fracture mode. The shear strength of the low alpha solder bump showed a maximum value of 369.63 mN at 1.0 m/s shearing speed and 17.6 μm tip height. The fraction of brittle fracture increased with increasing shearing speed.

Three-dimensional micro-Raman spectroscopy mapping of stress induced in Si by Cu-filled through-Si vias

Three-dimensional (3D) micro-Raman spectroscopy mapping of mechanical stress induced by Cu through-Si vias (TSVs) in the Si substrate is reported. The 3D-map is obtained by combining 2D-maps measured at different positions along the cross-section of TSVs. The results highlight the relaxing effect of cross-sectioning on the stress field and show that conventional 2D-measurements on cross-sections can seriously underestimate the real stress values. Using this technique, the impact of post-plating anneal on the TSV stress is measured and shown to correlate very well with TSV stress data obtained from wafer bending experiments.

Thermally stable ZrN/Zr3N4 bilayered barrier system for through-Si-via process

We propose the use of a system composed of successively deposited ZrN (diffusion barrier)/Zr3N4 (insulating layer) barrier layers with the same constituents in the via-last through-Si-via (TSV) process. A preliminary examination of low-temperature-deposited Zr3N4 films by reactive sputtering reveals that the films show good characteristics as an insulating layer comparable to those of SiNx films prepared at low temperatures. The TSV model system of Cu/ZrN/Zr3N4/Si tolerates annealing at 500 °C for 60 min without any change in structure and/or configuration, showing good thermal stability as a candidate TSV barrier system.

Role of Bath Composition in Electroless Cu Seeding on Co Liner for through-Si Vias

To enable Cu fill of through-Si vias (TSV) with a high aspect ratio (diameter 3 μm, depth 50 μm), the electroless deposition of a Cu seed on Co liner material was investigated. The reducing agent glyoxylic acid showed anodic oxidation on Co, which did not appear for the case of formaldehyde. From electrochemical analysis, an optimized bath composition caused limited Co corrosion during the electroless Cu nucleation phase. The concentration ratio of the complexing agent (ethylenediaminetetraacetic acid) and copper was found to strongly impact the liner corrosion; in case free complexing agent is present in the bath, the Co corrosion was assisted by complexation and replacement reactions. A continuous seed layer could be deposited in the entire TSV, which enabled the filling by electrochemical deposition (ECD). The substantially thinner total copper overburden generated for this combination of a wet-chemical seed deposition and an ECD fill process contributes to a cost reduction of its chemical mechanical polishing (CMP).

Development of Glyoxylic Acid Based Electroless Copper Deposition on Ruthenium

High aspect ratio through Si via (TSV) has received much attention as a process integration route to reduce stress build up around the TSV, leading to a small keep-out zone where device performance is impacted. High aspect ratio TSV requires alternative barrier and seed process, because physical vapor deposition (PVD) is facing difficulties yielding continuous layer in such structures. Combining the excellent conformality of ELD in high aspect ratio TSV and atomic layer deposition of barrier and liner, is seen as a potential process route [1]. Glyoxylic acid is a non-toxic reducing agent for ELD-Cu on Ru [2]. In previous work, we found that the nucleation mechanism is catalyst reaction [2]. In this paper, the different anodic reaction of formaldehyde and glyoxylic acid on Ru was compared by polarization analysis. Furthermore, the purity was evaluated after adding stabilizer in the ELD bath. The demonstration of deposition in TSV was performed using 3 × 50 µm TSV. Figure 1 shows polarization analysis of glyoxylic acid and formaldehyde on Ru and PVD-Cu as a reference. All the measurements showed anodic oxidation. It indicates that the driving force of anodic oxidation of glyoxylic acid and formaldehyde is catalysis of Ru and Cu. Although the anodic oxidation of glyoxylic acid on Ru was weaker than formaldehyde, glyoxylic acid showed similar potential on Ru (-0.63 V) and Cu surface (-0.68 V) at -0.01 mA/cm2. They were -0.63 V on Ru and -0.83 V on Cu for the case of formaldehyde. Furthermore, we found that 2,2’-bipyridyl worked as stabilizer, brightener and suppressor in the glyoxylic acid based bath. Figure 2 shows surface morphology, roughness and purity of ELD Cu using various concentrations of 2,2’- bipyridyl. The roughness and the purity of copper films improved by adding 2,2’-bipyridyl in the bath. The high purity of Cu might help to reduce void generation during the annealing process after filling. Figure 3 shows cross sectional TEM images of TSV after ELD on Ru. The ELD layer was defect free and worked as a seed layer for electrodeposition of copper. The advantage of depositing a conformal seed layer is that it also reduces the total Cu overburden, which is to be removed by CMP.Reference[1] F. Inoue, H. Philipsen, A. Radisic, S. Armini, Y.Civale, S. Shingubara, and P. Leunissen Journal of The Electrochemical Society, 159 (7) D437-D441 (2012)[2] F. Inoue, H. Philipsen, A. Radisic, S. Armini, Y. Civale, P. Leunissen, M. Kondo, E. Webb, and S. Shingubaraba, Electrochimica Acta 100 (2013) 203– 211

Stability Evaluation of Non-Agglomerated Pd Nanoparticle Catalysts for Electroless Deposition

Conventional physical vapor depositions (PVD) of diffusion barrier and seed layers have been facing its limits of application for high aspect ratio of through Si via (TSV). Electroless plating (ELP) is an alternative candidate for TSV metallization because of their promising potential, e.g. conformal deposition property, cost reduction possible and low temperature.In order to deposit ELP film on dielectric layer, catalyst process is the most important. In general, Sn-Pd process has been used for catalyst process of ELP. In addition, palladium nanoparticles (Pd-NPs) showed high density of adsorption, which assisted achievement of thin and conformal ELP formation in high aspect ratio TSV [1, 2].To deposit electroless plating, high density of adsorption of Pd-NPs is required. Furthermore, in actual manufacturing process, long term stability that assumed repeated use is strongly desired.In this study, we have developed the Pd-NPs to shorten the processing time in TSV and disperse in water for a long period. We found that the addition of compound A(COM-A ) or B enable to significantly improve the stability without losing the adsorption property of Pd-NPs.Fig.1 shows the time transient of the diffusion coefficient of Pd-NPs with and without COM-A in solution which were stored at 25 °C. Diffusion coefficient of the particles were measured by dynamic light scattering (DLS).In the Pd-NPs solution without COM-A, the diffusion coefficient of the particles gradually decreased. However, the diffusion coefficient of particles maintained a constant value in the Pd-NPs solution with COM-A.According to the Stokes-Einstein equation, if the temperature and viscosity of a solution is constant, the decreasing of the diffusion coefficient indicates that the particles aggregate each other. Thus, the substantial catalyst particle number can be decreased for the case without COM-A.Fig.2 shows SEM images of Pd-NPs adsorbed on blanket SiO2. The Pd-NPs solutions were stored 40 days at 25 °C before use. In the case of Pd-NPs solution with COM-A, there is no agglomeration of the particles on the sample. On the other hand, particles agglomeration were occurred in case without COM-A.In addition, we also found that the addition of COM-A is possible to dispersed again agglomerated Pd-NPs. These results suggest that the Pd-NPs solution with COM-A is applicable to actual manufacturing process.[1] F. Inoue, S. Shingubara, et al., ECS Transactions, 25 (38) 31-36 (2010)[2] F. Inoue, S. Shingubara, et al., Electrochimica Acta 82 (2012) 372-277

Precipitation Behaviors of Rapid Thermal Annealing Treated Silicon Wafers under Various Thermal Cycles

For decades, oxygen precipitates in Cz silicon wafers have been a subject of defect engineering to optimize device yields and performance at both current high volume manufacturing and future generation nodes. With the ability of precipitates capturing metallic impurities, a well controlled built-in intrinsic gettering (IG) provides a self-insurance protecting fabs from suffering unexpected yield loss caused by metal contamination outside the control limit [1]. Such IG sinks traditionally are created, either by RTP or conventional furnace heat treatments, quite deep in the bulk, resulting in a wide denuded zone (DZ). This scheme has worked perfect for most devices with monolithic integration as fast diffusing metals travel the distance equal to the DZ depth quite easy. However, the industry is increasingly adopting 3-D integration, stacking multiple chips vertically using through Si via (TSV) techniques. Multichip stacking requires each die to be thinned substantially by back grinding down to 50um or even <30um, depending on the number of stacked dies. This results in either complete or major loss of IG sinks along with the bulk removal of the wafer. In this respect, IG with a shallower DZ is desired so that a sufficient amount of IG sinks are retained even after extensive thinning. On the other hand, the effect of oxygen precipitation on the yield strength is increasingly receiving attention as photolithography overlay is becoming more sensitive to local deformation [2]. A precisely controlled high density of precipitates would be desirable in this regard.In this report, we demonstrate that a 2-step Rapid Thermal Annealing (RTA) treatment in NH3 and Ar gas is capable of producing a high density of precipitates in an extremely uniform profile in the 300mm silicon wafers under CMOS-like thermal cycles. The RTA treatment is a special variant of MDZ® that has been widely adopted in the industry for >10 years [1, 3]. Figure 1 shows typical depth profiles of precipitates in the high oxygen material after through a CMOS thermal simulation and after a subsequent extra growth cycle. Adding the extra growth cycle was necessary for the sake of ensuring all the existing precipitates to be detectable as the metrology tool (laser scattering tomography) would otherwise miss those sub-threshold size in the count, especially in the case of the lower oxygen concentration material. Quite a uniform density of precipitates is formed at the depth of around 7 microns and extended to the entire thickness of the wafers with the maximum density around 8x109/cm3 and 7x109/cm3 in the cases of higher and lower oxygen concentration materials, respectively. It can also be seen that in the case of higher oxygen material the full cycle of the D simulation has effectively grown the precipitates so about 70% of the precipitate distribution was detectable without going through a growth cycle (the D2 curve). These results are pretty consistent with the previous work reported by co-authors, where the uniform density of precipitates is explained as a result of the nitride layer blocking vacancy sinking to the wafer surface [4]. The precipitation sites are created by vacancy aggregation in the course of fast post-RTA cooling. The radial distribution of oxygen precipitates is remarkably uniform, as shown in Fig. 2 (a) and (c). In comparison, the as-grown wafers (b and d) resulted in a large variation, especially in the high oxygen material, which is due to the inhomogeneous distribution of point defects formed during crystal growth. The result clearly demonstrates that the 2-step RTA eliminated the crystal originated variability, very effectively.In summary, adding a 2-step RTA treatment produces a high density precipitates near surface, uniformly both vertically and laterally, guaranteeing a <20um thick layer of IG sinks to be retained even after through wafer thinning to 30um.

Observation of lattice spacing fluctuation and strain undulation around through-Si vias in wafer-on-wafer structures using X-ray microbeam diffraction

Spatial fluctuations of the Si 004 lattice spacing, strain, and lattice tilt around through-Si vias (TSVs) in wafer-on-wafer (WOW) structures annealed at different temperatures were quantitatively investigated using X-ray microbeam diffraction. The TSVs were found to induce spatial fluctuations in the base and bonded wafers, and a strain of approximately 0.1% and lattice tilt with a long undulation period of 40 µm were clearly observed. Furthermore, annealing at approximately 100 °C effectively reduced the spatial fluctuation, strain, and lattice tilt in the WOW structure.

Preparation of nanocrystalline HfNx films as a thin barrier for through-Si via interconnects in three-dimensional integration

We propose a barrier material applicable to the through-Si via (TSV), a key technology for the three-dimensional stacked integration, from the point of view of materials science, including excellent thermal and chemical stability, low resistivity, and conformability to thin-film formation. We examine N-rich HfNx films consisting of nanocrystalline grains as candidate barrier materials. The HfNx film consisting of a HfN single phase without contaminants shows excellent phase stability and low resistivity. The barrier in the Cu/HfNx/SiO2/Si model configuration shows excellent barrier properties with little structural change and without excess solid-phase reactions and/or diffusion due to annealing. A 5-nm-thick thin barrier applicable to TSV downsizing in the future is thus effective in satisfying the fundamental requirements of a good needed barrier, stemming from the low-temperature process of TSV technology.

Fabrication and Testing of a TSV-Enabled Si Interposer With Cu- and Polymer-Based Multilevel Metallization

An electrically functional freestanding Si interposer for 3-D heterogeneous integration applications is designed and successfully fabricated. The interposer employs multilevel metallization (MLM) on the frontside of the wafer and Cu-filled through-Si vias (TSVs) and MLM on the backside. The MLM structures use electroplated Cu and polymer dielectrics of the type used in wafer-level packaging. The fabrication flow of the 3-D interposer test vehicle incorporates the formation of TSVs, the deposition and patterning of two routing levels of frontside MLM, wafer thinning, and the deposition and patterning of backside MLM. TSVs 80 μm in diameter, 315 μm in depth, and 80 μm in diameter, 265- μm depth (4:1 or 3:1 aspect ratio, respectively) are demonstrated. The frontside and backside MLM were formed with 3- μm-thick Cu routing layers and 5- μm-thick spin-on dielectric layers. Daisy chains consisting of 528 TSVs connecting the frontside and backside metal layers are tested for electrical continuity. Individual TSV operability exceeds 99.98%. Details of the MLM and TSV process modules, including thermal stabilization of Cu-filled TSVs and process integration required to successfully obtain the high TSV operability, are described.

Nucleation Kinetics of Electroless Cu Deposition on Ruthenium Using Glyoxylic Acid as a Reducing Agent

Glyoxylic acid is seen as a promising candidate to replace formaldehyde as reducing agent in electroless Cu baths. For deposition on ruthenium, the anodic reaction of glyoxylic acid has been evaluated and compared to formaldehyde using linear sweep voltammetry. Significant differences were observed for the deposition of copper on ruthenium. First of all, a faster nucleation was inferred from open-circuit potential measurements, which is beneficial as it reduces the total process time. Secondary, we found 2,2′ bipyridyl worked as stabilizer and brightener in this glyoxylic acid-based electroless bath. Thirdly, the purity of the copper films improved when 2,2′ bipyridyl was present in the solution. Using the optimized composition, we demonstrate a conformal Cu seed layer deposition (∼100 nm) inside high aspect ratio (16.7) through-Si vias. This work shows the feasibility for electroless Cu seeding in a through-Si via metallization sequence.

Through-Si-via (TSV) Keep-Out-Zone (KOZ) in SOI Photonics Interposer: A Study of the Impact of TSV-Induced Stress on Si Ring Resonators

Si photonic devices are sensitive to the change in refractive index on the Si-on-insulator (SOI) platform. One of the critical limitations in the compact 3D photonic integration circuit is the through-Si-via (TSV)-induced stress, which affects the performances of Si photonic devices integrated in interposer. We build a model to analyze and simulate the wavelength shift of the ring resonator caused by the effective-refractive-index change in the waveguide, arising from TSV-induced stress in the SOI interposer. Double-cascaded ring resonators integrated in the SOI interposer were fabricated and their wavelength shifts were characterized. The results show that the resonance wavelength shift on the order of 0.1 nm can be caused by the TSV-induced stress for , where d and R are the distance between the TSV and the Si waveguide, and the radius of TSV, respectively. This shift results in performance deviation from the target of design. Finally, this paper proposes a TSV keep-out-zone for the Si photonic ring resonator and a compact scaling of the SOI photonics interposer.

Relationship Between Wafer-Level Warpage and Cu Overburden Thickness Controlled by Isotropic Wet Etching for Through Si Vias

In this paper, we developed an isotropic wet etching process in a capsule-type bevel etch chamber to reduce a Cu overburden of through Si via (TSV) for less wafer-level warpage with 300 mm wafers. We report the relationship between the wafer-level warpage and the Cu overburden thicknesses controlled by the isotropic wet etching with diluted solution of hydrogen peroxide and sulfuric acid, which is widely used for Cu wet etching. After Cu filling by electroplating, there are humps at the top of the TSVs; therefore, the isotropic wet etching can be considered as a solution to etch away the Cu overburden without any damages on the TSVs. We modified the capsule-type bevel etch chamber to avoid serious attack on TSVs at the center area of the wafer caused by the etchant delivery path. We also adjusted the process parameters to have a controllable Cu etch rate. The etch rate of ~ 0.2 μm/s and the uniformity of ~ 3% were achieved. The overburden was able to be etched up to 3 μm m from the initial Cu overburden. While the Cu overburden decreased during the isotropic wet etching, the TSVs were protected from the etchant because of the humps at the top of the TSVs. After the Cu electroplating, there was a grain size difference between the Cu at TSV and the Cu at field area. Because the microstructural difference caused a galvanic corrosion during the wet etching, the etch rate of the adjacent Cu around TSV was faster than the Cu at any other area. That resulted in exposure of dielectric layer at the adjacent area around TSVs when the Cu overburden was etched heavily. It may be another protection mechanism of TSV during the isotropic wet etching. The wafer-level warpage of the wafer with the Cu overburden etched up to 3 μm after the annealing decreased by 50% from that of the wafer with the initial Cu overburden. The wafer-level warpage exhibited a linear relationship with the Cu overburden thickness controlled by the isotropic wet etching.

3D IC 열관리를 위한 TSV Liquid Cooling System

(2013년 8월 26일 접수: 2013년 9월 9일 수정: 2013년 9월 16일 게재확정 )Abstract: 3D integrated circuit(IC) technology with TSV(through Si via) liquid cooling system is discussed. As a devicescales down, both interconnect and packaging technologies are not fast enough to follow transistor's technology. 3D ICtechnology is considered as one of key technologies to resolve a device scaling issue between transistor and packaging.However, despite of many advantages, 3D IC technology suffers from power delivery, thermal management, manufacturingyield, and device test. Especially for high density and high performance devices, power density increases significantlyand it results in a major thermal problem in stacked ICs. In this paper, the recent studies of TSV liquid cooling systemhas been reviewed as one of device cooling methods for the next generation thermal management.Keywords: TSV, Liquid Cooling, Interconnect, 3D IC, Thermal management

A study of the mechanisms causing surface defects on sidewalls during Si etching for TSV (through Si via)

In this paper we report three mechanisms causing surface defects on Si sidewalls during Si etching for TSV. The first mechanism causing surface defects was a downward surface-defect formation due to the participation of the residual polymerizing gas in the transition periods between passivation steps and etch steps. The second mechanism was an upward surface-defect formation due to etchant attacking the interface between the Si and the sidewall polymer. Although the sidewall polymer was thick enough to protect the Si surface, it was not possible to avoid surface defects if the etch step was not switched to the following passivation step in time. The third mechanism was a sponge-like surface-defect formation caused by either poor polymer depositions or voids inside the sidewall polymer. The sponge-like surface defects were formed by Si isotropic etching through the weak points of the sidewall polymer. All three surface defects were considered as the major factors on TSV integration and packaging reliability issues.

Electroless Cu deposition on atomic layer deposited Ru as novel seed formation process in through-Si vias

High aspect ratio through Si vias (φ 2μm, depth 30μm) have been filled completely by Cu electroplating using an electroless deposited Cu seed layer. The electroless Cu deposition was carried out on ALD–Ru; the time transient of the mixed potential on Ru showed a catalyst type of behavior. The ELD–Cu, which was deposited inside TSVs along their sidewalls, was defect free and worked as a seed layer for electrodeposition of Cu to fill the structure. With a conventional method, such as PVD–Cu, it is challenging to deposit a seed in such structures. The adhesion strength of this ELD–Cu film on ALD–Ru was measured to be >100MPa. These coupon-scale results show the feasibility of electroless deposition in TSV processing.

On the thermal stability of physically-vapor-deposited diffusion barriers in 3D Through-Silicon Vias during IC processing

Barrier reliability in 3D through-Si via (TSV) Cu interconnections requires particular attention as these structures come very close to the active devices and Cu diffusion into the silicon substrate would significantly affect device performance. This work focuses on a via-middle process flow, which implies processing of the 3D-TSV after the front-end-of-line (FEOL) process, but before the back-end-of-line (BEOL) interconnect process. This results in several high temperature processing steps after TSV fabrication, including a final device wafer sintering step, generally in the 400 °C range. Thus, it becomes essential to study the stability of the TSV Cu-barrier at these temperatures to ensure a reliable integration of 3D TSV in CMOS wafers. TSV aspect ratios can vary as function of the integration scheme, for instance in a via-last or via-middle flow, and thus barrier continuity requires conformality which guarantees the presence of a diffusion barrier until the bottom of the TSV. Target conformality can either be obtained by PVD, typically for TSV A.R. ⩽ 10:1. We report on the thermal stability of Ta, and Ti barriers and we show that 5 nm PVD Ta barriers are thermally stable, while PVD Ti-barriers require thicknesses above 5 nm to guarantee their thermal stability.

Highly adhesive electroless barrier/Cu-seed formation for high aspect ratio through-Si vias

A conformal diffusion barrier was formed in a high aspect ratio through-silicon via using electroless plating. Dense adsorption of Pd nanoparticle catalyst on SiO2 assisted the formation of a thin electroless Co-W-B layer, upon which an electroless Cu seed layer could be deposited. The adhesion strength of the Co-W-B film was enhanced by reducing the film thickness, and the maximum strength was obtained at a thickness of 20nm. The Co-W-B layer exhibited good barrier properties against Cu diffusion to SiO2 after annealing at 300^oC, although slight diffusion of the Pd atoms in Cu was observed.

Transition from flip chip solder joint to 3D IC microbump: Its effect on microstructure anisotropy

As microelectronic industry develops 3D IC on the basis of through-Si-vias (TSV) technology, the processing and reliability of microbumps, which are used to interconnect the stacking chips, is being actively investigated. Due to the reduction in size of microbumps, the diameter is about one order of magnitude smaller than that of flip chip solder joints, and the volume is 1000 times smaller. Its microstructure and in turn its properties will be anisotropic because the number of grains in a microbump becomes very small. Its statistical failure will have a wide distribution because of anisotropy, including early failure. This review addresses this issue and the remedy.