Threshold Voltage Research Articles

Nanocrystal Materials for Resistive Memory and Artificial Synapses: Progress and Prospects.

Resistive random-access memory (RRAM) is considered to be the most promising next-generation non-volatile memory because of its low cost, low energy consumption, and excellent data storage characteristics. However, the on/off (SET/RESET) voltages of RRAM are too random to replace the traditional memory. Nanocrystals (NCs) offer an appealing option for these applications since they combine excellent electronic/optical properties and structural stability and can address the requirements of low-cost, large-area, and solution-processed technologies. Therefore, the doping NCs in the function layer of RRAM are proposed to localize the electric field and guide conductance filaments (CFs) growth. The purpose of this article is to focus on a comprehensive and systematical survey of the NC materials, which are used to improve the performance of resistive memory (RM) and optoelectronic synaptic devices and review recent experimental advances in NC-based neuromorphic devices from artificial synapses to light-sensory synaptic platforms. Extensive information related to NCs for RRAM and artificial synapses and their associated patents were collected. This review aimed to highlight the unique electrical and optical features of metal and semiconductor NCs for designing future RRAM and artificial synapses. It was demonstrated that doping NCs in the function layer of RRAM could not only improve the homogeneity of SET/RESET voltage but also reduce the threshold voltage. At the same time, it could still increase the retention time and provide the probability of mimicking the bio-synapse. NC doping can significantly enhance the overall performance of RM devices, but there are still many problems to be solved. This review highlights the relevance of NCs for RM and artificial synapses and also provides a perspective on the opportunities, challenges, and potential future directions.

Characteristics of electric breakdown in repeated frequency pulse with microcavity effect

The electric breakdown characteristics in microcavity structure under repeated frequency pulse (RFP) were studied, and the physical mechanism was investigated quantitatively based on the full statistical distribution of breakdown time delay obtained in step rectangular pulse (SRP). Experimentally, microcavity heights of 300, 800, and 2000 μm were used. In RFP, the occurrence of breakdown becomes probabilistic when the time delay t d and pulse width t PW satisfy the condition t s-min < t PW < t s-max. The breakdown probability increases with pulse width, and the probability distributions are roughly exponential and Gaussian at pulse frequencies of 3 and 1000 Hz, respectively. We found the results are attributed to the similar distributions of time delay in RFP and SRP with similar afterglow time and pulse voltage, and the equal distributions of breakdown probability (with pulse width) and cumulative probability of t d in RFP. The microcavity effect will decrease the breakdown probability under given pulse width and voltage. Additionally, it is found that in RFP the increase of pulse width from 1 to 1000 μ s will decrease the threshold voltages at 0% and 100% breakdown probabilities, and the threshold voltage difference will decrease simultaneously to around 0, which results in the transition of breakdown feature from probability to certainty. This phenomenon is due to that the reduction of pulse voltage will increase the time delay significantly and meanwhile the variation rate of time delay with pulse voltage Δt d/ΔU w decreases sharply. The microcavity effect will cause the increase of threshold breakdown voltages at a given pulse width and frequency. Finally, it is found that in RFP the breakdown voltage will decrease with the rise of pulse frequency from 10° to 104 Hz, which is consistent with the variation of time delay with afterglow time (from 10−1 to 103 ms) in the memory curve measured in SRP under similar afterglow time. Overall, the microcavity effect will enhance the adsorption of charged and excited species by dielectric walls during afterglow period and enlarge the time delay in the following pulse breakdown, and then influence the RFP breakdown characteristics.

Metal inserted doping less dielectrically modulated TFET biomarker for SARs-CoV-2 detection

In this paper, a metal strip loaded doping less TFET (MS-DLTFET) biomarker with four cavities is proposed for SARs-CoV-2 detection virus. The results demonstrate that the proposed device offers an improved biomarker performance by introducing the charged plasma concept and the metal strips. The electrical parameters such as electron tunneling rate, drain current (Ids), current ratio (ION/IOFF), threshold voltage (Vth) are evaluated through simulations by immobilized dielectric constant (k) and charge density (ρ) of the bioelements in the nano-gap cavities. In addition, their sensitivity is also calculated with respect to air. The results depict that the proposed device tenders better performance in terms of Ids, ION/IOFF and Vth sensitivity as compared to existing devices. The device's response time under varying k and ρ values are investigated. The non-uniform cavity configurations formed due to steric hindrance effect are studied. It is found that concave configuration offers the best performance compared to other. Furthermore, the cavity size analysis is also performed to optimize the device performance.

Enhancement-Mode Carbon Nanotube Optoelectronic Synaptic Transistors with Large and Controllable Threshold Voltage Modulation Window for Broadband Flexible Vision Systems.

The development of large-scale integration of optoelectronic neuromorphic devices with ultralow power consumption and broadband responses is essential for high-performance bionics vision systems. In this work, we developed a strategy to construct large-scale (40 × 30) enhancement-mode carbon nanotube optoelectronic synaptic transistors with ultralow power consumption (33.9 aJ per pulse) and broadband responses (from 365 to 620 nm) using low-work function yttrium (Y)-gate electrodes and the mixture of eco-friendly photosensitive Ag2S quantum dots (QDs) and ionic liquids (ILs)-cross-linking-poly(4-vinylphenol) (PVP) (ILs-c-PVP) as the dielectric layers. Solution-processable carbon nanotube thin-film transistors (TFTs) showed enhancement-mode characteristics with the wide and controllable threshold voltage window (-1 V∼0 V) owing to use of the low-work-function Y-gate electrodes. It is noted that carbon nanotube optoelectronic synaptic transistors exhibited high on/off ratios (>106), small hysteresis and low operating voltage (≤2 V), and enhancement mode even under the illumination of ultraviolet (UV, 365 nm), blue (450 nm), and green (550 nm) to red (620 nm) pulse lights when introducing eco-friendly Ag2S QDs in dielectric layers, demonstrating that they have the strong fault-tolerant ability for the threshold voltage drifts caused by various manufacturing scenarios. Furthermore, some important bionic functions including a high paired pulse facilitation index (PPF index, up to 290%), learning and memory function with the long duration (200 s), and rapid recovery (2 s). Pavlov's dog experiment (retention time up to 20 min) and visual memory forgetting experiments (the duration of high current for 180 s) are also demonstrated. Significantly, the optoelectronic synaptic transistors can be used to simulate the adaptive process of vision in varying light conditions, and we demonstrated the dynamic transition of light adaptation to dark adaptation based on light-induced conditional behavior. This work undoubtedly provides valuable insights for the future development of artificial vision systems.

Performance enhancement of nanotube junctionless FETs with low doping concentration rings

Abstract To reduce the static power consumption of the NT JLFET and the effect of SCEs on the NT JLFET, A nanotube junctionless field effect transistor with cyclic low doping concentration regions (C NT JLFET) is proposed. Based on Sentaurus TCAD numerical simulations, the electrical properties of the C NT JLFET and the NT JLFET were comparatively investigated, and the effects of the length (LCD) and radius (RCD) of cyclic low doping concentration regions on the electrical properties of the C NT JLFETs were studied. The C NT JLFET reduces the gate-induced drain leakage (GIDL) due to lateral band-to-band-tunneling (L-BTBT) as compared to the NT JLFET. As the LCD or RCD increases, the off-state current decreases. In addition, the C NT JLFET suffers from fewer short channel effects (SCEs), such as threshold voltage roll-off, drain-induced barrier lowering and subthreshold swing deterioration, compared to the NT JLFET. The inhibition of L-BTBT and attenuation of SCEs by cyclic low doping concentration regions remains when the channel length of the C NT JLFET is shortened to 10 nm. The C NT JLFET are suitable for low power applications as they exhibit reduced L-BTBT and suffer from fewer SCEs.

Spin coating high‐k multicomponent (Al,Ti,V,Zr,Hf)Ox films with sub‐nm EOT for MOS‐based electronic devices

AbstractThe facile spin coating fabrication of high‐dielectric‐constant (high‐k) multicomponent (Al,Ti,V,Zr,Hf)Ox films with an equivalent oxide thickness of ≈0.95 nm and the investigation of their thermal stability and dielectric and electrical properties of the resulting advanced metal–oxide–semiconductor (MOS)‐based electronic devices are reported in this study. Various heating conditions, including drying following spin coating, annealing after drying, and forming gas annealing, were investigated to optimize the quality of the films and reduce film defects. The favorable film‐based MOS devices exhibited robust capacitance–voltage (C–V) and current–voltage (I–V) characteristics with a remarkable k value of approximately 62 at 1 kHz. The thermal stability of the films was affirmed through a rapid thermal annealing treatment at 900°C for 5 s and observation of nondegraded C–V and I–V curves. The electrical performance of the resulting MOS field‐effect transistors (MOSFETs), including a threshold voltage of 0.4 V, an on/off ratio of 106, a saturated mobility of 40.1 cm2 V−1 s−1, and a subthreshold swing of 66.7 mV dec−1, was obtained. Moreover, hole‐ and electron‐trapping measurements through negative and positive gate bias stress instabilities, respectively, indicate the reliable performance of our MOSFETs. Our results imply that solution‐based processes are promising for fabricating fundamental semiconductor devices.

Efficacy and safety of lumenless leads compared with stylet-driven leads for left bundle branch area pacing

Abstract Introduction Left Bundle Branch Area Pacing (LBBAP) was initially performed with lumenless leads (LLLs). In the last years, stylet-driven leads (SDLs) have emerged as an alternative. However, we are still lacking data comparing these two different approaches. Purpose To compare the efficacy and safety of LLLs Vs SDLs for LBBAP. Methods 116 patients who underwent LBBAP attempt in our institution were prospectively included (mean age 74 ± 9 years, 40 (34%) female). We recorded and analyzed baseline characteristics, procedural findings, LBB capture criteria, lead parameters, success rates and complications. A 6-month remote follow-up data was programmed in every patient. Results We analyzed 75 patients who received LLLs and 41 patients with SDLs. Baseline characteristics were similar in both groups (table 1). There were no significant differences regarding Paced QRS (114 ± 18 ms Vs 117 ± 19 ms, p = 0.36), presence of a LB potential (16 (21%) Vs 9 (22%), p = 0.93), V6 R-wave peak time (V6RWPT) (83 ± 15 ms Vs 82 ± 16 ms, p = 0.71) or V6–V1 inter-peak interval (40 ± 17 ms Vs 37 ± 13 ms, p = 0.37). Time to lead implant was also similar (37 ± 18 minutes Vs 37 minutes ± 13 minutes, p = 0.87). Mean pacing voltage threshold was higher for SDLs after implantation (0.71 ± 0.33 V Vs 0.86 ± 0.30 V, p = 0.02) and also at the 6-month remote follow-up (0.75 ± 0.28 V Vs 0.9 ± 0.34 V, p = 0,04). R-wave amplitude and impedance were also higher in SDLs (table 1). According to 2023 EHRA clinical consensus statement on conduction system pacing, we achieved confirmed LBBP in 63 patients (54%), likely LBBP in 30 patients (26%) and Left Ventricular Septal Pacing (LVSP) in 21 patients (18 %), with no differences between groups (table 1). After the 6-month follow-up, a higher probability of lead dislodgement was appreciated in the SDLs group (3 (7%) Vs 0 (0%), p = 0,01). Conclusions LLLs and SDLs are effective tools to perform LBBAP, achieving similar paced QRS and and success rates. SDLs were associated with slightly higher pacing threshold. After the 6-month follow-up, a higher probability of lead dislodgement was appreciated in the SDLs group.

Dynamic voltage mapping of the ventricular tachycardia substrate

Abstract Background Substrate mapping techniques that predict ventricular tachycardia (VT) isthmus components in sinus or paced rhythm are necessary as mapping during VT is often not possible. Voltage maps lack accuracy in differentiating scar, traditionally displayed as tissue &amp;lt;0.50mV, from bordering arrhythmogenic substrate. We developed a practical technique aiming to improve the utility of a voltage map during VT ablation, termed ‘Dynamic Voltage Mapping’ (DVM). Methods Consecutive patients with post-infarct VT at our centre underwent left ventricle (LV) voltage mapping (mean 4762 points) with Carto3 v.7® and a PentaRay®, or Ensite X® and a HD Grid mapping catheter. Both mapping systems offer algorithms that allow substrate activation maps to be superimposed and analysed on the surface of a voltage display (i.e. Carto Ripple Maps, or Ensite X activation vectors). DVM is a process that sequentially adjusts the voltage display to highlight scar tissue in areas devoid of Ripple bars, or in areas where activation vectors point in multiple unfathomable directions (‘vector disarray’). This approach is summarised in Figures 1 &amp; 2 and was retrospectively performed in all cases. This alternative scar voltage limit was termed the ‘DVM scar threshold’ (mV). Tissue below this threshold was termed ‘DVM-scar’, and tissue immediately surrounding (up to 0.5mV) was termed "DVM-Borderzone (BZ)". Results Twenty-five patients (mean age 64.4±11.0 years, 88% male, LV ejection fraction 31.8±6.9%, 16.4±8.5 years since infarct) were studied (n=15 Carto; n=10 EnSite). Across all cases, the mean shell area with voltage &amp;lt;0.50 mV was 36.8±20.3 cm2. The mean DVM scar threshold was 0.24±0.07 mV (Carto: 0.22±0.07 mV [range 0.12–0.35 mV]; EnSite: 0.26±0.08 [range 0.18–0.50 mV]). The mean DVM-scar area was 18.4±14.3 cm2, significantly smaller than the traditional 0.50mV value (p=0.0002). In the 8 patients where stable VT was mapped, the VT isthmus sites co-located within the DVM-BZ in all cases, exemplified in the figures. Pace-mapping at the DVM-BZ matched the remaining unmappable VT morphologies. Ablation lesions were retrospectively superimposed onto the DVM map and generally co-located within the DVM-BZ. No ablation was delivered in tissues &amp;gt;0.5mV. At median follow-up of 8.8 months, VT burden significantly reduced (median 3 episodes in 3-months pre vs. 0 post; p&amp;lt;0.001), with 76% of patients VT-free. Conclusion DVM appears to improve the delineation of the post-infarct VT substrate, and is feasible using two commercially-available mapping systems. The mean voltage threshold that differentiated DVM-Scar from BZ tissue was significantly lower than the traditional 0.50 mV scar definition, at 0.24mV, though ranged widely, suggesting that scar thresholds require individualised substrate definition. Targeted ablation of DVM-BZ may be effective at reducing future VT, though requires prospective validation.Figure 1Figure 2

A novel ballistic model for the subthreshold behavior of nanosheet transistors

A novel ballistic model for the subthreshold current of nanosheet transistors is successfully developed based on the Landauer approach with the three-dimensional number of channels. The ballistic threshold voltage can also be achieved through the calculated free charge density induced by the three-dimensional density-of-states equal to the substrate doping concentration. It indicates that under the low drain voltage corresponding to the Fermi distribution function, the subthreshold current is mainly governed by the low contact potential. However, under the high drain voltage corresponding to the Fermi distribution function, the thermal voltage, instead of the contact potential between the source and drain, initiates the subthreshold current. Besides subthreshold current and threshold voltage, the ballistic conductance and subthreshold swing are also revealed in the subthreshold conduction. It indicates that the thin silicon, thin gate oxide, heavy substrate doping density, and high work function will alleviate the ballistic effects, decrease the subthreshold current/swing, and increase the threshold voltage/ballistic resistance.

Volatile threshold switching devices for hardware security primitives: Exploiting intrinsic variability as an entropy source

In the age of the Internet of Things, the proliferation of edge devices has resulted in a significant increase in personal information that is susceptible to theft and counterfeiting at various stages of data communication. As a result, substantial attention has been focused on hardware (HW) security elements, such as the true random number generator and physical unclonable function. With the recent surge in research and development of emerging memristors, which exploit the inherent variability of these devices, there has been a notable increase in studies on HW security. Particularly, volatile threshold switch (TS) devices, which exhibit insulator/metal characteristics below/above a certain threshold voltage, show great promise as security devices due to their lower power consumption and higher cycling endurance compared to nonvolatile memory devices. Despite the promising attributes and increasing demand for TS devices for HW security, there remains a lack of a comprehensive overview covering various TS devices and their potential contributions to HW privacy. To address this gap, this review provides an encompassing analysis of different types of TS devices and their performance in HW security literature, providing insight into current limitations and the future prospects of HW security primitives based on TS devices.

Low Temperature (Down to 6 K) and Quantum Transport Characteristics of Stacked Nanosheet Transistors with a High-K/Metal Gate-Last Process

Silicon qubits based on specific SOI FinFETs and nanowire (NW) transistors have demonstrated promising quantum properties and the potential application of advanced Si CMOS devices for future quantum computing. In this paper, for the first time, the quantum transport characteristics for the next-generation transistor structure of a stack nanosheet (NS) FET and the innovative structure of a fishbone FET are explored. Clear structures are observed by TEM, and their low-temperature characteristics are also measured down to 6 K. Consistent with theoretical predictions, greatly enhanced switching behavior characterized by the reduction of off-state leakage current by one order of magnitude at 6 K and a linear decrease in the threshold voltage with decreasing temperature is observed. A quantum ballistic transport, particularly notable at shorter gate lengths and lower temperatures, is also observed, as well as an additional bias of about 1.3 mV at zero bias due to the asymmetric barrier. Additionally, fishbone FETs, produced by the incomplete nanosheet release in NSFETs, exhibit similar electrical characteristics but with degraded quantum transport due to additional SiGe channels. These can be improved by adjusting the ratio of the channel cross-sectional areas to match the dielectric constants.

Study of drain-induced channel effects in vertical GaN junction field-effect transistors

A normally-off vertical gallium nitride (GaN) junction field-effect transistor (JFET) is demonstrated in this work. The device shows an on/off current ratio of 3.6 × 1010, a threshold voltage (V TH) of 1.64 V, and a specific on-resistance (R ON,SP) of 1.87 mΩ·cm2. Drain-induced channel effects were proposed to explain the change in the gate current at different drain voltages. Drain current decline in the output characteristics and the reverse turn-on between drain and source can be explained by effects. A technological computer-aided design was used to simulate the change of the depletion region and confirm the explanation. Detailed analyses of the channel effects provide a reference for the design of novel structures. The characteristics at different temperatures demonstrated the stability of threshold voltage and specific on-resistance, thus indicating the great potential of applications in switching power circuits of vertical GaN JFETs.

Advancement of electro-optical properties through changes in the physicochemical composition of hybrid thin films by doping reduced graphene oxide into a sol-gel process solution.

A hybrid thin film was fabricated by doping graphene oxide into a sol-gel solution containing a mixture of zirconium, bismuth, and indium oxide. The thin film was fabricated using a brush coating process. The graphene oxide doping ratios used were 0, 5, and 15 wt%. During the thin film fabrication process, the produced sol-gel solution generates a contractile force due to the shear stress of the brush bristles, resulting in a microgroove structure. This structure was confirmed through scanning electron microscopy analysis, which revealed the clear presence of rGO. Comparing the electrical properties of a zirconium bismuth indium oxide thin film without graphene oxide doping and a thin film doped with 15 wt% graphene oxide, the electro-optical properties were significantly improved with graphene oxide doping. In general, the threshold voltage decreased by approximately 0.42 V. In addition, bandgap measurements confirmed the improved conductivity characteristics with graphene oxide doping. Since this improvement in electro-optical properties is associated with the reduction process due to graphene oxide doping, X-ray photoelectron spectroscopy analysis was performed to assess the intensity change of each element. Based on these observations, hybrid thin films doped with graphene oxide emerge as promising candidates for next generation thin film.

Threshold Voltage Modulation and Gate Leakage Suppression of Enhancement‐Mode GaN HEMT by Metal/Insulator/p‐GaN Gate Structure

Herein, a metal/insulator/p‐GaN gate HEMT (MIP‐HEMT) with Si3N4 gate dielectric layer is fabricated. Compared to the conventional p‐GaN HEMT, the MIP‐HEMT has a higher threshold voltage (Vth) of 4.8 V and better gate leakage suppression. The mechanism of threshold voltage increase in MIP‐HEMT is elucidated through an analysis of the electric field distribution in the gate region and the proposed gate capacitance model. Furthermore, MIP‐HEMTs with gate dielectric layers of varying dielectric constants and thicknesses are designed and simulated. The obtained results lead to the derivation of an empirical formula for the threshold voltage of the MIP‐HEMT under ideal dielectric/p‐GaN interface conditions, in relation to the dielectric constant and thickness of the gate dielectric layer. Additionally, simulations are conducted on the MIP‐HEMT incorporating fixed charges at the dielectric/p‐GaN interface, and the impact of interface charges is investigated. This refinement enables a more accurate prediction of the MIP‐HEMT's threshold voltage. Conclusively, MIP‐HEMTs can effectively modulate the threshold voltage by manipulating the parameters of the gate dielectric layer, thereby extending the threshold voltage range of conventional enhancement‐mode devices.

Comparative Cryogenic Investigation of FD-SOI Devices with Doped Epitaxial and Metallic Source/Drain

Abstract Defects induced by the source/drain process have a significant impact on the scattering mechanism of PMOS at cryogenic temperatures. Here, the cryogenic characteristics of FD-SOI devices with heavily doped epitaxial source/drain (Epi FD-SOI devices) and metallic Schottky barrier source/drain (SB FD-SOI devices) were investigated from 300 K down to 6 K. The doping profile along the channel was analyzed by TCAD simulation analysis. Experimental comparison of transistor performance at cryogenic temperatures was carried out for these devices with gate lengths (LG) of 100 nm and 40 nm. The I-V characteristics of the FD-SOI devices were measured with a liquid helium cooling environment. The cryogenic effect of the two types of devices on Key parameters including transconductance (Gm), field effect mobility (μFE), threshold voltage (Vth) and subthreshold slope (SS) were systematically analyzed. The doping distribution of the heavily doped epitaxial SiGe source/drain structure were subjected to more Coulomb scattering at cryogenic temperatures, whereas the doping distribution of the Schottky-barrier source/drain structure dictates that the device is mainly subjected to phonon scattering at cryogenic temperatures.

Enhanced Performance of Normally-OFF GaN HEMTs with Stair-shaped p-GaN Cap Layer

Abstract The p-GaN gated E-mode HEMTs (P-HEMTs) are being extensively studied for emerging power electronics. However, the devices still suffer from performance trade-off among threshold voltage (VTH), output drain current (IDS), and breakdown voltage (VBD). Herein, we propose P-HEMTs with a stair-like p-GaN cap layer to boost their performance. The p-GaN cap layer is composed of four discrete p-GaN staircases with the decreased thickness to the right (Right-Stair P-HEMT, RSP-HEMT) or to the left (Left-Stair P-HEMT, LSP-HEMT). It is found that the RSP-HEMT simultaneously achieves the 1.3-times increased IDS, 160 V enhanced VBD, and improved VTH stability against drain-induced barrier lowering (DIBL) effects, compared with the LSP-HEMT and the conventional BaSeline P-HEMT (BSP-HEMT). These device merits should be attributed to the effective manipulation of the lateral electric field (EF) under all bias conditions by the unique band structures enabled by the RSP configuration. Such EF manipulation strategies to improve device characteristics offer us helpful guidance and insights to further propel the development of high-performance E-mode P-HEMTs of the future.&amp;#xD;

Flexible TFT backplane development for extremely small bending radius with organic ILD and novel TFT structures

AbstractA new flexible low‐temperature polycrystalline silicon thin film transistors (LTPS TFTs) on PI substrate with organic ILD layer, island TFT, and TFT channel perpendicular to stress direction was proposed. AMOLED display panel manufactured with organic ILD did not show any visible degradation of panel image after outward rolling cycles of 200,000 at rolling radius of 4 mm or inward folding cycles of 200,000 at folding radius of 1 mm. Another novel structure of TFT with channel perpendicular to stress direction significantly reduced change of threshold voltage of −0.03 V compared with change of threshold voltage of −0.6 V for TFT with channel parallel to stress direction for reliability test of high drain current (HDC) after 100,000 outward‐bending cycles at bending radius of 3 mm. After inward‐bending cycles of 200,000 at bending radius of 1 mm, reliability test results for TFT device with organic ILD layer showed that change of on‐current is 10.07% for hot carrier instability (HCI) test, change of threshold voltage −0.31 V for negative bias thermal instability (NBTI) test, change of threshold voltage −0.24 V for hysteresis test, and breakdown voltage of gate insulator 7.73 MV/cm, respectively, and these performances are similar to those of TFT device with inorganic ILD (SiNx).

Piperidine and Pyridine Series Lead-Free Dion-Jacobson Phase Tin Perovskite Single Crystals and Their Applications for Field-Effect Transistors.

Two-dimensional (2D) organic-inorganic metal halide perovskites have gained immense attention as alternatives to three-dimensional (3D) perovskites in recent years. The hydrophobic spacers in the layered structure of 2D perovskites make them more moisture-resistant than 3D perovskites. Moreover, they exhibit unique anisotropic electrical transport properties due to a structural confinement effect. In this study, four lead-free Dion-Jacobson (DJ) Sn-based phase perovskite single crystals, 3AMPSnI4, 4AMPSnI4, 3AMPYSnI4, and 4AMPYSnI4 [AMP = (aminomethyl)-piperidinium, AMPY = (aminomethyl)pyridinium] are reported. Results reveal structural differences between them impacting the resulting optical properties. Namely, higher octahedron distortion results in a higher absorption edge. Density functional theory (DFT) is also performed to determine the trends in energy band diagrams, exciton binding energies, and formation energies due to structural differences among the four single crystals. Finally, a field-effect transistor (FET) based on 4AMPSnI4 is demonstrated with a respectable hole mobility of 0.57 cm2 V-1 s-1 requiring a low threshold voltage of only -2.5 V at a drain voltage of -40 V. To the best of our knowledge, this is the third DJ-phase perovskite FET reported to date.

Tuning the Intrinsic Stochasticity of Resistive Switching in VO2 Microresistors.

Vanadium dioxide (VO2) microresistors exhibit resistive switching above a certain threshold voltage, allowing them to emulate neurons in neuromorphic systems. However, such devices present intrinsic cycle-to-cycle variations in their resistances and threshold voltages, which can be detrimental or beneficial, depending on their use. Here, we study this stochasticity in VO2 microresistors with various grain sizes and dimensions, through high-resolution electrical and optical measurements across numerous cycles. Our results highlight that the cycle-to-cycle variations in threshold voltage increase as the grain size becomes comparable to the device dimensions. We also present observations of multimodal threshold voltage distributions in the smaller-length resistors. To understand the underlying phenomenon, we investigate the relationship between the device insulating resistance and threshold voltage distributions, showing that these modes could correspond to distinct percolation paths and filaments. Our findings provide the first experimentally verified guidelines for designing VO2 devices with minimized/maximized stochasticity, depending on the targeted application.

Piezoresistive sensitivity enhancement below threshold voltage in sub-5 nm node using junctionless multi-nanosheet FETs.

In this paper, the piezoresistive sensitivity is enhanced by applying uniform mechanical stress (MS) on the multi-nanosheet (NS) channels of sub-5 nm junctionless field-effect transistors (FETs). The piezoresistivity of the sensing device is boosted by narrowing channel conductivity using low gate biasing and reducing physical channel width, resulting in the maximum (~6 times higher) sensitivity observed in the subthreshold regime compared to the ON-state condition. In addition, the sensitivity is extensively increased by ~30.3% near the threshold voltage (VTH) with horizontally multi-NS stacking due to the uniform MS distribution on the multi-NS channels, which can sense slight deflection of pressure on the circular diaphragm. These results show that the tunable sensitivity of junctionless multi-channel devices is superior to the inversion mode, a consequence of the less scattering effect, better thermal stability, and low electronic noise.