Threshold Voltage Values Research Articles

Research on Double Parameters Discharge Gap Detection of Gap Voltage and Charging Current in Micro-EDM

In micro-EDM, for discharge energy and gap is very small, discharge state is much complex and changes very fast, traditional detection of average voltage can’t judge discharge state in real time, so double parameters detection mode of gap voltage and charging current is designed. Based on characters of RC pulse discharge, three threshold voltage and current values of high, medium, low are devided according to charge constant. Gap voltage and charging current have fixed corresponding relationship, through this relationship, these two parameters can be combined as five different situations to determine three states of discharge machining, representing open-circuit, normal discharge and short-circuit. The combination of gap voltage and charging current can accurately judge gap state and further improve working efficiency in micro-EDM.

Circuit Modeling of Vertical Buried-Grid SiC JFETs

The main problem when the conventional PSpice JFET model is used to simulate a vertical short-channel buried-grid JFET is caused by the constant values of Threshold Voltage (VTO) and Transconductance (BETA). This paper presents a new model for the vertical short-channel buried-grid 1200V JFET, where both VTO and BETA vary with respect to the Drain-Source voltage. Simulation data from Medici have been analyzed in order to extract the analytical equations for VTO and BETA. Also other PSpice parameters are extracted from these data. The proposed circuit model has been simulated in Matlab by optimizing the same algorithm that PSpice uses. A variety of results are shown and discussed in this paper.

Electron-plasmon interactions in resonant molecular tunnel junctions

In this paper, we show that electron-plasmon interactions play a critical role in resonant charge transfer in molecular tunnel junctions (MTJs). Only when such interactions are taken into account, does it become possible to obtain the correct values of the turn-on threshold voltage in the current-voltage characteristics observed in experiment. In addition, we predict the emission of photons from MTJs with a large quantum yield $\ensuremath{\sim}{10}^{\ensuremath{-}2}$ as a result of the excitation of surface plasmons upon the application of a voltage across the junction. Finally, we discuss physical conditions, which are necessary for the experimental observation of this phenomenon.

Integration Challenges in Standard CMOS with Multiple Gate Oxide Thicknesses

Following the prototype release of an automotive, dual gate oxide, and high voltage process, yield problems were observed on an intermittent basis. An investigation was made into a temperature sense circuit and a differential input of a unity gain operational amplifier used for I/O circuitry. The problem was isolated to a bimodal distribution of threshold voltage values for standard gate oxide thickness transistor test structures. When all such structures on the wafer were electrically probed, their distribution of failures was found to be mostly random. Curiously, this mismatch was consistent with a small increase in gate oxide thickness but not observed in the single gate technology. Microscope inspection following etchback of oxide from standard gate regions provided evidence of water spotting and damage to active areas. Process changes were implemented to minimize this damage. Subsequent lots yielded well and matching problems were eliminated.

A current limiter for DC/DC regulators with compensation against process and temperature variations

A low-voltage current limiter suitable for both linear and switching regulators is presented. Although the approach relies on absolute values of sense resistance and MOSFET threshold voltage on subsequent I/V and V/I conversions of the sensed current, a reference current in the process and temperature (PT) compensator is derived in such a manner that the dependence of clamping threshold I TH on PT-spread is first-order canceled out. Furthermore, the current sensor embodies a transconductor build up with either p-MOSFET depletion-mode device or a level-shifter with enhancement-mode transistors, meeting low-dropout requirements. For nominal value of 750 mA, Monte Carlo data express boundaries for I TH of 523 and 1,075 mA, accounting for broad PT-variation, as well as operating voltages and mismatching. A linear regulator with 400 mA-current rate and 250 mV-dropout incorporating the limiter on its depletion p-MOSFET version was integrated on a smart-power process. The limiter occupies an area of 0.052 mm2 and consumes only 65 μA. Experimental data attest the clamper functionality and accuracy against PT-variations. From samples of distinct lots, I TH spans from 615 to 996 mA. Owing to its simplicity and open-loop operation in case of switchers, the limiter reacts upon overcurrent in only 20 ns, making it compatible with converters functioning in MHz range and under low duty-cycles. Moreover, the limiter suits supply voltages as low as 1 V.

Electronic model for VCSELs: Switching mode, control of threshold current and saturation

An electronic model of VCSELs based on the mathematical rate equations of Danckaert et al. [J. Danckaert, B. Nagler, J. Albert, K.K. Panajotov, I. Veretennicoff, T. Erneux, Opt. Commun. 201 (2002) 129] is built. The polarization switching (PS) phenomenon is generated. The PS phenomenon here is analyzed using two methods. In the first method, the behavior of the polarization modes is investigated in terms of the injection voltage parameter. A threshold voltage value and a switching value are obtained as prescribed by the theoretical model. In the second method, the ratio of the voltages (modes) outputs is plotted in terms of the voltage parameter. It is found that the ratio reaches a maximum at a critical value of the voltage parameter. Controlling the threshold current, it is found that it can be reduced voluntarily by the use of an external voltage supplier (denoted E 2). When E 2 increases, the threshold current decreases and the maximum reached by the polarization mode increases. When the control voltage is high and below a second critical value, the polarization modes saturate to the same value. But above this critical value, they saturate to opposite values.

Nanopower Subthreshold MCML in Submicrometer CMOS Technology

This paper presents subthreshold MOS current-mode logic (MCML) circuits implemented in a commercial 0.25-mum CMOS technology. We propose the adoption of bulk-drain-connected pMOS transistors as loads for subthreshold MCML gates. The b-d connection extends the linear operating range of the load, thus increasing the output logic swing of the subthreshold MCML gate. Theoretical and measured results are presented for an MCML inverter and a ten-stage ring oscillator operating at supply voltages below the threshold-voltage value, with power consumption on the order of nanowatts. At a 300-mV supply, the oscillator works at a frequency of 638 Hz with a total power consumption of 345 pW.

A numerical analysis of the electrical characteristics of small-grains poly-Si TFTs

Voltage characteristics of polysilicon thin films transistors (Poly-Si TFTs) are related to basic material and device parameters. Understanding and modeling the electrical behavior of poly-Si TFT require knowledge of equivalent properties of polysilicon which are strongly affected by defects present in this material. A numerical analysis, which studies the electrical characteristics of small-grains poly-Si TFTs, has been investigated. The density of states (DOS) in the band gap is modeled by assuming an exponential distribution of deep and tail states. The proposed model evaluates the influence of both deep and tail states on the electrical conduction process and the dominant contribution of tail states on the threshold voltage values while the deep states in the middle of polysilicon gap controls the lower threshold regime. The surface potential and ON/OFF current ratio are also calculated. The comparison of the generated current-voltage characteristics obtained from numerical simulation TCAD-ATLAS with those reported in the literature show a good agreement.

Suppression of corner effects in wide-channel triple-gate bulk FinFETs

This paper presents a method of eliminating corner effects in triple-gate bulk FinFETs. The parasitic device in FinFET’s corners can be turned off by increasing body doping in corner regions by corner implantation. Corner implantation described in this work does not require additional masks, rotation or tilt. This method is investigated in idealized (with rectangular cross-section of the fin) and realistic (with rounded top corners of the fin) triple-gate bulk FinFETs and has shown considerable improvements: kink effect in transfer characteristics is completely eliminated, threshold voltage increased by up to 0.43 V, subthreshold swing and drain-induced barrier-lowering decreased to values under 95 mV/dec and 16 mV/V, respectively. Optimization is performed on the realistic rounded-corner FinFET structure to find the proper body doping and corner implantation peak values for acceptable threshold voltage and on-state current.

MOS mismatch effects on TIQ comparators

The main purpose of this study is to investigate the so-called threshold inverter quantisation (TIQ) technique from a MOS transistor mismatch point of view. The logic threshold voltage values on the voltage transfer characteristics of three different area-sized CMOS cascaded inverters located on four different locations around a TIQ-based 5b Flash ADC are measured over 40 fabricated samples in a 0.5 μm CMOS process to investigate the intra-die and inter-die mismatch effects. Based on the test results, the worst case inter-die and intra-die standard deviations occur (as 70 mV and 80 mV, respectively) when (W n/W p) has the minimum design value of (W n/W p = 3.6 μm/23.6 μm). If the mean value of percent–standard deviations are chosen as the comparison parameter, then the comparator having minimum size of transistors exhibits the worst case matching property for having 2.91% of mean percent–standard deviation value for the intra-die case. This work concludes that the suggested resolution values for TIQ-based Flash ADC designs are to be less than 6-bit for 0.5 μm CMOS process. However, it might be lesser for a smaller feature-size CMOS TIQ-based flash ADC design due to the expected increase in short channel and narrow width effects. On the other hand, if a higher resolution is preferred, then the channel length value should not be reduced to the minimum value that the related technology allows during the design process. In this situation, however, the sampling rate will be degraded.

Work-Function Engineering for 32-nm-Node pMOS Devices: High-Performance TaCNO-Gated Films

We have demonstrated p-type field effect transistors (p-FETs) devices using a TaCNO metal gate for the first time. These p-FETs have threshold voltage values of - 0.4 and - 0.25 V for HfSiON and HfSiO gate dielectrics, respectively, with equivalent oxide thickness of 1.6-1.7 nm. The TaCNO metal shows a high effective work function (eWF) of 4.89 eV on thick SiO2 interface layer, although the eWF rolls off with reducing EOT. Excellent transistor characteristics are achieved, with Ion of 375 muA/mum at Ioff = 60 nA, for Vdd = 1.1V .

Controlled synthesis of millimeter-long silicon nanowires with uniform electronic properties.

We report the nanocluster-catalyzed growth of ultralong and highly uniform single-crystalline silicon nanowires (SiNWs) with millimeter-scale lengths and aspect ratios up to approximately 100,000. The average SiNW growth rate using disilane (Si 2H 6) at 400 degrees C was 31 microm/min, while the growth rate determined for silane (SiH 4) reactant under similar growth conditions was 130 times lower. Transmission electron microscopy studies of millimeter-long SiNWs with diameters of 20-80 nm show that the nanowires grow preferentially along the 110 direction independent of diameter. In addition, ultralong SiNWs were used as building blocks to fabricate one-dimensional arrays of field-effect transistors (FETs) consisting of approximately 100 independent devices per nanowire. Significantly, electrical transport measurements demonstrated that the millimeter-long SiNWs had uniform electrical properties along the entire length of wires, and each device can behave as a reliable FET with an on-state current, threshold voltage, and transconductance values (average +/-1 standard deviation) of 1.8 +/- 0.3 microA, 6.0 +/- 1.1 V, 210 +/- 60 nS, respectively. Electronically uniform millimeter-long SiNWs were also functionalized with monoclonal antibody receptors and used to demonstrate multiplexed detection of cancer marker proteins with a single nanowire. The synthesis of structurally and electronically uniform ultralong SiNWs may open up new opportunities for integrated nanoelectronics and could serve as unique building blocks linking integrated structures from the nanometer through millimeter length scales.

Leakage Minimization of SRAM Cells in a Dual-$V_t$ and Dual-$T_{\rm ox}$ Technology

Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicrometer regime. As a result, reducing the subthreshold and tunneling gate leakage currents has become one of the most important criteria in the design of VLSI circuits. This paper presents a method based on dual- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> and dual- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ox</sub> assignment to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and the decoder. Thus, the idea is to deploy different configurations of six-transistor SRAM cells corresponding to different threshold voltage and oxide thickness assignments for the transistors. Unlike other techniques for low-leakage SRAM design, the proposed technique incurs neither area nor delay overhead. In addition, it results in a minor change in the SRAM design flow. The leakage saving achieved by using this technique is a function of the values of the high threshold voltage and the oxide thickness, as well as the number of rows and columns in the cell array. Simulation results with a 65-nm process demonstrate that this technique can reduce the total leakage power dissipation of a 64 times 512 SRAM array by 33% and that of a 32 times 512 SRAM array by 40%.

Electrical-thermal switching effect in high-density polyethylene/graphite nanosheets conducting composites

The nonlinear response in high-density polyethylene/graphite nanosheets conducting composites under increasing applied voltage is investigated. Under sufficient applied constant voltage, the resistance increases initially due to Joule heating effect and then eventually reaches a steady value with a characteristic thermal relaxation time τh, which decreases as the applied field increases. The switch value, namely the ratio of the resistance under steady condition to the resistance of sample in linear regime, gradually increases with the increasing applied field. The threshold voltage (V0) at which the resistance start to increase with time scales with linear regime resistance (R0) of the sample as \( V_{0} \sim R^{x}_{0} ,\) with the exponent x = 0.78 ± 0.05. All the curves of R/R0 vs. V/V0 collapse to a similar curve with the function R/R0 = 1 + α(V/V0)θ. The results reveal that the threshold voltage value decreases with increasing graphite nanosheets content in the composites.

5.4: Improvement of Fast Response LC Materials by Bent‐Core Dopants in Optical Compensated Bend (OCB) Mode Liquid Crystal Displays

AbstractThe stabilization of bend configuration in optical compensated bend (OCB) mode cells by doping bent‐core molecules was developed in this study. The values of response time (τ) and threshold voltage (Vth) in OCB cells were dependent on not only the concentration but also the shape, dipole direction, and flexible chain length of the doping molecules. Experimental results showed that the total response time (τtotal) and threshold voltage (Vth) of OCB cells could be reduced by doping bent‐core molecules, and smaller τ values by reducing flexible chain lengths as well as smaller Vth values by reducing polarization of bent‐core molecules were normally obtained. In general, higher concentrations of dopants normally induced shorter field‐on response time (τon) and a minimum field‐off response time (τoff) occurred at 0.5% of doping concentration, where the fastest total response time (τtotal) values were achieved.

Lower current operation of phase change memory cell with a thin TiO2 layer

The phase change memory cell with 8nm TiO2 layer inserted between phase change material Ge2Sb2Te5 and bottom heating electrode tungsten was fabricated. It showed an advanced electrical threshold switching characteristics in the dc current-voltage measurement with the much lower value of threshold voltage of 1.5V. The reset current of the device cell decreased 68% compared with that without TiO2 layer. These results will contribute to the lower power consumption of the phase change memory. Besides that, the device cell showed good endurance characteristics, demonstrating the capability of random access memory application.

Electrical characterizations of a pentacene-based thin film transistor under optical excitation

Light effect on electrical properties of a pentacene-based transistor was studied. We showed that under optical excitation, the phenomenon of photoconductivity can modify both carrier density and mobility; these changes depend on the wavelength, on the carrier photogeneration rate and on the material absorption coefficient. At first, we examined structural, optical and electrical properties of pentacene films; a thickness of 50 nm is the good compromise to obtain optimal performances. Then we observed the effect of illumination on the drain current in the accumulation regime: at 365 nm, we obtained a maximum ratio of photocurrent to dark current ( I dsillumination / I dsdark ) of about 2 × 10 3 when the gate is turned off, mobility and threshold voltage values around 0.02 cm 2 V −1 s −1 and 7.5 V respectively. Moreover the dynamics study (off-state) showed sufficiently fast response times with large current gains to envisage applications in the area of light activated memory components. Finally, we examined the performances of a new component based on the coupling of an organic light emitting diode (with an emission peak at 550 nm) as an input unit with an organic transistor as an output unit. This last study enabled to underscore an increase in mobility without modifying the carrier density for low carrier photogeneration rates.

Compact cantilever force probe for plasma pressure measurements

A simple, compact cantilever force probe (CFP) has been developed for plasma pressure measurements. It is based on the pull-in phenomenon well known in microelectromechanical-system electrostatic actuators. The probe consists of a thin (25 mum) titanium foil cantilever (38 mm of length and 14 mm of width) and a fixed electrode separated by a 0.75 mm gap. The probe is shielded by brass box and enclosed into boron nitride housing with a 9 mm diameter window for exposing part of cantilever surface to the plasma. When the voltage is applied between the cantilever and the electrode, an attractive electrostatic force is counterbalanced by cantilever restoring spring force. At some threshold (pull-in) voltage the system becomes unstable and the cantilever abruptly pulls toward the fixed electrode until breakdown occurs between them. The threshold voltage is sensitive to an additional externally applied force, while a simple detection of breakdown occurrence can be used to measure that threshold voltage value. The sensitivity to externally applied forces obtained during calibration is 0.28 V/microN (17.8 VPa for pressure). However, the resolution of the measurements is +/-0.014 mN (+/-0.22 Pa) due to the statistical scattering in measured pull-in voltages. The diagnostic temporal resolution is approximately 10 ms, being determined by the dynamics of pull-in process. The probe has been tested in the tokamak ISTTOK edge plasma, and a plasma force of approximately 0.07 mN (plasma pressure approximately 1.1 Pa) has been obtained near the leading edge of the limiter. This value is in a reasonable agreement with the estimations using local plasma parameters measured by electrical probes. The use of the described CFP is limited by a heat flux of Q approximately 10(6) W/m(2) due to uncontrollable rise of the cantilever temperature (DeltaT approximately 20 degrees C) during CFP response time.

Pentacene-based low voltage organic field-effect transistors with anodized Ta2O5 gate dielectric

Pentacene-based low voltage organic field-effect transistors were realized using an anodized Ta2O5 gate dielectric. The Ta2O5 gate dielectric layer with a surface roughness of 1.3Å was obtained by anodizing an e-beam evaporated Ta film. The device exhibited values of saturation mobility, threshold voltage, and Ion∕Ioff ratio of 0.45cm2∕Vs, 0.56V, and 7.5×101, respectively. The gate leakage current was reduced by more than 70% with a hexamethyldisilazane (HMDS) treatment on the Ta2O5 layer. The HMDS treatment also resulted in enhanced mobility values and a larger pentacene grain size.

Charge-pumping characterization of SOI devices fabricated by means of wafer bonding over pre-patterned cavities

The quality of the silicon-buried oxide bonded interface of SOI devices created by thin Si film transfer and bonding over pre-patterned cavities, aiming at fabrication of DG and SON MOSFETs, is studied by means of chargepumping (CP) measurements. It is demonstrated that thanks to the chemical activation step, the quality of the bonded interface is remarkably good. Good agreement between values of front-interface threshold voltage determined from CP and I-V measurements is obtained.