Threshold Voltage Instability Research Articles

Engineered interface charges and traps in GaN metal-oxide-semiconductor field-effect transistors providing high channel mobility and E-mode operation

Abstract This review focuses on controlling interface charges and traps to obtain minimal channel resistance and stable enhancement-mode operation in GaN metal-oxide-semiconductor field-effect transistors. Interface traps reduce the free electron density and act as Coulomb scattering centers, thus reducing the channel mobility. Oxide traps cause instability of threshold voltage (V th) by trapping electrons or holes under gate bias. In addition, the V th is affected by the overall distribution of interface charges. The first key is a design of a bilayer structure to simultaneously obtain good insulating properties and interface properties. The other key is the optimization of post-deposition annealing to minimize oxide traps and interface fixed charges. Consequently, the gate structure of an AlSiO/AlN/p-type GaN has been designed. Reductions in V th as a result of polarization charges can be eliminated by using an m-plane trench channel, resulting in a channel mobility of 150 cm2V–1s–1 and V th of 1.3 V.

Threshold voltage instability of SiC MOSFETs under very‐high temperature and wide gate bias

AbstractThreshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs. In this article, the influence of gate bias (VGS) and high temperature on VTH instability is investigated under wide VGS and very‐high temperature range (150°C to 275°C). The degradation mechanism of gate oxide under coupling of different electrical and thermal stress is revealed. When the device is subjected to +VGS, the relationship between VTH shift and temperature is not monotonic and there is a temperature turning point. This is mainly related to the capture/release and generation of electron traps. However, the VTH shift increases sharply and gate oxide breakdown for the device bias at +35 V, which is related to Fowler–Nordheim (F–N) tunnelling effect. For a large −VGS, the VTH shift is very small. Moreover, when the negative VGS decreases, the VTH shift is positively correlated with temperature, which may result from the activation and charge exchange of hole traps. However, the influence of moving ions changes the temperature dependence of VTH shift for the device bias at −30 V. Finally, the devices of different manufacturers are studied and similar change patterns are found. This finding provides guidance for the further application of SiC MOSFETs under high temperatures and different voltages.

Physical understanding of a normally off p-GaN/AlGaN/GaN HEMT gate stack and a review of VTH measurement techniques

Abstract In this report a comprehensive review of the variations in threshold voltage (VTH) resulting from diverse VTH measurement bias conditions employed by leading manufacturers, as well as VTH extraction techniques is made. Notably, a standard deviation of 15% is observed in threshold voltage values due to variations in measurement bias conditions. This variation is attributed to the change in the lateral electic field conditions across gate and drain which occurs due to the change in bias conditions. Additionally, a simplified physical interpretation of the gate stack in p-GaN gate normally-off AlGaN/GaN on Si HEMTs is made. The formation of the two-dimensional electron gas (2DEG), the charge balance within the pGaN/AlGaN/GaN gate stack, and an analytical expression for threshold voltage are examined. Furthermore, various trapping mechanisms within the gate stack are reviewed to comprehend the dynamic conditions potentially contributing to threshold voltage instability during nominal operation.

Dynamic On-State Resistance and Threshold-Voltage Instability in SiC MOSFETs

Dynamic on-state resistance has been experimentally observed in all commercially-available SiC MOSFETs studied on the time scale of normal device operation, and can be explained by the presence of dynamic threshold-voltage instability. The magnitude of this dynamic on-state resistance varies from vendor to vendor, but in every case this magnitude generally corresponds to the magnitude of that device’s threshold-voltage instability, as described by standard textbook equations-especially in the case of large threshold-voltage instabilities.

Investigation of Threshold Voltage Instability and Bipolar Degradation in 3.3 kV Conventional Body Diode and Embedded SBD SiC MOSFET

The 3.3 kV SiC MOSFETs are essential for traction applications, so it is important to investigate the reliability of the recently developed high voltage MOSFETs and power modules as they are believed to be more susceptible to the effects of basal plane dislocations (BPDs). This paper presents measurement results and analysis of bipolar degradation and threshold voltage instability in 3.3 kV SiC MOSFETs having two distinct kinds of integrated diode, conventional body diode and embedded Schottky Barrier Diode (SBD). No bipolar degradation was observed both in MOSFET with conventional body diode and with embedded SBD after accumulated test with 100 hours each of 200%, 400% and 600% rated current stress in the 3rd quadrant of operation. However, the output characteristics show 1% (~0.2 mΩ) and 2% (~0.4 mΩ) increase in on resistance (RDS(on)) and 11% (0.23 V) and 5% (0.1 V) increase in threshold voltage (VTH), respectively, after total bipolar degradation test in the case of the MOSFET with conventional body diode and up to 74 hrs of 600% rated current stress in the case of the MOSFET with embedded SBD at 70°C. A rapid large negative VTH shift was observed in the MOSFETs with embedded SBD after ~ 74 hrs of 600% rated current stress. After accumulated Bias Temperature Instability (BTI) test at 150°C, the VTH value at 25°C has increased by 9.7% (0.14 V) and 14.5% (0.2 V) for the MOSFET with conventional body diode and with embedded SBD, respectively, while RDS(on) increased by 1mΩ at 25°C and by 5mΩ at 150°C, for both types of MOSFETs.

Study of the Bias Driven Threshold Voltage Drift of 1.2 kV SiC MOSFETs in Power Cycling and High Temperature Gate Bias Tests

Threshold voltage instability remains a challenging aspect for metal-oxide semiconductor-field-effect-transistors (MOSFETs) made from silicon carbide (SiC). SiC MOSFETs from two manufacturers, with planar and trench gate structure respectively, have been tested under different test procedures, including power cycling and high temperature gate bias tests. The standard power cycling test setup has been modified to enable an in situ threshold voltage read-out procedure with the hysteresis method. The recorded threshold voltage drift has been compared with results from high temperature gate bias tests applying a simple power law fit, with the intention to predict the drift in power cycling tests. For the group with trench MOSFETs comparable results between power cycling and gate stress tests have been achieved.

Quantum coupling and self-heating impacts on threshold voltages of GaN metal–insulator-semiconductor high-electron-mobility transistors

A transient heat conduction equation has been proposed to describe the cooling process of a hot two-dimensional electron gas layer in a GaN-based transistor. This equation serves as the basis for a physical analytical model that explains the impacts of hot electrons in the hot two-dimensional electron gas layer via quantum coupling on the threshold voltage of GaN-based transistors. The temperature of the two-dimensional electron gas layer decreases to ambient temperature as time increases, and the threshold voltage shifts caused by such a temperature will recover with time. The proposed model accurately reflects the observed recovery of threshold voltage over time in experiments. At the same time, it offers insight into how the gate voltage, the source-drain voltage, and the ambient temperature can shift the threshold voltage in these transistors. The simplicity and analytic nature of this proposed model not only provide a physical origin of the threshold voltage instability in GaN-based devices but also offer the possibility for improving device reliability by selecting appropriate device physical parameters.

Physical Modeling of Threshold Voltage Instability in GaN High‐Electron‐Mobility Transistors

The transient heat conduction equation for the 2D electron gas layer in GaN high‐electron‐mobility transistors is developed. The Schottky barrier height and the conduction band offset seen by electrons in the 2D electron gas layer will be reduced due to self‐heating in the 2D electron gas of GaN high‐electron‐mobility transistors via quantum coupling. Such a reduction will lead to a shift in the threshold voltage. To address this issue, an analytical physical model of self‐heating in the 2D electron gas of a GaN high‐electron‐mobility transistor via quantum coupling impacts on its threshold voltage instability is proposed. The proposed model forecasts that the threshold voltage can have an exponentially dependent relation with the reciprocal of the recovery time after the stress voltage is released, as well as dependencies on the square of the drift velocity, the gate voltage, and the surrounding temperature. The experimentally observed threshold voltage shifts of GaN high‐electron‐mobility transistors confirm such dependent relationships predicted by the proposed physical model. This article provides evidence that the combination of self‐heating in the 2D electron gas layer and quantum coupling may be a possible physical origin of the threshold voltage instability in GaN high‐electron‐mobility transistors.

Threshold voltage instability in III-nitride heterostructure metal–insulator–semiconductor high-electron-mobility transistors: Characterization and interface engineering

Threshold voltage instability in III-nitride heterostructure metal–insulator–semiconductor high-electron-mobility transistors: Characterization and interface engineering

Threshold Voltage Instability After Double Pulse Test Under Different OFF-State Drain Voltages and ON-State Drain Currents in p-GaN Gate AlGaN/GaN HEMT

This study investigated threshold voltage (VTH) instability in a Schottky p-GaN gate AlGaN/GaN high-electron-mobility transistor (HEMT) by using the double pulse test (DPT) with a 1 μs pulse width in the ON-state and OFF-state. OFF-state drain biases (VDS,OFF) of 100–400 V and ON-state drain currents of ID,ON 1–16 A were applied in the DPT to observe the post-DPT VTH shift. The ON-state currents did not strongly influence the device’s characteristics after the DPT. However, the OFF-state voltages, particularly VDS,OFF = 100 and 200 V, exerted notable effects. A TCAD simulation was conducted to investigate the mechanism underlying the VTH shift after the DPT at various VDS,OFF and ID,ON levels.

SiC Fin-Channel MOSFET for Enhanced Gate Shielding Effect

A SiC fin-channel MOSFET structure (Fin-MOS) is proposed for an enhanced gate shielding effect. The gates are placed on each side of the narrow fin-channel region, while grounded p-shield regions below the gates provide a strong shielding effect. The device is investigated using Sentaurus TCAD. For a narrow fin-channel region, there is difficulty in forming an Ohmic contact to the p-base; a floating p-base might potentially store negative charges upon high drain voltage, and, thus, causes threshold voltage instabilities. The simulation reveals that, for a fin-width of 0.2 μm, the p-shield regions provide a stringent shielding effect against high drain voltage, and the dynamic threshold voltage shift (∆Vth) is negligible. Compared to conventional trench MOSFET (Trench-MOS) and asymmetric trench MOSFET (Asym-MOS), the proposed Fin-MOS boasts the lowest OFF-state oxide field and reverse transfer capacitance (Crss), while maintaining a similar low ON-resistance.

Physical insight into the abnormal VTH instability of Schottky p-GaN HEMTs under high-frequency operation

In this Letter, we investigate the threshold voltage (VTH) instability of Schottky p-GaN gate high electron mobility transistors (SP-HEMTs) under high-frequency operation by a resistive-load hard switching method. The abnormal VTH instability is observed, which is different between fully and partially depleted SP-HEMTs (FD- and PD-HEMTs). Notably, for FD-HEMT, VTH shifts positively with effective stress time. However, the VTH instability in PD-HEMT is more complex. At low VGS (e.g., 3 V) and high VGS (e.g., 6 V), VTH shifts positively with stress time consistently. Nevertheless, at intermediate VGS levels (e.g., 4 and 5 V), VTH initially shifts positively and then negatively, displaying a non-monotonous variation. Furthermore, the frequency dependence of VTH is contingent upon VGS. At low VGS, VTH exhibits a negative shift with the increase in frequency. This trend inverses when VGS exceeds 4 V. And it should be noted that the extracted VTH under high-frequency operation is lower than their quasi-static values for both transistor types. This work depicts the physical process and mechanism of the abnormal VTH instability; different from the quasi-static case, hole accumulation effects will be enhanced due to the high dV/dt, which results in a lower VTH. The distinct VTH behaviors of FD- and PD-HEMTs are closely related to the trapping effects, as well as hole accumulation and insufficiency, within the two different p-GaN gate layers.

4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses.

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.

Investigation of Threshold Voltage Instability of SiC MOSFETs Under Different Gate Voltage Sequences

Investigation of Threshold Voltage Instability of SiC MOSFETs Under Different Gate Voltage Sequences

Rapid detection of capture and emission processes in surface and buffer traps: Understanding dynamic degradation in GaN power devices

This study utilized a rapid detection technique, Isothermal Capture Transient Spectroscopy (ICTS), to identify and evaluate defects related to GaN device surface and buffer traps, and investigated the mechanisms by which they affect the dynamic performance of GaN based devices. Interface states and dielectric bulk traps were analyzed, unveiling distinctive device behavior under positive gate pulse-biased ICTS. The observed S-shaped threshold voltage (VTH) instability and dynamic gate-drain capacitance (CGD) issues were directly associated with these interface states and bulk traps. Negative gate pulse-biased ICTS revealed the presence of logarithmic electron trapping originating from extended electron traps, and spatial wide distributed hole traps within the GaN buffer layer, significantly impacting the dynamic on-resistance (RON) during off-state stress of the devices. The rapid assessment capabilities of this method provide a valuable tool for optimizing GaN epitaxy and manufacturing processes.

Mg activation anneal of the p-GaN body in trench gate MOSFETs and its effect on channel mobility and threshold voltage stability

This work addresses the impact of the Mg activation anneal step and the resulting acceptor concentration on the channel mobility and VT stability of vertical MOSFETs. Increasing the annealing time with N2 only ambient and the annealing temperature with O2 in the ambient is shown to be effective in increasing the channel acceptor concentration. When the effective acceptor concentration is increased, the mobility is degraded due to a transition in the main scattering mechanism from Coulomb to surface roughness scattering. Degradation of the on-state current and maximum transconductance at high operating temperatures was linked to bulk mobility degradation of the drift layer due to lattice scattering. The two Mg activation annealing conditions considered here show different trends with regard to the threshold voltage stability, while N2 only ambient did not impact this parameter, including O2 increased threshold voltage instability. It is shown that increasing the Mg chemical concentration in the p-GaN layer degrades channel mobility and threshold voltage stability, irrespectively of the effective acceptor concentration, providing evidence for degradation of the channel/dielectric interface characteristics with higher Mg chemical concentration. This study shows that it is possible to achieve very low threshold voltage hysteresis and high channel mobility by reducing the Mg chemical concentration while maintaining high effective acceptor concentration. These results provide key insights for the development of vertical GaN FETs.

Dynamic Analytical Switching Loss Model of SiC MOSFET Considering Threshold Voltage Instability

Dynamic Analytical Switching Loss Model of SiC MOSFET Considering Threshold Voltage Instability

Mechanism of Threshold Voltage Instability in Double Gate α-IGZO Nanosheet TFT Under Bias and Temperature Stress

Mechanism of Threshold Voltage Instability in Double Gate α-IGZO Nanosheet TFT Under Bias and Temperature Stress

Effect of Noncircular Channel on Distribution of Threshold Voltage in 3D NAND Flash Memory.

The instability in threshold voltage (VTH) and charge distributions in noncircular cells of three-dimensional (3D) NAND flash memory are investigated. Using TCAD simulation, we aim to identify the main factors influencing the VTH of noncircular cells. The key focus is on the nonuniform trapped electron density in the charge trapping layer (CTL) caused by the change in electric field between the circular region and the spike region. There are less-trapped electron (LT) regions within the CTL of programmed noncircular cells, which significantly enhances current flow. Remarkably, more than 50% of the total current flows through these LT regions when the spike size reaches 15 nm. We also performed a comprehensive analysis of the relationship between charge distribution and VTH in two-spike cells with different heights (HSpike) and angles between spikes (θ). The results of this study demonstrate the potential to improve the reliability of next-generation 3D NAND flash memory.

Electrothermal power cycling of GaN and SiC cascode devices

This study investigates the power cycling tests of the GaN and SiC cascode devices to enable analysis of the alteration of their properties, such as case temperature, transfer characteristics, threshold voltage and leakage current once cycles complete. The highest increase in case temperature is seen in GaN cascode devices and more pronounced changes are seen in the drain current of these devices than that of the SiC devices as well. This is also the case in threshold voltage instability which is seen in the transfer characteristics of GaN devices whereas there is no change in their leakage currents. With respect to SiC cascode devices, the case temperature rise in the devices is around 25 °C and there is little increase in the leakage current after increasing the cycles, although there is a decreasing trend in their threshold voltages that can be linked to the temperature rise of the device while their transfer characteristics are invariant with increasing power cycles.