Threshold Logic Research Articles

Complete all-optical processing polarization-based binary logic gates and optical processors

We present a complete all-optical-processing polarization-based binary-logic system, by which any logic gate or processor can be implemented. Following the new polarization-based logic presented in [Opt. Express 14, 7253 (2006)], we develop a new parallel processing technique that allows for the creation of all-optical-processing gates that produce a unique output either logic 1 or 0 only once in a truth table, and those that do not. This representation allows for the implementation of simple unforced OR, AND, XOR, XNOR, inverter, and more importantly NAND and NOR gates that can be used independently to represent any Boolean expression or function. In addition, the concept of a generalized gate is presented which opens the door for reconfigurable optical processors and programmable optical logic gates. Furthermore, the new design is completely compatible with the old one presented in [Opt. Express 14, 7253 (2006)], and with current semiconductor based devices. The gates can be cascaded, where the information is always on the laser beam. The polarization of the beam, and not its intensity, carries the information. The new methodology allows for the creation of multiple-input-multiple-output processors that implement, by itself, any Boolean function, such as specialized or non-specialized microprocessors. Three all-optical architectures are presented: orthoparallel optical logic architecture for all known and unknown binary gates, singlebranch architecture for only XOR and XNOR gates, and the railroad (RR) architecture for polarization optical processors (POP). All the control inputs are applied simultaneously leading to a single time lag which leads to a very-fast and glitch-immune POP. A simple and easy-to-follow step-by-step algorithm is provided for the POP, and design reduction methodologies are briefly discussed. The algorithm lends itself systematically to software programming and computer-assisted design. As examples, designs of all binary gates, multiple-input gates, and sequential and non-sequential Boolean expressions are presented and discussed. The operation of each design is simply understood by a bullet train traveling at the speed of light on a railroad system preconditioned by the crossover states predetermined by the control inputs. The presented designs allow for optical processing of the information eliminating the need to convert it, back and forth, to an electronic signal for processing purposes. All gates with a truth table, including for example Fredkin, Toffoli, testable reversible logic, and threshold logic gates, can be designed and implemented using the railroad architecture. That includes any future gates not known today. Those designs and the quantum gates are not discussed in this paper.

Room-temperature negative differential resistance in polymer tunnel diodes using a thin oxide layer and demonstration of threshold logic

Conjugated polymers, with π molecular orbitals delocalized along the polymer chain, are useful organic semiconductors that provide the possibility of molecular electronics for low-power organic-based memory and logic. Quantum functional devices based upon carrier tunneling processes open vistas into very efficient and low-power consumption circuitry that would be ideal for these applications. We demonstrate here strong room temperature negative differential resistance (NDR) for poly[2-methoxy-5-(2′-ethyl-hexyloxy)-1,4-phenylenevinylene] (MEH-PPV) polymer tunnel diodes (PTD) using a thin TiO2 tunneling layer (∼2–8nm) sandwiched between the MEH-PPV and the indium tin oxide anode. A key advantage is the pronounced NDR using a thick polymer layer with a large active area, circumnavigating the need for molecularly-sized junctions. Current-voltage measurements show large and reproducible NDR with a PVCR as high as 53 at room temperature. We also demonstrate basic logic circuit operation using a pair of these PTDs connected in series to form a monostable-bistable transition logic element (MOBILE) latch.

On Single-Electron Technology Full Adders

This paper reviews several full adder (FA) designs in single-electron technology (SET). In addition to the structure and size (i.e., number of devices), this paper tries to provide a quantitative and qualitative comparison in terms of delay, sensitivity to (process) variations, and complexity of the design. This will allow for a better understanding of the advantages and disadvantages of each solution. An optimization of an SET FA (combining one of the SET FAs with a static buffer), together with a new SET FA design (based on capacitive SET threshold logic gates), will also be described and compared with the other SET FAs.

Robust Fault Detection and Isolation Using Robust l1 Estimation

The application of robust 1 estimation to robust fault detection and isolation (FDI) is considered. This is accomplished by developing a series, or bank, of robust estimators (full-order observers), each of which is designed such that the residual will be sensitive to a certain fault (or faults) while insensitive to the remaining faults. Robustness is incorporated by ensuring that the residual remains insensitive to exogenous disturbances as well as modeling uncertainty. Mixed structured singular value and 1 theories are used to develop the appropriate threshold logic to evaluate the outputs of the estimators used for determining the occurrence and location of a fault. A real-coded genetic algorithm is used to obtain the estimator gain matrices. This approach to FDI is successfully demonstrated using a linearized model of a jet engine.

A study of slope stability prediction using neural networks

The determination of the non-linear behaviour of multivariate dynamic systems often presents a challenging and demanding problem. Slope stability estimation is an engineering problem that involves several parameters. The impact of these parameters on the stability of slopes is investigated through the use of computational tools called neural networks. A number of networks of threshold logic unit were tested, with adjustable weights. The computational method for the training process was a back-propagation learning algorithm. In this paper, the input data for slope stability estimation consist of values of geotechnical and geometrical input parameters. As an output, the network estimates the factor of safety (FS) that can be modelled as a function approximation problem, or the stability status (S) that can be modelled either as a function approximation problem or as a classification model. The performance of the network is measured and the results are compared to those obtained by means of standard analytical methods. Furthermore, the relative importance of the parameters is studied using the method of the partitioning of weights and compared to the results obtained through the use of Index Information Theory.

Rules, similarity, and threshold logic

Rules and similarity are two sides of the same phenomenon, but the number of features has nothing to do with transition from similarity to rules; threshold logic helps to understand why.

Threshold network synthesis and optimization and its application to nanotechnologies

We propose an algorithm for efficient threshold network synthesis of arbitrary multioutput Boolean functions. Many nanotechnologies, such as resonant tunneling diodes, quantum cellular automata, and single electron tunneling, are capable of implementing threshold logic efficiently. The main purpose of this work is to bridge the current wide gap between research on nanoscale devices and research on synthesis methodologies for generating optimized networks utilizing these devices. While functionally-correct threshold gates and circuits based on nanotechnologies have been successfully demonstrated, there exists no methodology or design automation tool for general multilevel threshold network synthesis. We have built the first such tool, threshold logic synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with 56 multioutput benchmarks indicate that, compared to traditional logic synthesis, up to 80.0% and 70.6% reduction in gate count and interconnect count, respectively, is possible with the average being 22.7% and 12.6%, respectively. Furthermore, the synthesized networks are well-balanced structurally. The novelty of this work lies in the introduction of the first comprehensive synthesis methodology and tool for general multilevel threshold logic design.

Uncertainty of Data, Fuzzy Membership Functions, and Multilayer Perceptrons

Probability that a crisp logical rule applied to imprecise input data is true may be computed using fuzzy membership function (MF). All reasonable assumptions about input uncertainty distributions lead to MFs of sigmoidal shape. Convolution of several inputs with uniform uncertainty leads to bell-shaped Gaussian-like uncertainty functions. Relations between input uncertainties and fuzzy rules are systematically explored and several new types of MFs discovered. Multilayered perceptron (MLP) networks are shown to be a particular implementation of hierarchical sets of fuzzy threshold logic rules based on sigmoidal MFs. They are equivalent to crisp logical networks applied to input data with uncertainty. Leaving fuzziness on the input side makes the networks or the rule systems easier to understand. Practical applications of these ideas are presented for analysis of questionnaire data and gene expression data.

The Cut Number of the n-Cube, Boolean Methods and a Geometric Connection to Threshold Logic

The Cut Number of the n-Cube, Boolean Methods and a Geometric Connection to Threshold Logic

Pass-transistor based implementations of threshold logic gates for WOS filtering

This paper presents a systematic procedure to implement threshold functions by using a pass-transistor network. A main feature of the threshold gates (TGs) produced by this technique is that they do not exhibit the fan-in limitations usual when other implementation techniques are used. Thus, they are especially useful for Weighted Order Statistical (WOS) filters because the binary filters required are threshold functions which usually present a high total sum of weights. A WOS filter with its binary filters implemented as pass-transistor TGs is demonstrated in an standard 0.35μm CMOS technology at 3.3V. The filter shows a sample frequency well over 100MHz at the nominal process condition and it is cheaper, faster and consumes less power than a conventional approach.

Reconfigurable magnetoelectronic circuits for threshold logic

AbstractMagnetoelectronic devices, which combine ferromagnetic materials with conventional silicon structures, offer the potential to add non‐volatile storage to electronic systems, eliminating their vulnerability to data loss due to power supply interruptions. We present a set of circuits, based on the Hybrid Hall Effect device, that combine logic with non‐volatile storage. These circuits can be configured on a cycle‐by‐cycle basis to compute different functions of their inputs, store their outputs indefinitely even in the absence of system power, and can be easily integrated into CMOS systems to provide non‐volatile operation without requiring additional supply voltages or other global signals. They exploit the properties of the Hybrid Hall Effect device to efficiently implement threshold logic functions and thereby reduce the number of gates required to implement most Boolean expressions.In this paper, we describe our reconfigurable magnetoelectronic circuits and the interfaces that make them compatible with CMOS systems. The results presented are based on data from fabricated experimental devices, and we discuss how they can be expected to improve as devices scale to nanometer dimensions. Finally, we consider how magnetoelectronic circuits might be integrated into system designs to deliver high performance while tolerating power supply interruptions. Copyright © 2004 John Wiley & Sons, Ltd.

Realisation of multiple-valued functions using the capacitive threshold logic gate

The circuit-level hardware realisation of several multiple-valued logic functions using the capacitive threshold logic design style is presented. The generic design approach for multiple-input, multiple-output and multiple-level transfer functions is shown. SPICE simulations of complex operators demonstrate correct operation which qualifies the proposed circuits for integration into larger multiple-valued logic systems. An analysis of noise margin figures and comparisons with previously published circuit examples are provided.

A new theorem in threshold logic and its application to multioperand binary adders

We present a new theorem in Threshold Logic which is a generalization of Mezei's theorem. We demonstrate one of its applications, i.e., the optimization of the size of depth-2 Multioperand Binary Adders. By applying this theorem, the weight complexity of the gates in the second layer of a previous construction is reduced from O(m·2 n ) to O(1), where m is the number of operands and n is the number of bits.

VLSI implementations of threshold logic- a comprehensive survey

This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

A compact 3-D VLSI classifier using bagging threshold network ensembles

A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three-dimensional (3D) multiprecision very large-scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks - one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7-/spl mu/m CMOS technology and packaged using MCM-V micro-packaging technology. The 3D chip implements up to 192 TLUs operating at a speed of up to 48 GCPPS and implemented in a volume of (/spl omega/ /spl times/ L /spl times/ h) = (2 /spl times/ 2 /spl times/ 0.7) cm/sup 3/. The 3D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.

Multi-threshold threshold logic circuit design using resonant tunnelling devices

A novel and extremely compact circuit topology able to implement a generalised threshold logic function with two thresholds is presented. The circuit consists of resonant tunnelling diodes and heterostructure field effect transistors.

Low depth, low power carry lookahead adders using threshold logic

This paper describes a low power threshold logic-gate based on a capacitive input, charge recycling differential sense amplifier latch. The gate is shown to have low power dissipation and high operating speed, as well as robustness under process, temperature and supply voltage variations. This is followed by the main result, which is the development of a novel, low depth, carry lookahead addition scheme based on threshold logic. One such adder is also designed and simulated using the proposed gate.

Hysteretic threshold logic and quasi-delay insensitive asynchronous design

We introduce the class of hysteretic linear-threshold (HLT) logic functions as a novel extension of linear threshold logic, and prove their general applicability for constructing state-holding Boolean functions. We then demonstrate a fusion of HLT logic with the quasi-delay insensitive style of asynchronous circuit design, complete with logical design examples. Future research directions are also identified.

Auditory stimulus optimization with feedback from fuzzy clustering of neuronal responses.

The primary focus of this paper was to develop a high-performance computer system for optimizing auditory stimuli based on neuronal feedback. Using the Algorithm Of Pattern EXtraction (ALOPEX) extra-cellular action potentials (APs) recorded from frog (Rana Pipiens) auditory neurons were used as feedback to optimize sound stimuli. This computer-based system works in real time to iteratively find the neuron's best excitatory frequency (BEF). Three programmable (positive and negative) threshold logic levels are used to collect 300 APs in response to normalized pure tones. Fuzzy logic is then used to separate up to five fuzzy centers (templates) from the 300 APs. The fuzzy centers are used for on-line fuzzy mapping of future responses. The five fuzzy centers allow the system to monitor up to five neighboring neurons. To study the auditory neurons of the frog, one, two, and three simultaneous tones are used as the stimulus for optimization of the best combination of frequencies. Testing with the response calculated as a parabolic function of a single best frequency demonstrated system dynamics and reliability for up to nine simultaneous tones. Experiments using one pure tone and ten stimulus presentations per iteration showed that the automated system is able to repeatedly converge to the best frequency within 100 iterations. Studies using one, two, and then three pure tones played simultaneously on the same group of neurons has shown that these tones converged on the same best frequencies by properly mixing the tones available to produce the optimal complex sound.

Method and apparatus for automatic muting of Doppler noise induced by ultrasound probe motion

A method and an apparatus for monitoring the wall signal input to the wall filter of a spectral Doppler processor to check for probe-motion-induced clutter. This clutter is typically of higher frequency and amplitude than that due to normal vessel wall motion. Some additional threshold logic is used to check for energy within a frequency band greater than the normal wall signal frequencies. If significant energy above some “rattle” threshold is detected for a predefined time interval, the Doppler audio is automatically muted. This can be effected at one or more points within the normal Doppler audio signal path in a conventional scanner. If the rattling clutter is no longer detected, the Doppler audio is re-activated or ramped up smoothly.