Threshold Inverter Quantization Research Articles

Landauer-QFLPS Model for Mixed Schottky-Ohmic Contact Two-Dimensional Transistors.

Two-dimensional material-based field-effect transistors (2DM-FETs) are playing a revolutionary role in electronic devices. However, before electronic design automation (EDA) for 2DM-FETs can be achieved, it remains necessary to determine how to incorporate contact transports into model. Reported methods compromise between physical intelligibility and model compactness due to the heterojunction nature. To address this, quasi-Fermi-level phase space theory (QFLPS) is generalized to incorporate contact transports using the Landauer formula. It turns out that the Landauer-QFLPS model effectively overcomes the issue of concern. The proposed new formula can describe 2DM-FETs with Schottky or Ohmic contacts with superior accuracy and efficiency over previous methods, especially when describing non-monotonic drain conductance characteristics. A three-bit threshold inverter quantizer (TIQ) circuit is fabricated using ambipolar black phosphorus and it is demonstrated that the model accurately predicts circuit performance. The model could be very effective and valuable in the development of 2DM-FET-based integrated circuits.

Threshold Inverter Quantizer (TIQ)-Based 2-Bit Comparator Using Spatial Wavefunction Switched (SWS) FET Inverters

A Threshold Inverter Quantizer (TIQ)-based voltage comparator is used to quantize analog input signal in flash ADC designs. This quantizer is based on the systematic sizing of CMOS inverter thus eliminating resistor array which is used for conventional comparator array. Such an implementation removes static power during quantization of analog input signal. This paper presents a simulation of TIQ 2-bit-based comparator using spatial wavefunction switched (SWS) field effect transistor (FET)-based CMOS inverters. The inverters use 4-state SWSFETs. Unlike conventional FETs, SWSFETs consist of two or more vertical coupled arrays of either quantum dot or quantum well channels, where the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10), and (11). The TIQ-based comparator circuit presented here is based on the 2-bit SWS-CMOS inverter. The schematic of the ADC comparator circuit is demonstrated as well as the 2-bit ADC configuration cascading two 2-bit SWSFET-based inverters in CMOS-X. The circuit simulation was done in Cadence and SWSFET was modeled by integrating Berkeley Short-Channel IGFET Model (BSIM) and the Analog Behavioral Model (ABM). The 2-bit comparator circuit provides a four-state logic output voltage for any given analog input signal.

180 nm FLASH ANALOG TO DIGITAL CONVERTOR

In this paper, Threshold Inverter Quantizer (TIQ) is a novel idea which can effectively replace the reference voltage generator, resistive/capacitive voltage divider network and array of differential comparators in a conventional flash Analog to Digital Converter (ADC) by an internal reference comparator array constructed of Complementary Metal Oxide Semiconductor (CMOS) inverters. The inverter threshold voltage serving as the reference voltage, this architecture claims large improvements in terms of silicon area, power consumption and operating speed. Perturbations due to sensitivity of the inverter threshold voltage to operating temperature/process variations pose impediments in such ADC designs and strongly demand a compensation scheme to such variations. This paper presents a TIQ based flash ADC, with inverter threshold voltage compensation. In this project 5 bit flash adc using TIQ Comparator is designed and simulated using TANNER EDA in 180nm technology. Key Words: flash, adc, tiq(threshold inverter quantization)

Temperature dependence of TIQ flash ADC

Threshold Inverter Quantizer (TIQ) is an innovative idea in the construction of flash ADC, which can effectively replace the reference voltage circuit, resistive or capacitive voltage divider and differential comparator array in a conventional flash ADC by an internal reference comparator array made of CMOS inverters. The inverter switching voltage serving as the internal reference voltage, this architecture offers large improvements in chip area, power consumption and operating speed of the ADC. Variations of the inverter switching voltage due to its sensitivity to operating temperature and process variations causes imperfections in this ADC designs. This paper presents the thermal dependencies TIQ based flash ADC architecture. The complete circuit is modelled in cadence virtuoso simulation suite with gpdk 180 nm design library.

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks-an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

A Novel Rail-to-Rail Input Swing Threshold-Inverter Multi-Bit Quantizer Using Interpolation Technique for Sampled-Data Circuits

In this paper, a novel and simple multi-bit quantizer based on the threshold inverter quantization (TIQ) approach is presented for use in sampled-data circuits. The key part is a front-end signal conditioning circuit with the aid of the interpolation technique that makes it possible to realize a rail-to-rail input range operation over the conventional threshold inverter-based quantizer circuits while maintaining the benefits of the TIQ structure without employing any analog-intensive circuits such as current sources or amplifiers, thus achieving a digital-compatible implementation. Simulation results in TSMC 90-nm CMOS technology at a power-supply voltage of 1[Formula: see text]V confirm the efficient performance of the proposed circuit.

3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs

Multi-valued logic using multi-state spatial wavefunction switched (SWS)-FETs offers overall reduction in size and power as compared to conventional FET based circuits. This paper presents the design of compact 3-bit Analog-to-Digital Converters (ADC) implemented with SWS-FETs. A novel multi-valued Threshold Inverter Quantization (TIQ) based voltage comparator using SWS FET transistors has been proposed. Unlike conventional FETs, SWS-FETs are comprised of two or more vertically stacked coupled quantum well or quantum dot channels, and the spatial location of carriers within these channels is used to encode the logic states (00), (01), (10) and (11). The SWS-FET logic and circuit models for complementary (n- and p-channel) using 20 nm technology are presented. The digital logic circuit in the ADC is developed using SWS-FET based quaternary logic circuits. The accuracy of the SWS-FET circuits is verified by SWS-FET models in Cadence. The simulations for the SWS FET are based on integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The ADC circuit design using SWS-FETs reduce the number of transistors by 55% compared with CMOS counterpart.

A Suggestive Low Power TIQ Comparator Architecture using Adiabatic Logic for Implementation of 3-bit Flash type ADC.

Power consumption is prime concern for the designers in modern day scenario. For the devices that are power-driven by tiny rechargeable or non-rechargeable batteries over the entire life period, such as medical transplant devices or portable medical instruments, necessitates lowest possible power consumption. In these devices Analog-to-Digital Converter (ADC) isdynamic component to provide connectionamongstAnalog and Digital system. The paper is aimed to report the design contests and tactics for low power ADCs which are used in biomedical graft devices and instruments. A comparator module of ADCs used in designing of such devices requires more power than other blocks in the device, a low power comparator is suggested for Threshold-Inverter-Quantizer (TIQ)usingDiode-Free-Adiabatic-Logic (DFAL) to implement Flash type ADCs. The projected 3-bit Flash ADC is simulated using Cadence ® Virtuoso IC616 with TSMC 65nm technology. The ADC was simulated atpeak to peak voltage of 1.2V andcapacitive load of 1fF,results in consumption of5.53 μW of average power, which is 66.03 % lesser relative toconservative CMOS-TIQ based comparator. Observed static parameters are: DNL is equal to-0.62 / + 0.57 LSB and INL is equal to- 0.44/ +0.41 LSB.Dynamic parameters observed results are as: THD = -25.25dB, SNR=19.45 dB, SNDR=18.39 dB, ENOB=2.76 bits, SFDR = 23.4 dB.

TIQ Flash ADC Design using a Low Power Multiplier Based Encoder

Threshold Inverter Quantization (TIQ) for applications of system-on-chip (SoC) depending on CMOS flash analog-to-digital converter (ADC). The TIQ technique which uses two cascaded CMOS inverters as a voltage comparator. However, this TIQ method must be created to meet the latest SoC trends, which force ADCs to be integrated with another electronic circuit on the chip and focus on low-power and low-voltage applications. TIQ comparator reduced the impact of variations in the process, temperature, and power supply voltage. Therefore, we obtained a higher TIQ flash ADC speed and resolution. TIQ flash ADC reduced / managed power dissipation. We obtain large power savings by managing the power dissipation in the comparator. Furthermore, the new comparator has a huge benefit in power dissipation and noise rejection comparative to the TIQ comparator [1]. The findings indicate that the TIQ flash ADC based on Modied mux attain heavy-speed transformation and has a tiny size, low-power dissipation and operation of lowvoltage compared to another flash ADCs.

10-Bit Flash ADCs and Beyond: An Automated Framework for TIQ Flash ADCs Design

In this work we introduce the flash ADC design automation (FADA) framework. It aims to reduce the design time of the threshold inverter quantization (TIQ) flash ADCs and optimizes the selected TIQ comparators of the flash ADC for differential nonlinearity (DNL), integral nonlinearity (INL), analog voltage range, power consumption and comparator noise values. We performed a survey study on flash ADCs published in the last two decades and compared them to our 10-bit single-channel TIQ flash ADC. Further, it took FADA < 6 h to design the 10-bit TIQ flash ADC compared to few weeks of manual design. Accordingly, FADA selected TIQ comparators set for the 10-bit TIQ flash ADC with DNL and INL values less than 0.17 LSB and 0.16 LSB, respectively, when designed in the ibm65n CMOS technology. The 10-bit TIQ flash ADC has simulated signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) values of 57.2 dBs and 61 dBs, respectively. It consumes 1.67 mW of power and operates at 1.57 GSample/s. FADA provides TIQ models to optimize for high-performance versus low-noise TIQ flash ADCs designs.

Design and implementation of reliable flash ADC for microwave applications

Analog to Digital Converter (ADC) is a necessary component of mixed signal designs. It converts the analog signal to the digital signal so that it is used as a bridge. This paper proposes R-Flash ADC (Reliable Flash ADC) which combines an area efficient multiplexer pass gate (MPG) encoding technique and low power ITIQ (Improved Threshold Inverter Quantization) comparator. The proposed Flash ADC is implemented using tanner EDA with 125 nm technology. R-Flash ADC reduces the number of transistors by 39% and reduces the power consumption by 59% with high resolution quality when compared to Mux TIQ ADC. The reliability analysis shows that the proposed R-Flash ADC has reliability of 95% and it overcomes the existing techniques as well.

A Novel CNFET Technology Based 3 Bit Flash ADC for Low-Voltage High Speed SoC Application

The continuous scaling down of metal-oxide-semiconductor field effect transistors (MOSFETs) led to the considerable impact in the analog-digital mixed signal integrated circuit design for system-on-chips (SoCs) application. SoCs trends force ADCs to be integrated on the chip with other digital circuits. These trends present new challenges in ADC circuit design based on existing CMOS technology. In this paper, we have designed and analyzed a 3-bit high speed, low-voltage and low-power flash ADC at 32nm CNFET technology for SoC applications. The proposed ADC utilizes the Threshold Inverter Quantization (TIQ) technique that uses two cascaded carbon nanotube field effect transistor (CNFET) inverters as a comparator. The TIQ technique proposed has been developed for better implementation in SoC applications. The performance of the proposed ADC is studied using two different types of encoders such as ROM and Fat tree encoders. The proposed ADCs circuits are simulated using Synopsys HSPICE with standard 32nm CNFET model at 0.9 input supply voltage. The simulation results show that the proposed 3 bit TIQ technique based flash ADC with fat tree encoder operates up to 8 giga samples per second (GSPS) with 35.88µW power consumption. From the simulation results, we observed that the proposed TIQ flash ADC achieves high speed, small size, low power consumption, and low voltage operation compared to other low power CMOS technology based flash ADCs. The proposed method is sensitive to process, temperature and power supply voltage variations and their impact on the ADC performance is also investigated.

&lt;b&gt;Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC) by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ)-comparator, the encoder and the parallel input serial output (PISO) register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm 2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

STUDY AND IMPLEMENTATION OF COMPARATOR IN CMOS 50NM TECHNOLOGY

This paper describes the comparator circuits used in FLASH Analog to digital converter (ADC). The performance of FLASH ADC is greatly influenced by the choice of comparator. In this paper, first a single ended “Threshold Inverter Quantizer” (TIQ) is presented. The TIQ comparator is based on a CMOS inverter cell, in which voltage transfer characteristics (VTC) are changed by systematic transistor sizing. However, TIQ comparator is very sensitive to power supply noise. Another comparator circuit presented in this paper is “Two stage open loop comparator”. It is implemented in 50 nm CMOS Technology. Pre-simulation of comparator is done in LT-Spice and post layout simulation is done in Microwind 3.1.

An area-efficient 55 nm 10-bit 1-MS/s SAR ADC for battery voltage measurement

An area-efficient CMOS 1-MS/s 10-bit charge-redistribution SAR ADC for battery voltage measurement in a SoC chip is proposed. A new DAC architecture presents the benefits of a low power approach without applying the common mode voltage. The threshold inverter quantizer (TIQ)-based CMOS Inverter is used as a comparator in the ADC to avoid static power consumption which is attractive in battery-supply application. Sixteen level-up shifters aim at converting the ultra low core voltage control signals to the higher voltage level analog circuit in a 55 nm CMOS process. The whole ADC power consumption is 2.5 mW with a maximum input capacitance of 12 pF in the sampling mode. The active area of the proposed ADC is 0.0462 mm2 and it achieves the SFDR and ENOB of 65.6917 dB and 9.8726 bits respectively with an input frequency of 200 kHz at 1 MS/s sampling rate.

Low Power CMOS Data Converter with SNDR analysis for High Speed System On Chip Applications

In modern era of advanced VLSI design the transistor sizing and scaling has an considerable impact. There are very essential two constrains, which needs serious attention to the VLSI chip designer are high speed and low power consumption. Therefore in this paper an 8-bit 3 Gs/sec flash analog-to-digital data converter (ADC) in 45nm CMOS technology is presented for low power and high speed system-on-chip (SoC) applications. This low power 8-bit flash Analog to Digital data converter comprises 255 comparators and one thermometer to binary encoder. This flash ADC design is an extended research work of the earlier work related to ADC design using CMOS process technology. The schematic simulation of ADC is done in Tanner-Spice Pro (S-Edit) and layout simulation is done in Tanner-Spice Pro (L-Edit) V.15.14. The Simulated result shows the power consumption in Flash ADC is 41.78μw. The Threshold Inverter Quantization (TIQ) technique is proposed to get WPMOS/WNMOS < 1 for transistors to keep the power consumption as low as possible. It is also observed that the ADC consumes 41.78μW of peak power and 6.45μW of average power at full speed while it operates on a power supply voltage of 0.6V. Compared with the earlier work, this project consumes less power and high speed with proposed TIQ technique gives an edge in SoC based VLSI design. Finally the Signal to Noise Distortion analysis is done to obtain more precise data conversion results. The SNDR was found 31.9dB for ultimate precise data conversion using 45nm CMOS process technology.

Employing Threshold Inverter Quantization (TIQ) technique in designing 9-Bit folding and interpolation CMOS analog-to-digital converters (ADC)

This paper presents design and implementation of a 9-bit folding and interpolation ADC using 0.35 µm CMOS C35B4 model under AMS-HIT Kit Library. The complete system consists of two main blocks. One of them is 4-bit flash ADC, which is based on the so-called Threshold Inverter Quantization (TIQ) technique. This part forms the coarse part of the data conversion process. The second one is the 5-bit fine ADC part of the converter. This block includes comparator, analog pre-processing and interpolation units. The designed converter works with 5 V power supply, and has analog input range of 3.4 Vpp. Analog input bandwidth is 1 MHz with clock frequency of 2 GHz for the digital part. The linearity measures of the converter include 2.9 LSB of DNL and 6.3 LSB of INL. The main purpose of this work is to investigate the possibility of employing TIQ technique in designing folding and interpolation type of ADCs. Although, the linearity measures are not satisfying for 9-bit case, the authors believe that this case study will serve as a preferred reference for the researchers who are willing to use TIQ technique in designing fast ADCs other than flash scheme especially. Key words: Threshold inverter quantization, flash analog-to-digital converter, folding and interpolation analog-to-digital converter.

A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS

Data converters are needed to interface between the physical world of analog signals and the digital world of signal processing, computing and data processing. Full flash converter is considered as the fastest converter type. The problems associated with small signal and clock delays of larger size structures limit the accuracy and introduce distortion and therefore improved converter systems with a reduced chip area are desirable. With few comparators compared to flash, folding and interpolation architectures are good option for low-power implementations of medium resolution (4b to 10b), high speed (tens or hundreds mega samples per second (MSample/s)) analog-to-digital converters (ADCs). This paper describes the concept of threshold inverter quantization based folding amplifier. The reference ladder using resistors is replaced by inverters and as a result the area and static power dissipations are expected to be lower. Introduction of inverters would reduce the node capacitances and the transition of signals would be faster. The proposed method is very sensitive to process variations and their impact on the ADC performance is investigated.

Improved Complementary Metal Oxide Semiconductor Digital Pixel Sensor

Charge Coupled Devices (CCDs) are used in imaging as they have advantages over conventional bulky tube type TV cameras. The complementary metal oxide semiconductor (CMOS) based image sensors, passive pixel sensors (PPS), and active pixel sensor (APS) have advantages in implementation. This makes the APS competitive with CCDs. However, APS is not popular because of the poor All factor and lack of resolution. With the development of image sensor technology, digital pixel sensor (DPS) has overcome all problems associated with CCDs and CMOS-APS image sensor. In DPS, comparator and memory are implemented on chip for each pixel. This results in benefits in terms of power, pixel size, fill factor and resolutions. This paper analyses earlier DPS pixel with an analog comparator and inverter-based comparator. The limitations reported in the analysis of analog comparator are overcome using cascaded CMOS inverter-based comparator. The cascaded CMOS inverter is built with proper adjustment of Width (W) to Length (L) ratio. This adjustment sets the threshold voltage ‘Vth ’ that remains fixed for the pixel (in our case Vth is equal to 2.2V). This cascaded inverter based comparator is called as threshold inverter quantizer (TIQ) and is further analyzed with biasing for high gain. Four-pixel and 16-pixel array design is done using TIQ based pixel. Extensive simulation of the TIQ based pixel array is done and results are reported for current and power dissipation.

Digital Hysteretic Voltage-Mode Control for DC–DC Converters Based on Asynchronous Sampling

This paper investigates a digital voltage-mode controller for dc-dc converters based on hysteresis modulation. The control structure implements a high-bandwidth hysteretic differentiator as its main building block, and realizes a nonconventional structure of PID compensation with performances comparable to analog hysteretic controls, thus breaking the bandwidth and dynamic limitations commonly encountered in typical digital control arrangements. The employment of an asynchronous A/D converter based on the threshold inverter quantization concept dramatically shrinks the average delay time that separates the sampling instant from the corrective control action. Moreover, the hysteretic nature of the derivative action results in an inherent nonlinear response to large signal load variations, which translates into fast control intervention and reduced settling times. The hysteretic differentiator employs a ring-oscillator-based modulator, which ensures resolution up to 390 ps without asking for a high-frequency clock. Both the 6-bit asynchronous A/D converter and the ring-oscillator-based modulator are designed and manufactured in the same IC using a standard 0.35 mum CMOS process. Analytical modeling, computer simulations, and experimental results on a synchronous buck converter confirm the validity of the approach and the dynamic performances achievable by the proposed control architecture.