A threshold inverter quantization based folding and interpolation ADC in 0.18 μm CMOS

Abstract

Data converters are needed to interface between the physical world of analog signals and the digital world of signal processing, computing and data processing. Full flash converter is considered as the fastest converter type. The problems associated with small signal and clock delays of larger size structures limit the accuracy and introduce distortion and therefore improved converter systems with a reduced chip area are desirable. With few comparators compared to flash, folding and interpolation architectures are good option for low-power implementations of medium resolution (4b to 10b), high speed (tens or hundreds mega samples per second (MSample/s)) analog-to-digital converters (ADCs). This paper describes the concept of threshold inverter quantization based folding amplifier. The reference ladder using resistors is replaced by inverters and as a result the area and static power dissipations are expected to be lower. Introduction of inverters would reduce the node capacitances and the transition of signals would be faster. The proposed method is very sensitive to process variations and their impact on the ADC performance is investigated.