Three-stage Doherty Power Amplifier Research Articles

Design of Inner Matching Three-Stage High-Power Doherty Power Amplifier Based on GaN HEMT Model.

This paper introduces the structure and characteristics of an internal-matching high-power Doherty power amplifier based on GaN HEMT devices with 0.25 μm process platforms from the Nanjing Electronic Devices Institute. Through parameter extraction and load-pull testing of the model transistor, an EE_HEMT model for the 1.2 mm gate-width GaN HEMT device was established. This model serves as the foundation for designing a high-power three-stage Doherty power amplifier. The amplifier achieved a saturated power gain exceeding 9 dB in continuous wave mode, with a saturated power output of 49.7 dBm. The drain efficiency was greater than 65% at 2.6 GHz. At 9 dB power back-off point, corresponding to an output power of 40.5 dBm, the drain efficiency remained above 55%. The performance of the amplifier remains consistent within the 2.55-2.62 GHz frequency range. The measured power, efficiency, and gain of the designed Doherty power amplifier align closely with the simulation results based on the EE_HEMT model, validating the accuracy of the established model. Furthermore, the in-band matching design reduces the size and weight of the amplifier. The amplifier maintains normal operation even after high and low-temperature testing, demonstrating its reliability. In conjunction with DPD (digital pre-distortion) for the modulated signal test, the amplifier exhibits extremely high linearity (ACLR < -50.93 dBc). This Doherty power amplifier holds potential applications in modern wireless communication scenarios.

Dual Input Digitally Controlled Broadband Three-Stage Doherty Power Amplifier With Back-Off Reconfigurability

This article presents a design strategy to improve the bandwidth of the three-stage Doherty Power Amplifier (DPA) by controlling the phase difference between the dual RF inputs digitally. The theory also proposes multiple back-off reconfigurability without using tuning elements and extra circuitry. The proposed theory is validated by demonstration of a dual-input three-stage DPA which is designed and implemented using Wolfspeed’s GaN HEMT transistors. The measured results show a drain efficiency of 50.4 – 58% and 46.1 – 65.4% at 12 dB and 6 dB back-off respectively, over the frequency range of 550-900 MHz. Over this 350 MHz band, the drain efficiency is between 53.97% and 71.5% at saturation, corresponding to 48.3% fractional bandwidth. The measurement results also show that both the back-offs are reconfigurable by changing the drain bias of main and first auxiliary power amplifier. The modulated measurements are carried with a 10 MHz LTE signal with a PAPR of 11.75 dB. The high average efficiency of 51.6%, 54.9%, and 52.6% is reported at 600, 700, and 800 MHz, respectively, at an average power of around 30 dBm. The measurement results validate the theory proposed making the presented DPA as a potential candidate for future wireless transmitters.

Improved Three-Stage Doherty Amplifier Design With Impedance Compensation in Load Combiner for Broadband Applications

This paper presents a broadband three-stage Doherty power amplifier (DPA) using impedance compensation for bandwidth extension. Different from the conventional design, an impedance-compensating load combiner is proposed to broaden the bandwidth of the three-stage DPA by employing the output impedances of the peaking amplifiers. Considering the load impedance of the peaking branch as an independent design variable, the Doherty load modulations are analyzed in theory, pointing out the optimized solution for the load combiner. To achieve the impedance compensation, the peaking output matching networks are deliberately designed with the dual-impedance matching topology. Experimental results show that a three-stage DPA is realized from 1.6 to 2.6 GHz (48% fractional bandwidth) with a measured efficiency of 50%-53% at 9.5-dB back-off and a saturated output power around 45.5 dBm. When stimulated by the 20- and 40-MHz modulated signals at an average output power of around 36.5 dBm, the proposed DPA can achieve the adjacent channel leakage ratio of -50 dBc over the whole frequency band after linearization, with an average efficiency of higher than 50%.

A Design Strategy for Bandwidth Enhancement in Three-Stage Doherty Power Amplifier With Extended Dynamic Range

This paper presents a design strategy to enhance the bandwidth of three-stage Doherty power amplifier (DPA) with operation upto 12-dB back-off. Based on the proposed strategy, a broadband 48-W DPA is designed and implemented using packaged CREE GaN transistors. The measured drain efficiency of 50%–61.8% at 12-dB back-off and 51.9%–66.2% at 6-dB back-off is obtained over the frequency range of 600–900 MHz. Over this 300-MHz band, the drain efficiency is between 51.1% and 78% at saturation. This corresponds to 40% fractional bandwidth. The three-stage DPA is also linearized with a three carrier 15-MHz WCDMA signal with a PAPR of 10.6 dB at various frequencies within operating band and shows the output signal qualifies spectral mask specifications.

Bandwidth Enhancement of Three-Stage Doherty Power Amplifier Using Symmetric Devices

This paper proposes a design scheme for extending the bandwidth of a three-stage Doherty power amplifier (DPA) based on symmetric devices for broadband applications. The proposed bandwidth enhancement scheme provides an optimized solution for the load combiner parameters while operating the auxiliary power amplifier (PA) at lower current values as compared to the main PA at saturation. The proposed scheme promises 30.3% fractional bandwidth in terms of efficiency enhancement up to 9.54-dB back-off. The proposed design methodology is validated with the design of a broadband three-stage DPA using three 10-W packaged GaN HEMT devices. Measurement results show more than 51.6% drain efficiency at 6-dB output power back-off (OPBO) over the entire frequency range from 700 to 950 MHz. At 9.54-dB OPBO, the drain efficiency is better than 50.2% over this 250-MHz band. The peak drain efficiency at saturation is better than 60.04% over the entire band of operation. Measurement with 5-MHz WCDMA modulated signal shows the average drain efficiency of about 57.6% at 33.97-dBm average output power at the center frequency of operation. The corresponding adjacent channel power ratio is better than ${-}{\hbox{45.6}}$ dBc after applying digital predistortion. The circuit is realized with microstrip technology, which can be easily fabricated using conventional printed circuit processes.

Optimized Design of a Highly Efficient Three-Stage Doherty PA Using Gate Adaptation

We demonstrate an optimized design of a highly efficient three-stage Doherty power amplifier (PA) for the 802.16e mobile world interoperability for microwave access (WiMAX) application at 2.655 GHz. The “three-stage” Doherty PA is the most efficient architecture among the various Doherty PAs for achieving a high peak to average power ratio (PAPR) signal. However, it has a problem in that the carrier PA has to maintain a saturated state with constant output power when the other peaking PAs are turned on. We solved the problem using a gate envelope tracking (ET) technique. For the proper load modulation, the gate biases of the peaking PAs were adaptively controlled, and the peak power and maximum efficiency characteristics along the backed-off output power region were successfully achieved. Using Agilent's Advanced Design System and Matlab simulations, the overall behavior of the three-stage Doherty PA with the ET technique employed was fully analyzed, and the optimum design procedure is suggested. For the WiMAX signal with a 7.8-dB PAPR, the measured drain efficiency of the proposed three-stage Doherty PA is 55.4% at an average output power of 42.54 dBm, which is an 8-dB backed-off output power. Digital predistortion was used to linearize the proposed PA. After linearization, a -33.15 dB relative constellation error performance was achieved, satisfying the system specifications. This is the best performance of any 2.655-GHz WiMAX application ever reported, and it clearly shows that the proposed three-stage Doherty PA is suitable as a highly efficient and linear transmitter.

A Highly Efficient Three-Stage Doherty Power Amplifier with Flat Gain for WCDMA Applications

A three-stage Doherty power amplifier (DPA) with a flat gain is represented. The driving amplifier at an input of peaking cells is used to achieve high efficiency and flat gain to control the input power level of peaking cells. For the experimental validation, the proposed DPA is implemented using a GaN HEMT and Si LDMOSFETs. For a continuous wave signal, power-added efficiencies of 34.0% and 39.3% are obtained at 8.5-dB back-off power (BOP) and 4.0-dB BOP from the saturation output power, respectively. The measured one-carrier wideband code division multiple access results show high efficiency and flat gain characteristics above 10 dB over the entire output power range.