Three-level Space Vector Pulse Width Modulation Research Articles

Research on Optimization Simulation of Three-level Inverter in UPS Based on PSO Algorithm

As a kind of precision power equipment, the uninterruptible power supply system (UPS) can supply power to the load through a DC-AC converter to ensure the uninterrupted power supply in case of grid failure. The voltage waveform output by the inverter has a decisive effect on the power quality, performance of the UPS system is determined by the power quality. Therefore, this paper aims to optimize the output power of the inverter from two aspects: on the one hand, the three-level space vector pulse-width modulation (SVPWM) technology is combined with the double closed-loop control system to improve the voltage waveform of the inverter; On the other hand, the PI parameters in the double closed loop are optimized by the particle swarm optimization (PSO) algorithm, the dynamic performance of the system is optimized, the adjustment time and overshoot are reduced, thus the control performance of the UPS system is improved.

An Analytical Simplified Three-Level SVPWM With Unified Zero-Sequence Component Injection

The carrier-based pulse width modulation (CBPWM) with zero-sequence component injection is equivalent to the space-vector PWM (SVPWM), and hence it can be taken as a simplified alternative to the SVPWM. However, it is quite complex to calculate the zero-sequence component in CBPWM for three-level (3L) converters such as the T-type converter, making the 3L SVPWM still have a large computation burden. In this letter, unified expressions for the zero-sequence component are analytically derived, and the modulation waves of 3L SVPWM can be directly calculated by only 7 simple equations with 3 steps. The computation burden for implementing 3L SVPWM is therefore significantly reduced without sector determination, calculation and assignment of dwell times.

Research on an Improved Three-Level SVPWM Modulation Algorithm Based on ID-NPC Topology

The conventional three-level SVPWM (Space Vector Pulse Width Modulation) algorithm is a basic modulation algorithm, which can be performed easily due to clear modulation ideas. Considering different criteria for sectors, however, the basic vector action time is calculated repeatedly, the selection of vector action sequence is cumbersome, and the algorithm execution time is extended as a result of processing by the digital processing chip. In order to better adapt to the PMSM (Permanent Magnet Synchronous Motor) control requirements of the ID-NPC (Improved Diodes Neutral Point Clamped) topology for converter control objects, the sector judgment part, time effect part and vector synthesis part are optimized according to the principles of saving hardware resources and shortening the execution cycle. The vector synthesis optimization algorithm of 2 × amplitude substitution and the vector synthesis algorithm of 1/2 × amplitude substitution are both proposed. Finally, the ID-NPC topology is used to verify the proposed modulation algorithm.

Modelling and Control of a Three-Level Diode-Clamped Medium Voltage Distribution Static Synchronous Compensator using Space Vector Pulse Width Modulation

Efficient utilization of power networks under extreme voltage sags and swells and reducing the losses are widely recognized as the most important issues in energy industry. Power electronic converter based flexible AC transmission system (FACTS) devices play a significant role in power flow control, power quality improvement, voltage regulation and efficient energy utilization. Distribution static synchronous series compensator (D-STATCOM) is a FACTS device and it compensates for voltage sags and swells by injecting or absorbing reactive power to/from the power network. Modulation of D-STATCOMs is mostly based on pulse width modulation (PWM) techniques and space vector PWM (SV-PWM) is attracting considerable interest due to its better DC utilization and wide linear modulation range. In this paper, a three-level SV-PWM is suggested for the modulation of D-STATCOM which is based on a three-phase diode-clamped inverter (DCI). A grid connected three-phase power system feeding a 1 MW and 500 kvar load is designed in simulation environment and D-STATCOM is tested under voltage sags and swells occurring on the generation side. Results demonstrate that D-STATCOM successfully injects/absorbs reactive power to/from the system under fluctuating grid conditions

Simplified double switching SVPWM implementation for three‐level VSI

A generalised space vector pulse width modulation (SVPWM) framework for the realisation of all double switching states with a memory-optimised method is proposed to reduce the total harmonic distortion (THD) and to provide neutral point voltage balancing for three-level NPC voltage source inverter (VSI). The proposal provides an efficient SVPWM implementationwith reduced hardware requirement and zero increase in software complexity in comparison to the existing schemes. Microcontroller analogue-to-digital converter (ADC) hardware replaces multichannel ADC and associated Field programmable gate array hardware in this proposal. The proposed method follows digital control architecture and eliminates the need to sample phase voltages separately. The proposed algorithm samples rms voltage of one phase and generates eight bit modulation index command by a suitable compensation algorithm. The implemented SVPWM algorithm takes the modulation index command value and generates phase voltage values by multiplying with the stored sine angle values. Gate pulses are generated in the proposed implementation by the hardware pulse width modulation (PWM) block and there is no need for digital-to-analogue converter. The proposed strategy is validated with a fundamental frequency of 50 Hz on a 2 KVA three-phase three-level insulated gate bipolar transistor-based VSI using low-cost PIC microcontroller. The superiority of the proposed method lies in providing an efficient three-level SVPWM implementation with reduced THD, neutral point voltage balancing, reduced hardware requirement, small lookup table and zero increase in the software computing overhead.

A New Direct Power Control of Three-level PWM Rectifier Based on Equivalent Space Vector

This paper analyzes basic principle of DPC of three-phase voltage-source PWM rectifier, and presents its shortcomings of high and unfixed switching frequency. On this base, it proposes the method of combining DPC and three-level voltage space vector pulse width modulation(SVPWM), which reduces and fixes switching frequency. To overcome the shortcomings of complex control and complicated calculations of traditional SVPWM algorithm, the paper proposes an equivalent three-level SVPWM algorithm of dual-carrier modulation, and in the d-q coordinates, and a control strategy of power feed forward decoupling control of traditional DPC, which realizes the dynamic decoupling of active and reactive power. The MATLAB/SIMULINK simulations verify the feasibility of this control strategy.

Losses analysis of soft magnetic ring core under sinusoidal pulse width modulation (SPWM) and space vector pulse width modulation (SVPWM) excitations

Practical core losses in electrical machines differ significantly from those experimental results using the standardized measurement method, i.e. Epstein Frame method. In order to obtain a better approximation of the losses in an electrical machine, a simulation method considering sinusoidal pulse width modulation (SPWM) and space vector pulse width modulation (SVPWM) waveforms is proposed. The influence of the pulse width modulation (PWM) parameters on the harmonic components in SPWM and SVPWM is discussed by fast Fourier transform (FFT). Three-level SPWM and SVPWM are analyzed and compared both by simulation and experiment. The core losses of several ring samples magnetized by SPWM, SVPWM and sinusoidal alternating current (AC) are obtained. In addition, the temperature rise of the samples under SPWM, sinusoidal excitation are analyzed and compared.

Simplified SVPWM that Integrates Overmodulation and Neutral Point Potential Control

A simplified and effective space vector pulse-width modulation (SVPWM) algorithm with two and three levels for three-phase voltage-source converters is proposed in this study. The proposed SVPWM algorithm only uses several linear calculations on three-phase modulated voltages without any complicated trigonometric calculations adopted by conventional SVPWM. This simplified SVPWM also avoids choosing the vector sector required by conventional SVPWM. A two-level overmodulation scheme is integrated into the proposed two-level SVPMW to generate the output voltage that increases from a linear region to a six-step state with a smoothly linear transition characteristic and a simple overmodulation process without a lookup table and complicated nonlinear functions. The three-level SVPWM with a proportional-integral controller effectively balances the neutral point potential of the neutral point clamped converter. Results from the simulation in MATLAB/Simulink and the experiment based on a digital signal processor are provided to clearly demonstrate the validity and effectiveness of the proposed strategies.

The elimination of leakage currents in the neutral point clamped photovoltaic grid-connected inverter by the improved space vector pulse width modulation method

In this paper, the reason of high-frequency leakage current in neutral point clamped photovoltaic grid-connected inverters that adopts traditional modulations is analysed. In order to solve the problem, this article puts forward two improved methods based on the three-level space vector pulse width modulation (SVPWM), which can reduce the leakage current by applying three medium vectors or using only two medium vectors and one specific zero vector to compose the reference vector. In addition, the system control method adopts the coordination control of the current inner loop and the DC voltage outer loop, which can reduce voltage fluctuation at the DC side. Thereby, the suppression of leakage current can be realised without requiring any modification on the multilevel inverter. Compared with the traditional three-level sinusoidal pulse width modulation (SPWM) and SVPWM, the two new methods are advantageous in having a stable common-mode voltage, low leakage current, and low harmonic component of grid current. The theoretical analysis and results show the effectiveness of the proposed methods.

A Vector Space Decomposition Based Space Vector PWM Algorithm for a Three-Level Seven-Phase Voltage Source Inverter

This paper presents a novel modulation strategy for a seven-phase three-level inverter, aimed at variable-speed drive applications. Developed space vector pulsewidth modulation (SVPWM) strategy is based on vector space decomposition (VSD) approach and an analysis of multidimensional space vector projections in mutually orthogonal planes. The algorithm represents an extension of a recently developed five-phase three-level SVPWM algorithm and is considerably more complex, due to the existence of three mutually orthogonal planes in a seven-phase system. The difficulties of generalization of space vector strategies, which stem from the nature of the multiphase systems, are highlighted. Increasing the number of phases from five to seven increases the number of switching states from 35 = 243 to 37 = 2187 and the number of orthogonal planes from two to three. This considerably affects the complexity of the offline calculations. However, the final implementation of the algorithm is simple. Developed SVPWM algorithm is compared to an equivalent carrier-based strategy and it is shown that they yield identical performance. The complexity of the algorithms for real-time implementation is compared. Simulation and experimental results, obtained using neutral-point clamped inverter, verify the theoretical developments.

Synchronized SVPWM Algorithm for the Overmodulation Region of a Low Switching Frequency Medium-Voltage Three-Level VSI

In high-power applications, the output voltage of a voltage source inverter (VSI) must be synchronized with its fundamental component in order to eliminate subharmonics. With proper selection of switching states, it is possible to obtain synchronization and symmetry in the space vector pulse width modulation (SVPWM) algorithm. This paper presents an improved three-level SVPWM algorithm for the overmodulation region, which guarantees synchronization, half-wave symmetry, quarter-wave symmetry, and three-phase symmetry for all integer values of the pulse number. The proposed synchronized SVPWM algorithm is experimentally verified. The performance of the proposed algorithm is compared with other conventional algorithms. The comparative results prove that the consideration of synchronization and various symmetry results in better performance of the VSI.

Design and Implementation of Three-Level Space Vector PWM IP Core for FPGAs

This paper presents a novel circuit realization of the three-level space-vector pulse-width modulation (SVPWM) strategy. A simplified algorithm for the three-level SVPWM is proposed. Due to the geometrical symmetry of six sectors, there exist the close relationships in on time calculations and on time arrangement for switches between them. So it can complete the computation of the three-level SVPWM in one sector. Consequently, compared with the conventional algorithm, the proposed algorithm is more suitable to hardware implementation by greatly reducing computation amount. Based on the simplified algorithm, a three-level SVPWM intellectual property (IP) core has been developed using hardware description language (HDL). The designed IP core can serve as a coprocessor to relieve the DSP or MCU from the intensive computation task of the three-level SVPWM. Simulation and experimental results are given to verify the IP core in a field programmable gate array (FPGA).

Three-level space vector PWM in low index modulation region avoiding narrow pulse problem

In using GTO, a few hundreds micro seconds longer than specified pulse width must be guaranteed for safety for each device to commutate with its inherent gate current sequences. This paper describes the mechanism of generating undesirable narrow pulses in conventional three-level space vector PWM inverters and suggests two new algorithms of space vector PWM using nonnearest three and four vectors in a control period to avoid such a narrow pulse problem. Experimental verifications for the suggested algorithms are also presented. >