Three-dimensional Integration Research Articles

Van der Waals polarity-engineered 3D integration of 2D complementary logic

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1–3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6–8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9–17) and MoS2 (refs. 11,18–28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V−1 s−1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

Monolithic three-dimensional tier-by-tier integration via van der Waals lamination.

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

TEFLON: Thermally Efficient Dataflow-Aware 3D NoC for Accelerating CNN Inferencing on Manycore PIM Architectures

Resistive random-access memory (ReRAM) based processing-in-memory (PIM) architectures are used extensively to accelerate inferencing/training with convolutional neural networks (CNNs). Three-dimensional (3D) integration is an enabling technology to integrate many PIM cores on a single chip. In this work, we propose the design of a thermally efficient dataflow-aware monolithic 3D (M3D) NoC architecture referred to as TEFLON to accelerate CNN inferencing without creating any thermal bottlenecks. TEFLON reduces the Energy-Delay-Product (EDP) by 4 2\% , 46\% , and 45 \% on an average compared to a conventional 3D mesh NoC for systems with 36-, 64-, and 100-PIM cores respectively. TEFLON reduces the peak chip temperature by 25 K and improves the inference accuracy by up to 11 \% compared to sole performance-optimized SFC-based counterpart for inferencing with diverse deep CNN models using CIFAR-10/100 datasets on a 3D system with 100-PIM cores.

Three-Dimensional Electrode Integration With Microwave Sensors for Precise Microparticle Detection in Microfluidics

Three-Dimensional Electrode Integration With Microwave Sensors for Precise Microparticle Detection in Microfluidics

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Germanium (Ge) has high mobility and is more suitable for low-temperature device processes than silicon (Si); thus, it has attracted attention as an upper-layer transistor for monolithic three-dimensional (M3D) integration. We evaluated in detail the crystalline quality of extremely thin polycrystalline-Ge (poly-Ge) thin films thinner than 15 nm fabricated by metal-induced crystallization using copper (Cu-MIC) at 400 °C using micro-Raman scattering, in-plane X-ray diffraction, transmission electron microscopy (TEM), TEM energy dispersive X-ray spectroscopy, and TEM electron diffraction. Additionally, the films were applied to p-ch double-gate (DG) poly-Ge thin-film transistors (TFTs), and their performance was evaluated. As a result, a high I on/I off ratio of 2.8 × 103 was realized by crystallization at 400 °C with a ratio equal to that of crystallization at 500 °C. This study demonstrated the feasibility of Cu-MIC DG poly-Ge TFTs for M3D applications.

Exploration of the “Three-dimensional Integration” Ideo-political Education System in MBA “Management Communication” Course

This paper focuses on the significance of curriculum-based ideological and political education (curriculum Ideo-politics) and explores its implementation within MBA education to achieve an organic integration of knowledge impartation, value shaping, and skill development. By analyzing the current teaching situation and challenges of the "Management Communication" course, this paper proposes a novel curriculum reform plan: a three-dimensional integration model centered on professional education, guided by curriculum Ideo-politics, and expanded through practical education. This plan encompasses the types and core content of course construction, principles of reform, mechanisms of three-dimensional integration, and system building, offering specific measures to ensure the effective implementation of the reform plan. Aimed at providing a new perspective and method for the deep integration of professional courses and Ideo-political education in higher education, this study seeks to promote the innovative development of management education and cultivate high-quality management talents who can meet the needs of societal development.

Impact of Hydrogen Voiding in Chip-to-Chip Electroless All-Copper Interconnections.

Three-dimensional (3D) integration has become a leading approach in chip packaging. The interconnection density and reliability of micro-bumps in chip stacking are often threatened by high bonding temperatures. The method of building chip-to-chip interconnections by electroless deposition of metal has its distinct merit, while the interfacial defect issue, especially that related to voiding during the merging of opposite sides, remains largely unsolved. In this study, to trace the influencing factors in the voiding, the growth characteristics of the electroless all-copper interconnections were examined by carrying out deposition experiments in a microfluidic channel device. The results show that when the gap between the opposite copper bumps to be electrolessly merged is as low as 10 μm, significant voids appear at the inflow side and the top of the copper bumps because the hydrogen cannot be expelled in time. A finite-element flow model of the plating solution between the chips was established, which showed that the flow rate of the plating solution around the copper bumps was much higher than in the merging gap, causing an uneven supply of reactants. Based on these findings, we proposed two potential solutions, one is to improve the flow mode of the plating solution, and the other is to add the reaction inhibitor, 2,2'-bipyridine. Finally, the combination of these two approaches successfully achieved an improved merging quality of the copper joints.

Atomic Layer Deposition of WO3-Doped In2O3 for Reliable and Scalable BEOL-Compatible Transistors.

Tungsten oxide (WO3) doped indium oxide (IWO) field-effect transistors (FET), synthesized using atomic layer deposition (ALD) for three-dimensional integration and back-end-of-line (BEOL) compatibility, are demonstrated. Low-concentration (1∼4 W atom %) WO3-doping in In2O3 films is achieved by adjusting cycle ratios of the indium and tungsten precursors with the oxidant coreactant. Such doping suppresses oxygen deficiency from In2O2.5 to In2O3 stoichiometry with only 1 atom % W, allowing devices to turn off stably and enhancing threshold voltage stability. The ALD IWO FETs exhibit superior performance, including a low subthreshold slope of 67 mV/decade and negligible hysteresis. Strong tunability of the threshold voltage (Vth) is achieved through W concentration tuning, with 2 atom % IWO FETs showing an optimized Vth for enhancement-mode and a high drain current. ALD IWO FETs have remarkable stability under bias stress and nearly ideal performance extending to sub-100 nm channel lengths, making them promising candidates for high-performance monolithic 3D integrated devices.

Sub-5 nm Ultrathin In2O3 Transistors for High-Performance and Low-Power Electronic Applications.

Ultrathin oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, ultrathin indium oxide (In2O3) field-effect transistors (FETs) with thicknesses down to 0.4 nm exhibit an extremely high drain current (104 μA/μm) and transconductance (4000 μS/μm). Here, we employ ab initio quantum transport simulation to investigate the performance limit of sub-5 nm gate length (Lg) ultrathin In2O3 FETs. Based on the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, the scaling limit of ultrathin In2O3 FETs can reach 2 nm in terms of on-state current, delay time, and power dissipation. The wide bandgap nature of ultrathin In2O3 (3.0 eV) renders it a suitable candidate for ITRS low-power (LP) electronics with Lg down to 3 nm. Notably, both the HP and LP ultrathin In2O3 FETs exhibit superior energy-delay products as compared to those of other common 2D semiconductors such as monolayer MoS2 and MoTe2. These findings unveil the potential of ultrathin In2O3 in HP and LP nanoelectronic device applications.

Plasma activated titanium-based bonding for robust and reliable Si–Si and Si-glass integration

The exceptional biocompatibility of Ti/Ti bonding technology makes it highly significant for the sealing of implantable devices. However, achieving highly reliable Ti/Ti bonding at low temperatures is challenging due to the facile formation of a native oxide film, which hinders the diffusion of interfacial atoms. This paper develops a low-temperature Ti/Ti bonding process based on plasma activation, resulting in a remarkable bonding strength of 17.5 MPa at 300 °C, which can be used for Si–Si homogeneous and Si-glass heterogeneous integration. After optimizing the processes, the surface oxides of Ti can be partially reduced through Ar/H2 plasma activation to form unsaturated chemical bonds, thereby overcoming the limitation of film thickness in Ti/Ti bonding. The results indicate that plasma activation can realize high strength Ti/Ti bonding in the film thickness range of 10–50 nm. It is worth noting that the Ti/Ti bonding area and strength remain stable after immersion experiments in DI water and normal saline for 7 days, which proves that Ti/Ti bonding has good corrosion resistance. In addition, the microcavity structures were prepared using photolithography and etching techniques. The Ti/Ti bonding technology enables direct bonding of microcavity structures with plate Ti, and an intact bonding interface near the microcavity was obtained. This low-temperature Ti/Ti bonding technology is suitable for the three-dimensional integration of various substrate materials, and its excellent corrosion resistance makes it promising for application in the sealing of BioMEMS.

Nonvolatile memory operations using intersubband transitions in GaN/AlN resonant tunneling diodes grown on Si(111) substrates

Nonvolatile memory using intersubband transitions and quantum-well electron accumulation in GaN/AlN resonant tunneling diodes (RTDs) is a promising candidate for high-speed nonvolatile memory operating on a picosecond timescale. This memory has been fabricated on sapphire(0001) substrates to date because of the high affinity between the nitride materials and the substrate. However, the fabrication of this memory on Si(111) substrates is attractive to realize hybrid integration with Si devices and nonvolatile memory and three-dimensional integration such as chip-on-wafer and wafer-on-wafer. In this study, GaN/AlN RTDs are fabricated on a Si(111) substrate using metal-organic vapor phase epitaxy. The large strain caused by the differences in the thermal expansion coefficients and lattice constants between the Si(111) substrate and nitride materials are suppressed by a growth technique based on the insertion of low-temperature-grown AlGaN and thin AlN layers. The GaN/AlN RTDs fabricated on Si(111) substrates show clear GaN/AlN heterointerfaces and a high ON/OFF ratio of >220, which are equivalent to those for devices fabricated on sapphire(0001) substrates. However, the nonvolatile memory characteristics fluctuate by repeated write/erase memory operations. Evaluation of the ON/OFF switching time and endurance characteristics indicates that the instability of the nonvolatile memory characteristics is caused by electron leakage through deep levels in the quantum-well structure. Possible methods for suppressing this are discussed with an aim of realizing high-speed and high-endurance nonvolatile memory.

High-performance, power-efficient three-dimensional system-in-package designs with universal chiplet interconnect express

Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0 specification defines interoperability using standard and advanced packaging technologies with planar interconnects. Here we examine the development of UCIe as the bump interconnect pitches reduce with advances in packaging technologies for three-dimensional integration of chiplets. We report a die-to-die solution for the continuum of package bump pitches down to 1 µm, providing circuit architecture details and performance results. Our analysis suggests that—contrary to trends seen in traditional signalling interfaces—the most power-efficient performance for these architectures can be achieved by reducing the frequency as the bump pitch goes down. Our architectural approach provides power, performance and reliability characteristics approaching or exceeding that of a monolithic system-on-chip design as the bump pitch approaches 1 µm.

Anti-friction gold-based stretchable electronics enabled by interfacial diffusion-induced cohesion

Stretchable electronics that prevalently adopt chemically inert metals as sensing layers and interconnect wires have enabled high-fidelity signal acquisition for on-skin applications. However, the weak interfacial interaction between inert metals and elastomers limit the tolerance of the device to external friction interferences. Here, we report an interfacial diffusion-induced cohesion strategy that utilizes hydrophilic polyurethane to wet gold (Au) grains and render them wrapped by strong hydrogen bonding, resulting in a high interfacial binding strength of 1017.6 N/m. By further constructing a nanoscale rough configuration of the polyurethane (RPU), the binding strength of Au-RPU device increases to 1243.4 N/m, which is 100 and 4 times higher than that of conventional polydimethylsiloxane and styrene-ethylene-butylene-styrene-based devices, respectively. The stretchable Au-RPU device can remain good electrical conductivity after 1022 frictions at 130 kPa pressure, and reliably record high-fidelity electrophysiological signals. Furthermore, an anti-friction pressure sensor array is constructed based on Au-RPU interconnect wires, demonstrating a superior mechanical durability for concentrated large pressure acquisition. This chemical modification-free approach of interfacial strengthening for chemically inert metal-based stretchable electronics is promising for three-dimensional integration and on-chip interconnection.

The Electronics Resurgence Initiative 2.0 for U.S. Semiconductor Manufacturing

Abstract The second Electronics Resurgence Initiative (ERI 2.0), sponsored by the U.S. Defense Advanced Research Project Agency (DARPA) Microsystems Technology Office (MTO), is focused on driving next generation dual use microelectronics for national security and domestic needs. The initiative focuses on creating U.S. capability for three-dimensional heterogeneous integration (3DHI) manufacturing and pursuing focused research for the manufacture of complex 3D microsystems. This guest editorial describes the outcomes from a three-day summit (Seattle, Washington, August 2023) where the initiative was launched.

Fabrication of high aspect ratio, non-line-of-sight vias in silicon carbide by a two-photon absorption method

The future of Moore’s Law for high-performance integrated circuits (ICs) is going to be driven more by advanced packaging and three-dimensional (3D) integration than by simply decreasing transistor size. 3D ICs offer low-power consumption, high-performance and a smaller footprint compared to conventional 2D ICs. The key enabling technology to 3D integration is the interposer that provides interconnects to route signals between the chiplets that comprise the IC. However, the fabrication of high-aspect ratio through wafer vias (TWVs), that provide electrical and mechanical connection between chiplets on the top and bottom of the interposer, is one of the important challenges that limit interposer performance. Current fabrication technologies are limited by tapering effects and the need for direct line of sight to the fabrication surface. These limit the possible aspect ratios of vias and require large, complicated surface traces to connect the vias to the chiplets. Here, we demonstrate the fabrication of high-aspect ratio, non-line-of-sight TWVs in silicon carbide (SiC). SiC provides better mechanical, chemical, and thermal performance than silicon (Si). The technique uses an electro-chemical etch process that utilizes two-photon absorption to create any arbitrary 3D structure in SiC allowing for direct, subsurface routing between chiplets.

Linked data to streaming data sensors sources for direct access

Goal: Industrial operations are complex, and data sensors assure safety and reliable information for production improvements. Multiple stakeholders can take advantage of data acquisition for post-analysis and process control. Providing users and systems with friendly access to operating data is fundamental to the digital transition in the industry 4.0 scenario. Linking data and systems over ontologies and Industry Foundation Classes will boost supply chain performance in many layers. This paper presents the concept of valid data points over Uniform Resource Identifiers for sensor time-series into triples stores via Application Programming Interfaces. Design/Methodology/Approach: A streaming data source approach to integrating industrial sensor data and sharing it via Uniform Resource Identifiers is developed and tested using Node-Red with multiple data connection types, such as the Industry Foundation Classes and open-source time series databases. Results: The detailed proof of concept presented valid the feasibility of sharing sensor data via Uniform Resource Identifiers. The findings provide a backbone of a system able to interop Message Queuing Telemetry Transport data, Resource Description Framework datasets and Industry Foundation Classes schema. Limitations of the investigation: The system envisaged was tested using simulated data. However, it is expected to have similar results from real data use. Nevertheless, more research will be needed to implement more features, such as three-dimensional object integration. Practical implications: The solution designed and tested presented can be used in practice for companies that desire to expand via linked data shareability and interoperability. Also, researchers can advance the solution for specific features, such as creating an open-source data query and manipulation language. Originality/Value: This paper examines future deployments of systems-to-systems interoperability targeting user-friendly data shareability. It is meant to be useful for industrial and academic developments.

Quantum Conductance in Vertical Hexagonal Boron Nitride Memristors with Graphene-Edge Contacts.

Two-dimensional materials (2DMs) have gained significant interest for resistive-switching memory toward neuromorphic and in-memory computing (IMC). To achieve atomic-level miniaturization, we introduce vertical hexagonal boron nitride (h-BN) memristors with graphene edge contacts. In addition to enabling three-dimensional (3D) integration (i.e., vertical stacking) for ultimate scalability, the proposed structure delivers ultralow power by isolating single conductive nanofilaments (CNFs) in ultrasmall active areas with negligible leakage thanks to atomically thin (∼0.3 nm) graphene edge contacts. Moreover, it facilitates studying fundamental resistive-switching behavior of single CNFs in CVD-grown 2DMs that was previously unattainable with planar devices. This way, we studied their programming characteristics and observed a consistent single quantum step in conductance attributed to unique atomically constrained nanofilament behavior in CVD-grown 2DMs. This resistive-switching property was previously suggested for h-BN memristors and linked to potential improvements in stability (robustness of CNFs), and now we show experimental evidence including superior retention of quantized conductance.

Improved parameter targeting in 3D-integrated superconducting circuits through a polymer spacer process

Three-dimensional device integration facilitates the construction of superconducting quantum information processors with more than several tens of qubits by distributing elements such as control wires, qubits, and resonators between multiple layers. The frequencies of resonators and qubits in flip-chip-bonded multi-chip modules depend on the details of their electromagnetic environment defined by the conductors and dielectrics in their vicinity. Accurate frequency targeting therefore requires precise control of the separation between chips and minimization of their relative tilt. Here, we describe a method to control the inter-chip separation by using polymer spacers. With the spacers, we measure a mean tilt of (76 ± 36) μrad, and a mean deviation of (0.4 ± 0.8) μm from the target inter-chip separation of 10 μm. We apply this process to coplanar waveguide resonator samples and observe chip-to-chip resonator frequency variations below 50 MHz (≈1%\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$\\approx 1\\%$\\end{document}). We measure internal quality factors of 5×105\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$5\ imes10^{5}$\\end{document} at the single-photon level, suggesting that the added spacers are compatible with low-loss device fabrication.

Three-dimensional integration of two-dimensional field-effect transistors.

In the field of semiconductors, three-dimensional (3D) integration not only enables packaging of more devices per unit area, referred to as 'More Moore'1 but also introduces multifunctionalities for 'More than Moore'2 technologies. Although silicon-based 3D integrated circuits are commercially available3-5, there is limited effort on 3D integration of emerging nanomaterials6,7 such as two-dimensional (2D) materials despite their unique functionalities7-10. Here we demonstrate (1) wafer-scale and monolithic two-tier 3D integration based on MoS2 with more than 10,000 field-effect transistors (FETs) in each tier; (2) three-tier 3D integration based on both MoS2 and WSe2 with about 500 FETs in each tier; and (3) two-tier 3D integration based on 200 scaled MoS2 FETs (channel length, LCH = 45 nm) in each tier. We also realize a 3D circuit and demonstrate multifunctional capabilities, including sensing and storage. We believe that our demonstrations will serve as the foundation for more sophisticated, highly dense and functionally divergent integrated circuits with a larger number of tiers integrated monolithically in the third dimension.

An analysis of the three-dimensional integration of intangible cultural heritage into ideological and political education in colleges and universities

An analysis of the three-dimensional integration of intangible cultural heritage into ideological and political education in colleges and universities