Three-dimensional Integration Research Articles

Interface modeling analysis using density functional theory in highly reliable Pt/HfO2/TaOx/Ta self-rectifying memristor

The self-rectifying memristor (SRM) is a promising device prototype for high-density three-dimensional (3D) integration and high-efficiency in-memory computing (IMC) by virtue of its ability to effectively suppress sneak current, simple device structure, and low energy consumption. Theoretically understanding the intrinsic mechanisms of SRM is a matter of concern. Here, we fabricated a Ta/TaOx/HfO2/Pt-stacked SRM exhibiting >103 on/off ratio, rectification ratio, and nonlinearity. The SRM can be repeatedly programmed by more than 106 pulses and demonstrates robust retention and high scalability (∼59 Mbit). A reasonable interface model for this SRM is established based on first-principles calculations. Using self-energy corrected density function theory, we calculate the barrier heights at each interface. Detailed I–V curve fitting and energy band analysis are performed and computationally verified to explain the intrinsic reasons for resistive switching, self-rectifying, and nonlinear behaviors. The work may advance the development of SRM prototype to enable energy-efficient 3D IMC.

High-performance single-crystalline In2O3 field effect transistor toward three-dimensional large-scale integration circuits

Formation of a single crystalline oxide semiconductor on an insulating film as a channel material capable of three-dimensional (3D) stacking would enable 3D very-large-scale integration circuits. This study presents a technique for forming single-crystalline In2O3 having no grain boundaries in a channel formation region on an insulating film using the (001) plane of c-axis-aligned crystalline indium gallium zinc oxide as a seed. Vertical field-effect transistors using the single-crystalline In2O3 had an off-state current of 10−21 A μm−1 and electrical characteristics were improved compared with those using non-single-crystalline In2O3: the subthreshold slope was improved from 95.7 to 86.7 mV dec.−1, the threshold voltage showing normally-off characteristics (0.10 V) was obtained, the threshold voltage standard deviation was improved from 0.11 to 0.05 V, the on-state current was improved from 22.5 to 28.8 μA, and a 17-digit on/off ratio was obtained at 27 °C.

Hierarchical magneto-colorimetric labels for immediate lateral flow immunoassay of chlorothalonil residues

Quantitative detection of pesticide residues in food and environmental samples using an improved lateral flow immunoassay (LFIA) is of considerable importance for real-time analysis. This paper proposes a highly sensitive LFIA platform based on a hierarchical magneto-colorimetric compact. This compact serves as both the target magnetic enrichment substrate and a photosensitive label. Initially, a large porous dendritic silica template is prepared and doped with superparamagnetic ferric oxide nanoparticles (Fe3O4 NPs) and colloidal gold nanoparticles (AuNPs) at high densities within its vertical channels. The sequential assembly of central–radial channels allow for the three-dimensional integration of these two components, enabling independent control of their discrete functions without mutual interference. Following alkyl organosilicon encapsulation and silica sealing, the composite spheres are then applied in LFIA to detect chlorothalonil residues. Fe3O4 NPs enhance the binding efficiency to target analytes, while AuNPs amplify the signal, leveraging their high loading densities and robust optical properties. The developed LFIA platform exhibited a detection limit of 0.34 ng/mL for chlorothalonil and a linear range of 0.0085–824 ng/mL. The recoveries varied between 85.1 % and 103.1 %, and the relative standard deviations were 1.25%–8.84 %. This LFIA approach demonstrates high sensitivity, specificity, reproducibility and flexible detection modes, making it highly suitable for the on-site monitoring of pesticide residues.

TEFLON: Thermally Efficient Dataflow-aware 3D NoC for Accelerating CNN Inferencing on Manycore PIM Architectures

Resistive random-access memory (ReRAM)-based processing-in-memory (PIM) architectures are used extensively to accelerate inferencing/training with convolutional neural networks (CNNs). Three-dimensional (3D) integration is an enabling technology to integrate many PIM cores on a single chip. In this work, we propose the design of a t hermally e fficient data flo w-aware monolithic 3D (M3D) N oC architecture referred to as TEFLON to accelerate CNN inferencing without creating any thermal bottlenecks. TEFLON reduces the Energy-Delay-Product (EDP) by 42%, 46%, and 45% on an average compared to a conventional 3D mesh NoC for systems with 36-, 64-, and 100-PIM cores, respectively. TEFLON reduces the peak chip temperature by 25 K and improves the inference accuracy by up to 11% compared to sole performance-optimized SFC-based counterpart for inferencing with diverse deep CNN models using CIFAR-10/100 datasets on a 3D system with 100-PIM cores.

Nitrogen: A promising doping strategy for high-performance ovonic threshold switching selectors

The Ovonic Threshold Switching (OTS) selector serves as an essential component in the development of three-dimensional high-density memory integration technology. Nevertheless, the state-of-the-art high-performance OTS materials usually contain toxic elements such as arsenic (As), posing significant risks to both environmental and human health. Nitrogen (N), which belongs to the same group as arsenic (As), has emerged as a highly promising alternative for As doping. However, the underlying mechanisms that govern N-based OTS materials have not yet been extensively investigated. In this study, we delve into the effects of N doping on the structural, bonding, and electronic properties of amorphous GeSe (a-GeNSe) by ab initio molecular dynamics simulations to bridge the knowledge gap. Our findings indicate that upon N doping in a-GeSe, the formation of robust Ge-N bonds, along with N-centered tetrahedral and triangular structures, resulting in the sluggish atomic movement that enhances the thermal stability and endurance of a-GeNSe. The OTS characteristics are significantly influenced by the material’s electronic band structure, and thus the relatively slow performance drift can be attributed to the stabilization of mid-gap states, a result of N doping which effectively slows down the aging process of chalcogenide glass. Moreover, the increased mobility gap in a-GeNSe raises the threshold voltage (Vth), making it more compatible with commercially available phase-change memory materials. Our findings reveal the extensive impact of the N element on a typical OTS material and offer valuable perspectives for alternative doping strategies that could potentially supplant As practices.

Multilayer stacked crystalline silicon switch with nanosecond-order switching time.

To realize compact and denser photonic integrated circuits, three-dimensional integration has been widely accepted and researched. In this article, we demonstrate the operation of a 3D integrated silicon photonic platform fabricated through wafer bonding. Benefiting from the wafer bonding process, the material of all layers is c-Si, which ensures that the mobility is high enough to achieve a nanosecond response via the p-i-n diode shifter. Optical components, including multimode interferences (MMIs), waveguide crossing, and Mach-Zehnder interferometer (MZI)-based switch, are fabricated in different layers and exhibit great performance. The interlayer coupler and crossing achieve a 0.98 dB coupling loss and <-43.58 dB cross talk, while the crossing fabricated in the same layer shows <-36.00 dB cross talk. A nanosecond-order switch response is measured in different layers.

A Cost-Driven Chip Partitioning Method for Heterogeneous 3D Integration

Three-dimensional integration circuit (3D IC) offers significant benefits in terms of performance and cost. Existing research in through-silicon via (TSV)-based 3D IC partitioning has focused on minimizing the number of TSVs to reduce costs. Partitioning methods based on heterogeneous integration have emerged as viable approaches for cost optimization. Leveraging mature processes to manufacture not timing-critical blocks can yield cost benefits. Nevertheless, none of the previous 3D partitioning work has focused on reducing the overall cost, including both design and manufacturing costs, for heterogeneous 3D integration. Moreover, throughput constraints have not been considered. This article presents a cost-aware integer linear programming-based formulation and a heuristic algorithm that partition the functional blocks in the design into different technological groups. Each group of functional blocks will be implemented using a particular process technology, and then integrated into a 3D IC. Our results show that 3D heterogeneous integration chip implementation can reduce overall cost while satisfying various timing constraints.

Three-dimensional integrated metal-oxide transistors

AbstractThe monolithic three-dimensional vertical integration of thin-film transistor (TFT) technologies could be used to create high-density, energy-efficient and low-cost integrated circuits. However, the development of scalable processes for integrating three-dimensional TFT devices is challenging. Here, we report the monolithic three-dimensional integration of indium oxide (In2O3) TFTs on a silicon/silicon dioxide (Si/SiO2) substrate at room temperature. We use an approach that is compatible with complementary metal–oxide–semiconductor (CMOS) processes to stack ten n-channel In2O3 TFTs. Different architectures—including bottom-, top- and dual-gate TFTs—can be fabricated at different layers in the stack. Our dual-gate devices exhibit enhanced electrical performance with a maximum field-effect mobility of 15 cm2 V−1 s−1, a subthreshold swing of 0.4 V dec−1 and a current on/off ratio of 108. By monolithically integrating dual-gate In2O3 TFTs at different locations in the stack, we created unipolar invertor circuits with a signal gain of around 50 and wide noise margins. The dual-gate devices also allow fine-tuning of the invertors to achieve symmetric voltage-transfer characteristics and optimal noise margins.

Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors.

The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.

The future of two-dimensional semiconductors beyond Moore's law.

The primary challenge facing silicon-based electronics, crucial for modern technological progress, is difficulty in dimensional scaling. This stems from a severe deterioration of transistor performance due to carrier scattering when silicon thickness is reduced below a few nanometres. Atomically thin two-dimensional (2D) semiconductors still maintain their electrical characteristics even at sub-nanometre scales and offer the potential for monolithic three-dimensional (3D) integration. Here we explore a strategic shift aimed at addressing the scaling bottleneck of silicon by adopting 2D semiconductors as new channel materials. Examining both academic and industrial viewpoints, we delve into the latest trends in channel materials, the integration of metal contacts and gate dielectrics, and offer insights into the emerging landscape of industrializing 2D semiconductor-based transistors for monolithic 3D integration.

Performance improvement of HfO2-based ferroelectric with 3D cylindrical capacitor stress optimization

To meet commercialization requirements, the distributions of materials in hafnium-based ferroelectric devices—including their phase and orientation—need to be controlled. This article presents a method for improving the ferroelectric phase ratio and orientation by adjusting the stress distribution of the annealing structure in a three-dimensional capacitor. In such a structure, stress can be applied in three directions: tangential, axial, and radial; there are, thus, more ways to regulate stress in three-dimensional structures than in two-dimensional structures. This work sought to clarify the role of the stress direction on the proportions and orientations of ferroelectric phases. The results of stress simulations show that a structure with an internal TiN electrode, but no filling provides greater axial and tangential stresses in the hafnium-oxide layer. In comparison with the case of the hole being filled with tungsten, the proportion of the O phase is increased by approximately 20%, and in experiments, the projection of the polarization direction onto the normal was found to be increased by 5%. Axial and tangential stresses are regarded to be beneficial for the formation of the O phase and for improving the orientation of the polarization direction. This work provides a theoretical basis and guidance for the three-dimensional integration of hafnium-based ferroelectric materials.

Bioinspired low temperature Cu bonding interfaces with interlocked microstructures to achieve high reliability

The reliability of Cu bonding technology in three-dimensional integration packaging is limited by high sintering temperatures and the growth of oxide at the joining interface. Hence, we propose a bionic adhesion interface of creeper sucker on the Cu substrate and covered with monolayer graphene, which increases the shear strength by 3 times compared to the conventional flat Cu substrate. The covered graphene layer effectively inhibits the generation of oxide at the joint interface and maintains a high shear strength after aging at 300 °C for 48 h Nanoscale Cu particles could reduce the chemical potential energy of the substrate surface, and stable bonding was achieved at 200 °C under a pressure of 2 MPa. Molecular dynamics simulation models reveal crystal structure evolution and residual stresses during the sintering process. This work demonstrates that bionic microstructures applied to copper bonding play an important role in interface enhancement, resulting in reliable bonding of Cu substrate at low temperatures. The method proposed here can provide insight into diversified applications including high-power light-emitting diodes soldering, SiC electronic devices, and flexible electrode interconnects.

Van der Waals polarity-engineered 3D integration of 2D complementary logic

Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great promise, as it offers the possibility to scale up logic layers in the z axis1–3. Indeed, vertical complementary field-effect transistors (CFETs) built with such mixed-dimensional heterostructures4,5, as well as hetero-2D layers with different carrier types6–8, have been demonstrated recently. However, so far, the lack of a controllable doping scheme (especially p-doped WSe2 (refs. 9–17) and MoS2 (refs. 11,18–28)) in 2D semiconductors, preferably in a stable and non-destructive manner, has greatly impeded the bottom-up scaling of complementary logic circuitries. Here we show that, by bringing transition metal dichalcogenides, such as MoS2, atop a van der Waals (vdW) antiferromagnetic insulator chromium oxychloride (CrOCl), the carrier polarity in MoS2 can be readily reconfigured from n- to p-type via strong vdW interfacial coupling. The consequential band alignment yields transistors with room-temperature hole mobilities up to approximately 425 cm2 V−1 s−1, on/off ratios reaching 106 and air-stable performance for over one year. Based on this approach, vertically constructed complementary logic, including inverters with 6 vdW layers, NANDs with 14 vdW layers and SRAMs with 14 vdW layers, are further demonstrated. Our findings of polarity-engineered p- and n-type 2D semiconductor channels with and without vdW intercalation are robust and universal to various materials and thus may throw light on future three-dimensional vertically integrated circuits based on 2D logic gates.

Monolithic three-dimensional tier-by-tier integration via van der Waals lamination.

Two-dimensional (2D) semiconductors have shown great potential for monolithic three-dimensional (M3D) integration due to their dangling-bonds-free surface and the ability to integrate to various substrates without the conventional constraint of lattice matching1-10. However, with atomically thin body thickness, 2D semiconductors are not compatible with various high-energy processes in microelectronics11-13, where the M3D integration of multiple 2D circuit tiers is challenging. Here we report an alternative low-temperature M3D integration approach by van der Waals (vdW) lamination of entire prefabricated circuit tiers, where the processing temperature is controlled to 120 °C. By further repeating the vdW lamination process tier by tier, an M3D integrated system is achieved with 10 circuit tiers in the vertical direction, overcoming previous thermal budget limitations. Detailed electrical characterization demonstrates the bottom 2D transistor is not impacted after repetitively laminating vdW circuit tiers on top. Furthermore, by vertically connecting devices within different tiers through vdW inter-tier vias, various logic and heterogeneous structures are realized with desired system functions. Our demonstration provides a low-temperature route towards fabricating M3D circuits with increased numbers of tiers.

Three-Dimensional Electrode Integration With Microwave Sensors for Precise Microparticle Detection in Microfluidics

Three-Dimensional Electrode Integration With Microwave Sensors for Precise Microparticle Detection in Microfluidics

Evaluation of extremely thin polycrystalline germanium films and their TFT performance fabricated at 400 °C by Cu-induced crystallization on a glass substrate

Germanium (Ge) has high mobility and is more suitable for low-temperature device processes than silicon (Si); thus, it has attracted attention as an upper-layer transistor for monolithic three-dimensional (M3D) integration. We evaluated in detail the crystalline quality of extremely thin polycrystalline-Ge (poly-Ge) thin films thinner than 15 nm fabricated by metal-induced crystallization using copper (Cu-MIC) at 400 °C using micro-Raman scattering, in-plane X-ray diffraction, transmission electron microscopy (TEM), TEM energy dispersive X-ray spectroscopy, and TEM electron diffraction. Additionally, the films were applied to p-ch double-gate (DG) poly-Ge thin-film transistors (TFTs), and their performance was evaluated. As a result, a high I on/I off ratio of 2.8 × 103 was realized by crystallization at 400 °C with a ratio equal to that of crystallization at 500 °C. This study demonstrated the feasibility of Cu-MIC DG poly-Ge TFTs for M3D applications.

Exploration of the “Three-dimensional Integration” Ideo-political Education System in MBA “Management Communication” Course

This paper focuses on the significance of curriculum-based ideological and political education (curriculum Ideo-politics) and explores its implementation within MBA education to achieve an organic integration of knowledge impartation, value shaping, and skill development. By analyzing the current teaching situation and challenges of the "Management Communication" course, this paper proposes a novel curriculum reform plan: a three-dimensional integration model centered on professional education, guided by curriculum Ideo-politics, and expanded through practical education. This plan encompasses the types and core content of course construction, principles of reform, mechanisms of three-dimensional integration, and system building, offering specific measures to ensure the effective implementation of the reform plan. Aimed at providing a new perspective and method for the deep integration of professional courses and Ideo-political education in higher education, this study seeks to promote the innovative development of management education and cultivate high-quality management talents who can meet the needs of societal development.

Impact of Hydrogen Voiding in Chip-to-Chip Electroless All-Copper Interconnections.

Three-dimensional (3D) integration has become a leading approach in chip packaging. The interconnection density and reliability of micro-bumps in chip stacking are often threatened by high bonding temperatures. The method of building chip-to-chip interconnections by electroless deposition of metal has its distinct merit, while the interfacial defect issue, especially that related to voiding during the merging of opposite sides, remains largely unsolved. In this study, to trace the influencing factors in the voiding, the growth characteristics of the electroless all-copper interconnections were examined by carrying out deposition experiments in a microfluidic channel device. The results show that when the gap between the opposite copper bumps to be electrolessly merged is as low as 10 μm, significant voids appear at the inflow side and the top of the copper bumps because the hydrogen cannot be expelled in time. A finite-element flow model of the plating solution between the chips was established, which showed that the flow rate of the plating solution around the copper bumps was much higher than in the merging gap, causing an uneven supply of reactants. Based on these findings, we proposed two potential solutions, one is to improve the flow mode of the plating solution, and the other is to add the reaction inhibitor, 2,2'-bipyridine. Finally, the combination of these two approaches successfully achieved an improved merging quality of the copper joints.

Atomic Layer Deposition of WO3-Doped In2O3 for Reliable and Scalable BEOL-Compatible Transistors.

Tungsten oxide (WO3) doped indium oxide (IWO) field-effect transistors (FET), synthesized using atomic layer deposition (ALD) for three-dimensional integration and back-end-of-line (BEOL) compatibility, are demonstrated. Low-concentration (1∼4 W atom %) WO3-doping in In2O3 films is achieved by adjusting cycle ratios of the indium and tungsten precursors with the oxidant coreactant. Such doping suppresses oxygen deficiency from In2O2.5 to In2O3 stoichiometry with only 1 atom % W, allowing devices to turn off stably and enhancing threshold voltage stability. The ALD IWO FETs exhibit superior performance, including a low subthreshold slope of 67 mV/decade and negligible hysteresis. Strong tunability of the threshold voltage (Vth) is achieved through W concentration tuning, with 2 atom % IWO FETs showing an optimized Vth for enhancement-mode and a high drain current. ALD IWO FETs have remarkable stability under bias stress and nearly ideal performance extending to sub-100 nm channel lengths, making them promising candidates for high-performance monolithic 3D integrated devices.

Sub-5 nm Ultrathin In2O3 Transistors for High-Performance and Low-Power Electronic Applications.

Ultrathin oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, ultrathin indium oxide (In2O3) field-effect transistors (FETs) with thicknesses down to 0.4 nm exhibit an extremely high drain current (104 μA/μm) and transconductance (4000 μS/μm). Here, we employ ab initio quantum transport simulation to investigate the performance limit of sub-5 nm gate length (Lg) ultrathin In2O3 FETs. Based on the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, the scaling limit of ultrathin In2O3 FETs can reach 2 nm in terms of on-state current, delay time, and power dissipation. The wide bandgap nature of ultrathin In2O3 (3.0 eV) renders it a suitable candidate for ITRS low-power (LP) electronics with Lg down to 3 nm. Notably, both the HP and LP ultrathin In2O3 FETs exhibit superior energy-delay products as compared to those of other common 2D semiconductors such as monolayer MoS2 and MoTe2. These findings unveil the potential of ultrathin In2O3 in HP and LP nanoelectronic device applications.