Three-dimensional Inductors Research Articles

Design of a Fully Integrated Inductive Coupling System: A Discrete Approach Towards Sensing Ventricular Pressure.

In this paper, an alternative strategy for the design of a bidirectional inductive power transfer (IPT) module, intended for the continuous monitoring of cardiac pressure, is presented. This new integrated implantable medical device (IMD) was designed including a precise ventricular pressure sensor, where the available implanting room is restricted to a 1.8 × 1.8 cm2 area. This work considers a robust magnetic coupling between an external reading coil and the implantable module: a three-dimensional inductor and a touch mode capacitive pressure sensor (TMCPS) set. In this approach, the coupling modules were modelled as RCL circuits tuned at a 13.56 MHz frequency. The analytical design was validated by means of Comsol Multiphysics, CoventorWare, and ANSYS HFSS software tools. A power transmission efficiency (PTE) of 94% was achieved through a 3.5 cm-thick biological tissue, based on high magnitudes for the inductance (L) and quality factor (Q) components. A specific absorption rate (SAR) of less than 1.6 W/Kg was attained, which suggests that this IPT system can be implemented in a safe way, according to IEEE C95.1 safety guidelines. The set of inductor and capacitor integrated arrays were designed over a very thin polyimide film, where the 3D coil was 18 mm in diameter and approximately 50% reduced in size, considering any conventional counterpart. Finally, this new approach for the IMD was under development using low-cost thin film manufacturing technologies for flexible electronics. Meanwhile, as an alternative test, this novel system was fabricated using a discrete printed circuit board (PCB) approach, where preliminary electromagnetic characterization demonstrates the viability of this bidirectional IPT design.

Injection‐locked frequency divider with a hybrid 3D multi‐path and single‐path inductor

This Letter proposes a divide-by-2 injection-locked frequency divider (ILFD) with a new passive resonator. The ILFD in the 0.18 μm 1P6M CMOS process uses a three-dimensional inductor consisted of three series single-path and multi-path inductors. Measured data shows that the varactor-less divide-by-2 ILFD has wide locking range, low power consumption and occupies a small area of 0.4446 × 0.9198 mm 2 .

Fabrication and Optimization of High Aspect Ratio Through-Silicon-Vias Electroplating for 3D Inductor.

In this study, the filling process of high aspect ratio through-silicon-vias (TSVs) under dense conditions using the electroplating method was efficiently achieved and optimized. Pulsed power was used as the experimental power source and the electroplating solution was prepared with various additive concentrations. Designed control variable experiments were conducted to determine the optimized method. In the control variable experiments, the relationship of multiple experimental variables, including current density (0.25–2 A/dm2), additive concentration (0.5–2 mL/L), and different shapes of TSVs (circle, oral, and square), were systematically analyzed. Considering the electroplating speed and quality, the influence of different factors on experimental results and the optimized parameters were determined. The results showed that increasing current density improved the electroplating speed but decreased the quality. Additives worked well, whereas their concentrations were controlled within a suitable range. The TSV shape also influenced the electroplating result. When the current density was 1.5 A/dm2 and the additive concentration was 1 mL/L, the TSV filling was relatively better. With the optimized parameters, 500-μm-deep TSVs with a high aspect ratio of 10:1 were fully filled in 20 h, and the via density reached 70/mm2. Finally, optimized parameters were adopted, and the electroplating of 1000-μm-deep TSVs with a diameter of 100 μm was completed in 45 h, which is the deepest and smallest through which a three-dimensional inductor has ever been successfully fabricated.

Multi‐layer on‐chip inductor for 10–100 GHz frequency applications

A multi-layer inductor is proposed to achieve high inductance with moderate Q-factor values. The development of integration of devices technology in radio-frequency (RF) has increased the importance of on-chip inductors. In the literature, the planar inductor, the three-dimensional (3D) inductor with constant width and the 3D inductor with variable width are reported. Using the basic concept of multi-layer technology in very large-scale integration (VLSI) system design and considering lambda rules, the proposed inductor is designed. The inductance of the proposed inductor is nearly 37–45% higher compared with reported inductors with a moderate quality factor. This inductor is realised using 180 nm scale technology with an area of cross-section 10 × 10 µm2. Results are presented using the IE3D EM field solver with the help of series RL and shunt RC lumped Pi model.

RF operation of MOSFETs under integrated inductors

This paper presents an in-depth analysis of the operation of a CMOS single-chip three-dimensional inductor over a MOSFET structure at RF frequencies. Active circuitry is placed underneath the integrated inductors in order to take advantage of the vacant space. Measurements indicate that the operation of the MOSFET and of the inductor is affected in a predictable manner. The paper theoretically investigates the interaction between the two elements,analyzes the origin of all appearing effects and compares the theory with the experimental data from a typical CMOS process. Moreover, this study proposes possible applications and design guides and confirms the attractiveness of the inductor over MOSFET placement.

Analytical GMD formulas for mutual inductance calculation of multilevel interconnects

A set of new analytical formulas is proposed for determining the geometric mean distance (GMD)for use in the Greenhouse method to calculate the inductances of three-dimensional inductors composed of on-chip interconnects. The expressions are derived using a graphical method based on the integral form of the GMD equation. The mutual inductances of coupled interconnects are computed for given layout geometries using the proposed formulas, even when the conductors are partially overlapped in different metal layers. The inductances computed using the formulas agreed well with those generated by an accurate commercial field solver, differing by less than 1% across a variety of the conductor geometries.

30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits

Silicon planar and three-dimensional inductors and transformers were designed and characterized on-wafer up to 100 GHz. Self-resonance frequencies (SRFs) beyond 100 GHz were obtained, demonstrating for the first time that spiral structures are suitable for applications such as 60-GHz wireless local area network and 77-GHz automotive RADAR. Minimizing area over substrate is critical to achieving high SRF. A stacked transformer is reported with S/sub 21/ of -2.5 dB at 50 GHz, and which offers improved performance and less area (30 /spl mu/m/spl times/30 /spl mu/m) than planar transformers or microstrip couplers. A compact inductor model is described, along with a methodology for extracting model parameters from simulated or measured y-parameters. Millimeter-wave SiGe BiCMOS mixer and voltage-controlled-oscillator circuits employing spiral inductors are presented with better or comparable performance to previously reported transmission-line-based circuits.

A novel modified-T equivalent circuit for modeling LTCC embedded inductors with a large bandwidth

This paper presents a new modified-T model for three-dimensional inductors embedded in the multilayer low-temperature cofired-ceramic substrate with a remarkably large bandwidth. This model combines a core circuit, a five-element modified-T model, to include the effects of a transmission line with an electrical length up to /spl pi/, and several resonators to consider the effects due to coil coupling and the finite ground plane. It is emphasized that most of the elements in this equivalent-circuit model can be extracted directly from the measured S-parameters. Compared to the conventional PI-section model that is valid only up to the fundamental self resonant frequency (SRF), this model can include more higher-order SRFs and ground resonant frequencies effectively, which results in several times larger bandwidth.

Fabrication of three-dimensional inductor coil using excimer laser micromachining

Conventional lithographic techniques are typically used for the fabrication of three-dimensional multilayer structures such as micro-inductors and microactuators. In this work a novel approach based exclusively on laser micromachining of dry film resists and electroplating is presented. The process involves seed layer deposition, lamination of dry film resist, laser micromachining and electroplating to mould the resist patterns. The process is then repeated, using intermediate plating seed layers if necessary, to realize the three-dimensional coil structure. The steps for sacrificial material removal involve laser patterning and chemical removal of resist and plating seed layers. The major advantages with this process are that it has fewer steps compared to conventional UV-based processing technology, and it utilizes the benefits of dry film resist processing using the laser. A three-layer micro-inductor coil was designed and fabricated using the new laser micromachining-based processing technology. The problems encountered during fabrication and possible actions to address them are discussed. This work reports the first multilayer structure that has been fabricated exclusively using laser ablation for the patterning of resist. Furthermore, this work reports the first structural layer that has been fabricated using laser ablation of resist to expose an underlying intermediate plating seed layer.

Development of three-dimensional inductors using plastic deformation magnetic assembly (PDMA)

On-chip inductors are critical for enabling portable power-efficient wireless communication systems. Existing on-chip spiral inductors based on conventional planar integrated-circuit fabrication technology suffer from substrate loss and parasitics, and have relatively large footprints. In this paper, we discuss the development of two types of on-chip three-dimensional (3-D) inductors-a vertical spiral inductor and a solenoid inductor-by using a 3-D assembly process called plastic deformation magnetic assembly. Prototype vertical spiral inductors and solenoid inductors have been fabricated and tested. Experimental results show that the vertical spiral inductors can achieve better performance and a smaller footprint than the in-plane ones.

High-Q factor three-dimensional inductors

In this paper, the great flexibility of three-dimensional (3-D) monolithic-microwave integrated-circuit technology is used to improve the performance of on-chip inductors. A novel topology for high-Q factor spiral inductor that can be implemented in a single or multilevel configuration is proposed. Several inductors were fabricated on either silicon substrate (/spl rho/ = 30 /spl Omega/ /spl middot/ cm) or semi-insulating gallium-arsenide substrate demonstrating, more particularly, for GaAs technology, the interest of the multilevel configuration. A 1.38-nH double-level 3-D inductor formed on an Si substrate exhibits a very high peak Q factor of 52.8 at 13.6 GHz and a self-resonant frequency as high as 24.7 GHz. Our 4.9-nH double-level GaAs 3-D inductor achieves a peak Q factor of 35.9 at 4.7 GHz and a self-resonant frequency of 8 GHz. For each technology, the performance limits of the proposed inductors in terms of quality factor are discussed. Guidelines for the optimum design of 3-D inductors are provided for Si and GaAs technologies.

Miniature 3-D inductors in standard CMOS process

The structure of a miniature three-dimensional (3-D) inductor is presented in this paper. The proposed miniature 3-D inductors have been fabricated in a standard digital 0.35-/spl mu/m one-poly-four-metal (1P4M) CMOS process. According to the measurement results, the self-resonance frequency f/sub SR/ of the proposed miniature 3-D inductor is 34% higher than the conventional stacked inductor. Moreover, the inductor occupies only 16% of the area of the conventional planar spiral inductor with the same inductance and maximum quality factor Q/sub max/. A 2.4-GHz CMOS low-noise amplifier (LNA), which utilized the proposed miniature 3-D inductors, has also been fabricated. By virtue of the small area of the inductor, the size and cost of the radio frequency (RF) chip can be significantly reduced.

A micromachined RF low phase noise voltage-controlled oscillator for wireless communications

An RF low phase noise voltage-controlled oscillator is implemented with micromachined IC-compatible variable capacitors and three-dimensional coil inductor. Unlike conventional on-chip passive devices, the micromachined variable capacitors achieve a high-Q value above 60 at 1 GHz with a 15% tuning range for a nominal 2 pF capacitance with 3 V tuning voltage. Three-dimensional inductors minimize the substrate loss and achieve a Q of 30 at 1 GHz with a 4.8 nH inductance. Both passive components are fabricated on silicon substrates and thus amenable to monolithic integration with standard IC process. The prototype VCO exhibits −136 dBc/Hz phase noise at 3 MHz offset frequency from the carrier, suitable for most wireless communication applications, in particular GSM. The VCO is tunable from 855 Mhz to 863 MHz, limited by the test set-up. © 2001 John Wiley & Sons, Inc. Int J RF and Microwave CAE 11: 285–300, 2001.

High-Q LTCC-based passive library for wireless system-on-package (SOP) module development

In this paper, we present the development and full characterization and modeling of a multilayer ceramic-based system-on-package component library. Compact high-Q three-dimensional inductor and capacitor topologies have been chosen and incorporated. A measured inductor Q factor as high as 100 and self-resonant frequency as high as 8 GHz have been demonstrated. The new vertically interdigitated capacitor topology occupies nearly an order of magnitude less of real estate while demonstrating comparable performance to the conventional topology. The low-temperature co-fired ceramic (LTCC) library has been incorporated into a 1.9-GHz CMOS power-amplifier design exhibiting a measured 17-dB gain, 26-dBm output power, and 48% power added efficiency. This power-amplifier module with fully integrated LTCC passives demonstrates a superior performance to those with full and partial on-chip passive integration.