Three-dimensional Device Structures Research Articles

(Invited) Heterogeneous Integration of Ultrawide Bandgap III-Nitrides and Diamond

Industry demands for power switching, amplification and photonic applications are continually pushing the limits of semiconductor device technologies leading to increasing applied voltages and, thus, higher electric fields while simultaneously requiring reduction in the size, weight and power consumption. In addition, recent heightened interest in higher temperature (and other extreme environment) applications, while simultaneously maintaining high-voltage and high-power performance, has inexorably led to ultrawide bandgap (UWBG) semiconductor materials. This interest in UWBG materials stems from superior properties that include high material hardness, breakdown strength to withstand large electric fields and mitigation of power dissipation during device switching, deliver high current density while operating at higher junction and ambient temperature. Among these materials are boron nitride in its hexagonal and cubic phases, gallium oxide, diamond, and aluminum gallium nitride. The versatile alloys of wurtzite AlxGa1-xN have long been demonstrated across the full composition range. The variation in Eg with AlGaN composition, along with select WBG and UWBG materials, is shown in Figure 1 versus (in-plane for non-cubic) lattice constant.Premier WBG materials to date for electronics and photonics are SiC (Eg = 3.3 eV) and GaN (Eg = 3.4 eV). The latter has been successfully applied to high-power transistors and near ultraviolet photonics. In both electronics and photonics applications, the polarization fields of the wurtzite crystal structure, generally grown along (0001) direction, produce design challenges. In photonics, for example, the fields and band alignment couple to spatially separate electrically injected electrons and holes to reduce wavefunction overlap in quantum wells. In electronics, the internal fields have contributed to difficulties in the design of logic and bipolar transistor devices based on these materials. Despite this, the inherent polarization field and band offsets were successfully employed in the design of high electron-mobility transistors (HEMTs). The inherent AlGaN/GaN HEMT band offset produces a high electron concentration at the interface that spontaneously forms a two-dimensional electron gas (2DEG). Because charge flow in these devices is restricted to the 2DEG, current crowding results in intense self-heating. The local heating decreases electrical conductivity to produce a runaway scenario for elevating the Joule heating. Dissipating this heat, therefore, is the principal limiting factor in operating at power higher than 40 W/mm.The various temperature dependences of semiconductor device parameters are the principal drivers in the operation of semiconductor devices. The physics has inextricably led to UWBGs for future high temperature applications, > 300 °C, due to their lower intrinsic carrier density and thus the effects of leakage are orders of magnitudes less than Si-based devices. Furthermore, AlGaN and diamond offer superior high temperature mechanical stability due to their structural hardness and chemical inertness. Thermal management is essential for achieving higher power densities. Diamond is highly attractive for many applications due to its high hardness, transparency, chemical inertness, promising semiconductor properties, and its high thermal conductivity (κ) to 2500 W/m·K in natural material. Factors related to the consequences of self-heating in devices have motivated extensive research to improve the properties of diamond and produce better approaches to determine the thermal properties. Laboratory-grown diamond films exhibit significantly poorer κ than natural diamond and, when integrated with other electronic materials, a low thermal boundary conductance (TBC in W/m2·K) that inhibits heat transfer between materials. The former originates from the ubiquitous polycrystalline nature of chemical vapor deposition (CVD) diamond and the presence of non-diamond carbon (NDC) in the layer. The low TBC stems from fundamental barriers to phonon propagation between two materials and from practical issues of poor diamond quality in the initial growth regime. Continued research is needed to improve κ in the polycrystalline diamond and mitigate the negative impact of the initial diamond layer on TBC.The current status of hetero-integration of UWBG AlGaN and diamond will be reviewed. Particular emphasis is given to high Al content AlGaN for near-bandgap matching with diamond. Patterned diamond grown using hot-filament CVD to realize unique three-dimensional lateral device structures in a self-aligned, as-grown fabrication process is employed. Engineering the AlGaN-diamond bandgap alignment is noteworthy at the nonpolar AlGaN – diamond interface including diamond surface terminations that produce either negative or positive electron affinity. The review will focus on improvements in material properties, especially the interfaces, that are critical to both charge and heat transport for UWBG device structures. Figure 1

Research Progresses on Suppressing the Short-Channel Effects of Field-Effect Transistor

Recently, with the continuous miniaturization and integration of microelectronic devices in all fields, the conventional MOSFET structure has suffered from severe short channel effects with continuous downsizing. In order to further improve the electrical properties of Very Large-Scale Integration Circuit (VLSI) and obtain the larger device integration density in circuits, new revolution in MOSFET technology is needed, which involves the innovations of new materials, new technologies, and new device structures. This paper explores device structure innovations in traditional planar transistors, such as the device performance enhancement via the high-κ/metal gate and especially the three-dimensional device structure—FinFET, as well as the subsequent development of gate-all-around FET proved to outperform FinFET. The development of high-performance devices based on new materials has become an imperative direction to break through the current bottleneck of silicon-based technologies. This paper focuses on an overview of transition-mental dichalcogenides and ferroelectric materials, including frontier research and current inadequacies. Based on these new approaches, VLSI manufacturing technology has seen many breakthroughs in recent years, which will successfully extend Moore's Law and further promote the development of emerging technologies in multiple fields.

Determining thermo-mechanical stress sources of an integrated optical device

In this study, we analyze the thermo-mechanical behavior of a multi-functional integrated optical chip (MIOC) via the finite element method (FEM). MIOC is a kind of fiber optic component which has a high thermal sensitivity. So; during temperature changes its mechanical resistance has a considerable critical significance. To investigate the thermo-mechanical effects, a three-dimensional device structure is modeled and time-dependent Von-Mises stress analyses are carried out via the multiphysics approach in the simulation environment. The simulation results are evaluated regarding the change of the crystal structure, epoxy layers, and waveguide core region. It is demonstrated that structural configuration has a crucial impact on the mechanical stability of the integrated optical device. Because of this reason, case D is accepted as a preferable geometrical structure for mass production. Also, the most dominant stress effect arises from the epoxy layer interface between the fiber pigtail carrier and lithium niobate (LiNbO3) chip called region 1. In this context, we investigate the influence of extreme thermal conditions on the induced stress on region 1. Apart from the mechanical strength of the devices, optical transmission is another subject to consider. Two claims arise on this point: power flow through the waveguide core is temperature-dependent and it is also related to the stress-optical effect. Finally, we compare the simulation results with the experimental results and there is certainly a consistency between the two separate analyses. Furthermore; it can be said that manufacturing more than 500 devices facilitates the quantitative analysis of device performance.

Line edge roughness measurement on vertical sidewall for reference metrology using a metrological tilting atomic force microscope

Line edge roughness (LER) measurement is one of the metrology challenges for three-dimensional device structures, and LER reference metrology is important for reliable LER measurements. For the purpose of LER reference metrology, we developed an LER measurement technique that can analyze LER distribution along the height of a line pattern, with high resolution and repeatability. A high-resolution atomic force microscopy (AFM) image of a vertical sidewall of a line pattern was obtained using a metrological tilting-AFM, which offers SI-traceable dimensional measurements. The tilting-tip was controlled with an inclined servo axis, and it scans the vertical sidewall along a line pattern with a high sampling density to enable an analysis of the LER height distribution at the sidewall. A horizontal cross-section of the sidewall shows sidewall roughness with sub-nm resolution. Power spectral density (PSD) analysis of the sidewall profile showed that the PSD noise in the high-frequency region was several orders of magnitude lower than the noise of typical scanning electron microscopy methods. AFM measurements were sequentially repeated three times to evaluate the repeatability of the LER measurement; results indicated a high repeatability of 0.07 nm evaluated as a standard deviation of LER at each height.

Out-of-plane electric whiskers based on nanocarbon strain sensors for multi-directional detection

Conventional Si-based electronics cannot realize unique macroscale device structures for various applications such as robotics, healthcare, and Internet of Things concepts. For example, mimicking animal whiskers to sense environmental obstacles requires detection in multiple directions and an array structure without sacrificing mechanical flexibility and complexity. To address these challenges, this study proposes an out-of-plane electric whisker array using transferred-nanocarbon strain sensors in polydimethylsiloxane (PDMS). Eight directional force detection and a 3 × 3 array device proof-of-concept are demonstrated by monitoring the resistance change of an integrated strain sensor surrounding a whisker structure. Due to the embedded nanocarbon structure into PDMS, the sensor is mechanically robust and stable for long-time measurements. Although a three-dimensional device structure is used, sensor integration is realized via the simple device fabrication process, suggesting that an out-of-plane flexible integrated sensor platform has potential in future applications for macroscale flexible electronics without increasing complexity.

AsH3 gas-phase ex situ doping 3D silicon structures

Dopant incorporation in Si can be done in situ during epitaxial growth, or ex situ for localised material modification from a variety of sources including ion, solid, liquid, or gas. Gas-phase doping has the advantage that it does not require a thin film deposition, it is more effective at entering tight spaces than a liquid, and it is less damaging and more conformal than a beam-line ion implant. In this work, we apply arsine (AsH3) gas at approximately atmospheric pressures in order to n-type dope three-dimensional (3D) Si device structures. It was observed that the gas-phase doping can be either corrosive or gentle to thin-body Si depending on the process conditions. Initial doping processes caused damage to the Si due to etching, but after process optimisation, the structural integrity of the Si nanostructures could be maintained successfully. Moreover, it was noted that evaluating doping processes entirely on planar Si surfaces can be misleading: processes which appear promising initially may not be transferrable to non-planar thin-body structures like fins or nanowires, due to unwanted Si etching. Overall, we found that gas-phase doping with AsH3 could provide >1020 cm−3 electrically active As concentrations. This high As incorporation makes gas-phase doping very attractive for future gate-all-around devices, where the space between features will decline with continued transistor scaling.

Formation technology of flat surface with epitaxial growth on ion-implanted (100)-oriented Si surface of thin silicon-on-insulator

For the development of three-dimensional devices, selective epitaxial growth (SEG) technology has attracted much attention. SEG has been applied to fabricate many devices and it is expected to be used in future manufacturing processes. Therefore, its characteristics must be examined in detail to extend its application. For the fabrication of a three-dimensional device structure, the selectivity of epitaxial growth must be accurately controlled not only on Si and SiO2, but also on different impurity-type silicon surfaces. In this work, we investigated some characteristics of the SEG process, especially focusing on the surface roughness after SEG. Both vapor phase epitaxy (VPE) and solid phase epitaxy (SPE) were performed on ion-implanted silicon-on-insulator (SOI) thin wafers. It was often reported that epitaxial growth is very sensitive to the crystal condition of the substrate on which the films are deposited. However, we first revealed that the impurity type (p- or n-type) and its concentration at the substrate surface markedly changed the roughness and incubation times of the deposition. From our results, SPE with the oxide cap layer formation is effective for maintaining almost the same flatness as the original wafer surface. It is also effective to employ the low-temperature H2/Xe plasma treatment after the SEG to reduce roughness.

Analytical coupled-wave model for photonic crystal surface-emitting quantum cascade lasers.

An analytical coupled-wave model is developed for surface-emitting photonic-crystal quantum cascade lasers (PhC-QCLs). This model provides an accurate and efficient analysis of full three-dimensional device structure with large-area cavity size. Various laser properties of interest including the band structure, mode frequency, cavity loss, mode intensity profile, and far field pattern (FFP), as well as their dependence on PhC structures and cavity size, are investigated. Comparison with numerical simulations confirms the accuracy and validity of our model. The calculated FFP and polarization profile well explain the previously reported experimental results. In particular, we reveal the possibility of switching the lasing modes and generating single-lobed FFP by properly tuning PhC structures.

Performance projections for ballistic carbon nanotube FinFET at circuit level

A novel three-dimensional device structure for a carbon nanotube (CNT) fin field-effect transistor (FinFET) is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22-nm node at the circuit level using three performance metrics including propagation delay, total power dissipation, and energy-delay product (EDP). Compared with a Si FinFET, the CNT FinFET presents obvious advantages in speed and EDP arising from its almost much larger current density but also results in a higher total power dissipation, especially at a low threshold voltage (V th = 1/3V dd). A suitable improvement in V th can effectively contribute to a significant suppression of leakage current and power dissipation, and then an obvious optimization is obtained in the EDP with an acceptable sacrifice in speed. In particular, CNT FinFETs with optimized threshold voltages can provide an EDP advantage of approximately 50 times over Si FinFETs under a low supply voltage (V dd = 0.4 V), suggesting great potential for CNT FinFET-based integrated circuits.

A three-dimensional flexible supercapacitor with enhanced performance based on lightweight, conductive graphene-cotton fabric electrode

Recently, the topic of developing lightweight, flexible and implantable energy storage systems to address the energy-supply problem of wearable electronics has aroused increasing interests. In this paper, by introducing reduced graphene oxide (rGO), we successfully converted the commercial cotton fabric into free-standing, electrically conductive and electrochemically active fabric. Flexible supercapacitor based on the obtained conductive reduced graphene oxide-carbonized cotton fabric (rGO/CCF) exhibits high capacitance (87.53 mF cm−2 at 2 mV s−1), well cycling stability (89.82% capacitance retention after 1000 charge–discharge cycles) and excellent electrochemical stability (90.5% capacitance retention after 100 bending cycles). Moreover, a macroscopic three-dimensional sandwich-interdigital device structure was designed to enhance the supercapacitor performance. The unique rGO/CCF based sandwich-interdigital structure (SIS) supercapacitor shows a volumetric capacitance of 5.53 F cm−3 at current density of 0.0625 A cm−3 in aqueous electrolyte, which is 1.67 and 4.28 orders higher than the traditional sandwich structure (SS) and interdigital structure (IS) supercapacitor based on the same electrode material and electrolyte. Furthermore, energy density enhancement of the supercapacitor has also been achieved by adopting the well-designed device structure. The original SIS supercapacitor based on the elaborate device structure and high-performance electrode material may provide new design opportunities for flexible energy storage devices.

Bipolar stacked quasi-all-solid-state lithium secondary batteries with output cell potentials of over 6 V.

Designing a lithium ion battery (LIB) with a three-dimensional device structure is crucial for increasing the practical energy storage density by avoiding unnecessary supporting parts of the cell modules. Here, we describe the superior secondary battery performance of the bulk all-solid-state LIB cell and a multilayered stacked bipolar cell with doubled cell potential of 6.5 V, for the first time. The bipolar-type solid LIB cell runs its charge/discharge cycle over 200 times in a range of 0.1–1.0 C with negligible capacity decrease despite their doubled output cell potentials. This extremely high performance of the bipolar cell is a result of the superior battery performance of the single cell; the bulk all-solid-state cell has a charge/discharge cycle capability of over 1500 although metallic lithium and LiFePO4 are employed as anodes and cathodes, respectively. The use of a quasi-solid electrolyte consisting of ionic liquid and Al2O3 nanoparticles is considered to be responsible for the high ionic conductivity and electrochemical stability at the interface between the electrodes and the electrolyte. This paper presents the effective applications of SiO2, Al2O3, and CeO2 nanoparticles and various Li+ conducting ionic liquids for the quasi-solid electrolytes and reports the best ever known cycle performances. Moreover, the results of this study show that the bipolar stacked three-dimensional device structure would be a smart choice for future LIBs with higher cell energy density and output potential. In addition, our report presents the advantages of adopting a three-dimensional cell design based on the solid-state electrolytes, which is of particular interest in energy-device engineering for mobile applications.

Computational study of graphene-based vertical field effect transistor

Poisson and drift-diffusion equations are solved in a three-dimensional device structure to simulate graphene-based vertical field effect transistors (GVFETs). Operation mechanisms of the GVFET with and without punched holes in the graphene source contact are presented and compared. The graphene-channel Schottky barrier can be modulated by gate electric field due to graphene's low density of states. For the graphene contact with punched holes, the contact barrier thinning and lowering around punched hole edge allow orders of magnitude higher tunneling current compared to the region away from the punched hole edge, which is responsible for significant performance improvement as already verified by experiments. Small hole size is preferred due to less electrostatic screening from channel inversion layer, which gives large electric field around the punched hole edge, thus, leading to a thinner and lower barrier. Bilayer and trilayer graphenes as the source contact degrade the performance improvement because stronger electrostatic screening leads to smaller contact barrier lowering and thinning. High punched hole area percentage improves current performance by allowing more gate electric field to modulate the graphene-channel barrier. Low effective mass channel material gives better on-off current ratio.

Fabrication and characterization of a piezoelectric gallium nitride switch for optical MEMS applications

The utilization of gallium nitride (GaN) in the area of microelectronics continues to increase due to the advantages it offers over other semiconductors. This paper presents GaN as a candidate material well suited for novel microelectromechanical systems (MEMS). The potential of GaN for MEMS is demonstrated via the design, analysis, fabrication, testing and characterization of an optical microswitch device actuated by piezoelectric and electrostrictive means. The piezoelectric and electrostrictive properties of GaN and its differences from common piezoelectrics are briefly discussed before touching upon the device configuration used to implement the microswitch device. Subsequently, the development of two recent fabrication technologies, photoelectrochemical etching and bias-enabled dark electrochemical etching, used to realize the three-dimensional device structure in GaN are described in detail. Lastly, an ultra-low-cost, laser-based, non-contact approach to test and characterize the microswitch device is described, followed by the device testing results.

Conformal Ni-silicide formation over three-dimensional device structures

This letter reports on conformal formation of ultrathin Ni-silicide films over a three-dimension structure relevant to the most advanced tri-gate transistor architecture. This is achieved by combining ionization of the sputtered Ni atoms with application of an appropriate bias to the Si substrate during the sputter-deposition of Ni films. In comparison, use of ordinary DC sputtering for Ni deposition results in thinner or less uniform silicide films on the vertical sidewalls than on the top surface of the three-dimensional structure. The roughened Si sidewall surface is ascribed to be responsible for a deteriorated thermal stability of the resultant silicide films.

Comprehensive and Accurate Parasitic Capacitance Models for Two- and Three-Dimensional CMOS Device Structures

In this paper, we propose an accurate, detailed, and ready-to-use model to evaluate quickly parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar double gate (DG), and FinFET (in DG or triple-gate configuration). This model takes into account raised source drain, trench contacts and discreet contacts, bilayer spacers, and inner-fringe capacitance screening. It has been validated with 2-D (FlexPDE software) and 3-D (Raphael software) simulations.

Nano/microfabrication of three-dimensional device structures using a multilayered mould approach

There is growing interest in the development of fabrication techniques to cost effectively mass-produced high-resolution (micro/nano) three-dimensional structures in a range of materials. Biomedical applications are particularly significant. This work demonstrates how to fabricate simultaneously a sacrificial mould having the inverse shape of the desired device structure and also create the desired device structure using electrodeposition techniques. The mould is constructed of many thin layers using a photo-resist material that is dissolvable and sensitive to ultraviolet (UV) light. At the same time the device is created in the emerging mould layers using gold electrodeposition technique. Choosing to fabricate the mould and the three-dimensional structures in multiple thin layers allows for the use of UV light and permits the potential cost-effective realization of three-dimensional curved surfaces, the accuracy and geometric details of which are related to the number of layers used. An example is provided to explain the novel fabrication process and to outline the resulting design and fabrication constraints.

Reduction of the PtGe/Ge Electron Schottky-Barrier Height by Rapid Thermal Diffusion of Phosphorous Dopants

The electron Schottky-barrier height (SBH) of platinum germanide diodes on germanium (PtGe/Ge) is tuned by means of incorporation of phosphorous dopants from a spin-on-dopant resist. Thereby a highly doped surface layer on Ge substrates is formed in a rapid thermal diffusion process before the formation of PtGe. Applying a diffusion process of the P atoms at temperatures above , an ohmic contact behavior is found for the originally Schottky-type barrier diodes and evidence is given for a lowered electron SBH. The contacts exhibit barrier heights to electrons as low as . In contrast, increased barrier heights for holes of are found. The results of the electrical characterization are further supported by time of flight secondary-ion mass spectrometry measurements where a pileup of P dopants at the PtGe to Ge interface region is observed. In summary, a damage-free process scheme for the reduction in the electron SBHs in PtGe/Ge diodes is given. The presented approach can pave the way to ohmic-type n-contacts to germanium and is applicable to planar as well as three-dimensional device structures.

Characteristics of Ion-Induced Bending Phenomenon

We propose a technique of bending thin films based on the ion-induced bending (IIB) phenomenon that allows the fabrication of three-dimensional device structures and arrays, such as devices for micro-electromechanical systems (MEMSs). We investigated the IIB characteristics with various types of thin films under various ion irradiation conditions. We found that the important parameters of the IIB phenomenon were the depth of ion irradiation and ion dose. We also found that bending curvature could be controlled by the normalized depth of ion implantation and the dose of ions. Microsized regions of vertically standing thin-film arrays that were tens of nanometers thick could be produced with this technique.

Horizontally aligned single-walled carbon nanotubes can bridge wide trenches and climb high steps

The direct growth of horizontally aligned single-walled carbon nanotubes (HA-SWNTs) on the two basic structures of future SWNT-based nanodevices, i.e., trenches and steps, were demonstrated. The HA-SWNTs were found to be able to bridge trenches of varying widths (up to 1000 μm across) and to climb steps of varying heights (up to ∼1500 μm high). Observations of HA-SWNTs with periodical “beeline-curve-beeline” morphologies and HA-SWNTs which grew along step walls when climbing steps indicate that the popular “tip-floating” growth mechanism for HA-SWNTs should be modified because it is not always suitable for our HA-SWNTs. The consequence of HA-SWNTs being able to bridge wide trenches and to climb high steps suggests a promising way to fabricate nanodevices by directly integrating HA-SWNTs into three-dimensional device structures.

Patterned growth of silicon oxide nanowires from iron ion implantedSiO2 substrates

We demonstrate experimentally a simple and efficient approach for silicon oxide nanowire growth, by implantingFe+ ions intothermally grown SiO2 layers on Si wafers and subsequently annealing in argon and hydrogen to nucleate thenanowires. We study the effect of implantation dose and energy, growth temperature,H2 gas flow, and growth time on the silicon oxide nanowire growth. We find thatsufficiently high implant dose, high growth temperature, and the presence ofH2 gas flow are crucial parameters for silicon oxide nanowire growth.We also demonstrate the patterned growth of silicon oxide nanowires inlocalized areas by lithographic patterning and etching of the implantedSiO2 substrates before growth. We propose a simple physical model to explain the growthresults. This works opens up the possibility of growing silicon oxide nanowires directly fromsolid substrates, controlling the location of nanowires at the submicron scale, andintegrating them into nonplanar three-dimensional nanoscale device structures.