Abstract

Line edge roughness (LER) measurement is one of the metrology challenges for three-dimensional device structures, and LER reference metrology is important for reliable LER measurements. For the purpose of LER reference metrology, we developed an LER measurement technique that can analyze LER distribution along the height of a line pattern, with high resolution and repeatability. A high-resolution atomic force microscopy (AFM) image of a vertical sidewall of a line pattern was obtained using a metrological tilting-AFM, which offers SI-traceable dimensional measurements. The tilting-tip was controlled with an inclined servo axis, and it scans the vertical sidewall along a line pattern with a high sampling density to enable an analysis of the LER height distribution at the sidewall. A horizontal cross-section of the sidewall shows sidewall roughness with sub-nm resolution. Power spectral density (PSD) analysis of the sidewall profile showed that the PSD noise in the high-frequency region was several orders of magnitude lower than the noise of typical scanning electron microscopy methods. AFM measurements were sequentially repeated three times to evaluate the repeatability of the LER measurement; results indicated a high repeatability of 0.07 nm evaluated as a standard deviation of LER at each height.

Highlights

  • The line edge roughness (LER) of a line pattern is an important dimensional parameter and should be measured precisely for the fabrication of semiconductor devices

  • An LER measurement technique was developed based on the tilting-mAFM technique for LER reference metrology

  • The calculation of the Power spectral density (PSD) and height correlation function (HHCF) indicated that the proposed tilting-mAFM method had much lower noise than a typical SEM, further investigation into noise in the high-frequency region in the PSD is necessary

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Summary

Introduction

The line edge roughness (LER) of a line pattern is an important dimensional parameter and should be measured precisely for the fabrication of semiconductor devices. Critical-dimension scanning electron microscopes (CD-SEM) are commonly used as LER metrology tools in the fabrication process because of their high throughput and reasonably good resolution. The use of CD-SEMs to provide absolute LER measurements at the sub-nm scale is unreliable because of the difficulty of line-edge determination[1] and the random noise in the high-frequency region.[2,3,4] As the dimensions of semiconductor devices continue to decrease, the horizontal resolution of the SEM becomes insufficient. CD-SEM provides a top-view (twodimensional) metrology and cannot be used to measure a three-dimensional (3-D) profile of the vertical sidewall of a line pattern. LER measurements done only by CD-SEM are no longer reliable when considering recent lithography advances; the determination of a new LER metrology method poses a new metrology challenge for 3-D device structures.[5]

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