Reduction Of Threading Dislocation Density Research Articles

Impacts of Dislocations and Residual Thermal Tension on Monolithically Integrated InGaP/GaAs/Si Triple‐Junction Solar Cells

Direct epitaxy of III−V materials on Si is a promising approach for highly stable, scalable, and efficient Si‐based multijunction solar cells. However, challenges lie in overcoming epitaxial dislocations and residual thermal strain generated by lattice constant and thermal‐expansion‐coefficient mismatches, respectively. Herein, a 15.2% efficient InGaP/GaAs/Si triple‐junction solar cell with an open‐circuit voltage of 2.36 V by using In0.10Al0.16Ga0.74As digital‐alloy dislocation filter layers is first demonstrated. The filter layers are utilized in the n‐GaAs buffer on Si to reduce threading dislocation density to 4 × 107 cm−2 while maintaining optical transparency to Si bottom cell. Then, the impacts of threading dislocations and residual tension on InGaP/GaAs/Si cells are systematically investigated by comparing them to the co‐grown InGaP/GaAs tandem cells on a native GaAs substrate. Based on the comparative analysis, a strategy to suppress material deformation and defect formation toward 30% efficient InGaP/GaAs/Si triple‐junction solar cells is proposed.

Enhanced Optical Gain of c-plane InGaN Laser Diodes via a Strain Relaxed Template with reduced Threading Dislocation Density

Enhanced Optical Gain of c-plane InGaN Laser Diodes via a Strain Relaxed Template with reduced Threading Dislocation Density

Optimizing misfit dislocation glide kinetics for enhanced threading dislocation density reduction in Si1−xGex/Si(001) layers through dynamic growth rate control

Relaxed Si1−xGex layers on Si(001) serve as virtual substrates for strained Si or Ge layers. However, plastically relaxed layers inevitably contain misfit and threading dislocations, negatively affecting devices. Deposition of a SiGe layer on the backside of the substrate introduces a dislocation reservoir at the wafer edge that can reduce the threading dislocation density (TDD) of Si0.98Ge0.02/Si layers, as these preexisting dislocations start gliding toward the wafer center upon reaching the critical thickness. Here, we show that this low-strain system can be used effectively to study dislocation glide kinetics. In agreement with the literature, dislocation glide is a thermally activated process with an activation energy of 2.12–2.16 eV. Near the critical thickness, relaxation is sluggish and inefficient due to the linear dependence of the glide velocity on excess stress. At lower growth rates, dislocations from the edge reservoir are activated in a lower density due to the increase in the critical thickness through partial strain relaxation by already activated dislocations. Contrary to common models, here, the lowest possible growth rate is not essential for minimizing the TDD. Instead, a careful balance between low and high growth rates is beneficial. Overcoming the initial sluggish and inefficient relaxation phase is critical while also avoiding accumulation of strain energy, and, therefore, the activation of dislocation sources. Only in a later stage of buffer growth, the growth rate should be reduced to a minimum. With this method, the TDD of strain relaxed Si0.84Ge0.16 layers is reduced to 7 × 104 cm−2.

Exploring the Implementation of GaAsBi Alloys as Strain-Reducing Layers in InAs/GaAs Quantum Dots.

This paper investigates the effect of GaAsBi strain reduction layers (SRLs) on InAs QDs with different Bi fluxes to achieve nanostructures with improved temperature stability. The SRLs are grown at a lower temperature (370 °C) than the usual capping temperature for InAs QDs (510 °C). The study finds that GaAs capping at low temperatures reduces QD decomposition and leads to larger pyramidal dots but also increases the threading dislocation (TD) density. When adding Bi to the capping layer, a significant reduction in TD density is observed, but unexpected structural changes also occur. Increasing the Bi flux does not increase the Bi content but rather the layer thickness. The maximum Bi content for all layers is 2.4%. A higher Bi flux causes earlier Bi incorporation, along with the formation of an additional InGaAs layer above the GaAsBi layer due to In segregation from QD erosion. Additionally, the implementation of GaAsBi SRLs results in smaller dots due to enhanced QD decomposition, which is contrary to the expected function of an SRL. No droplets were detected on the surface of any sample, but we did observe regions of horizontal nanowires within the epilayers for the Bi-rich samples, indicating nanoparticle formation.

Impact of Pocket Geometry on Quantum Dot Lasers Grown on Silicon Wafers

Epitaxially grown quantum dot (QD) lasers in narrow pockets on patterned silicon photonics wafers present a key step toward full monolithic integration of on‐chip light sources. However, InAs QD lasers grown in deep and narrow pockets demonstrate limited performance and reliability compared to planar‐grown counterparts. Herein, InAs QD lasers are grown in patterned SiO2 pockets atop planar thermal cyclic annealed GaAs on (001) Si substrate with reduced threading dislocation density, enabling detailed study of how pocket geometry impacts device performance. Fabry–Pérot lasers with cleaved facets exhibit strong variation in performance based on the dimensions of the pocket, wherein thermal and optical metrics improve with increasing pocket width. Devices lase up to a maximum stage temperature of 115 °C with an extrapolated lifetime of 2.2 years at 80 °C for material grown in 50 μm by 3900 μm pockets. This study addresses, the ongoing challenge of optimizing pocket‐grown devices to planar equivalent performance.

Reduction of Structural Defects in the GaSb Buffer Layer on (001) GaP/Si for High Performance InGaSb/GaSb Quantum Well Light-Emitting Diodes.

Monolithic integration of GaSb-based optoelectronic devices on Si is a promising approach for achieving a low-cost, compact, and scalable infrared photonics platform. While tremendous efforts have been put into reducing dislocation densities by using various defect filter layers, exploring other types of extended crystal defects that can exist on GaSb/Si buffers has largely been neglected. Here, we show that GaSb growth on Si generates a high density of micro-twin (MT) defects as well as threading dislocations (TDs) to accommodate the extremely large misfit between GaSb and Si. We found that a 250 nm AlSb single insertion layer is more effective than AlSb/GaSb strained superlattices in reducing both types of defects, resulting in a 4× and 13× reduction in TD density and MT density, respectively, compared with a reference sample with no defect filter layer. InGaSb quantum well light-emitting diodes were grown on the GaSb/Si templates, and the effect of TD density and MT density on their performance was studied. This work shows the importance of using appropriate defect filter layers for high performance GaSb-based optoelectronic devices on standard on-axis (001) Si via direct epitaxial growth.

Nucleation and Growth of GaAs on a Carbon Release Layer by Halide Vapor Phase Epitaxy.

We couple halide vapor phase epitaxy (HVPE) growth of III-V materials with liftoff from an ultrathin carbon release layer to address two significant cost components in III-V device - epitaxial growth and substrate reusability. We investigate nucleation and growth of GaAs layers by HVPE on a thin amorphous carbon layer that can be mechanically exfoliated, leaving the substrate available for reuse. We study nucleation as a function of carbon layer thickness and growth rate and find island-like nucleation. We then study various GaAs growth conditions, including V/III ratio, growth temperature, and growth rate in an effort to minimize film roughness. High growth rates and thicker films lead to drastically smoother surfaces with reduced threading dislocation density. Finally, we grow an initial photovoltaic device on a carbon release layer that has an efficiency of 7.2%. The findings of this work show that HVPE growth is compatible with a carbon release layer and presents a path toward lowering the cost of photovoltaics with high throughput growth and substrate reuse.

The Si (001) substrate with sub-nano streaky surface: Preparation and its application to high-quality growth of GaAs heteroepitaxial-layer

The Si (001) substrates with a kind of special sub-nano streaky surface were prepared and applied to high-quality growth of GaAs heteroepitaxial-layers. The morphology of each of them features a series of parallel but randomly intermittent streaks along a common fixed direction and individually with their own saw-tooth cross-sections. The lateral interval between any two adjacent streaks is bound to be in sub-nano scale and both the two side-facets of every cross-section sawtooth are {111} planes. It has been found that the direct growth of GaAs epilayers on this kind of substrates, especially on exactly (001) oriented ones, can not only completely prevent the antiphase boundaries (APBs) generation, but also significantly reduce the threading dislocation density (TDD). This advancement could be regarded as a nearly perfect solution to APBs elimination and, moreover, provides better basis for further TDD reduction in the preparation of III-V/Si epilayers and for relevant device fabrications.

Origin of residual strain in heteroepitaxial films

Heterogeneous integration of diverse materials structures is critical to the scaling of electronic and photonic integrated circuits. For a model system of Ge-on-Si, we experimentally examine the roles of lattice misfit and thermal expansion misfit in determining the residual strain in as-grown and annealed heteroepitaxial films. We present data for Ge-on-Si growth from 400 to 730 °C followed by heat treatment from 500–900 °C. We show that strain fluctuations of 5.02% enable misfit dislocation formation, and we propose a comprehensive model for the conversion of compressive misfit strain to tensile elastic strain. The model is expressed in terms of three regimes: (1) misfit control for the low temperature growth regime at 400 °C; (2) point defect control via annealing in the point defect recovery regime at 500–650 °C; and (3) thermal expansion control for growth or anneal at T > 650 °C in the dislocation recovery regime. Growth from 400 to 730 °C exhibits near complete misfit strain relief by misfit dislocations leaving a consistent residual compressive strain of 0.09%. Growth at 400 °C followed by post growth heat treatment at 600 °C results in vertical threading dislocation density reduction via a point defect-mediated climb mechanism that gives minimal strain relief. Anneal above 650 °C promotes strain relief by dislocation glide. Temperature excursions at T > 730 °C followed by cooling to room temperature yield plastic strain in the Ge film that cannot be further relieved by thermal expansion misfit accommodation. Growth at 400–730 °C retains a residual compressive strain that represents the nucleation threshold for misfit dislocations.

Towards Efficient Electrically-Driven Deep UVC Lasing: Challenges and Opportunities

The major issues confronting the performance of deep-UV (DUV) laser diodes (LDs) are reviewed along with the different approaches aimed at performance improvement. The impact of threading dislocations on the laser threshold current, limitations on heavy n- and p-doping in Al-rich AlGaN alloys, unavoidable electron leakage into the p-layers of (0001) LD structures, implementation of tunnel junctions, and non-uniform hole injection into multiple quantum wells in the active region are discussed. Special attention is paid to the current status of n- and p-type doping and threading dislocation density reduction, both being the factors largely determining the performance of DUV-LDs. It is shown that most of the above problems originate from intrinsic properties of the wide-bandgap AlGaN semiconductors, which emphasizes their fundamental role in the limitation of deep-UV LD performance. Among various remedies, novel promising technological and design approaches, such as high-temperature face-to-face annealing and distributed polarization doping, are discussed. Whenever possible, we provided a comparison between the growth capabilities of MOVPE and MBE techniques to fabricate DUV-LD structures.

Mid-infrared InAs/InAsSb Type-II superlattices grown on silicon by MOCVD

In this work we report the growth of the InAs/InAsSb type-II superlattice (T2SL) onto Si substrates via the use of a GaSb/GaAs/Si buffer layer structure all grown by MOCVD. Transmission electron microscopy (TEM) was used to show the effectiveness of the buffer layer structure in reducing threading dislocation density and to verify the formation of an interfacial misfit dislocation array between the GaSb and GaAs layers. Electron channelling contrast imaging was used to measure a threading dislocation density of 6.73 × 108/cm2 at the surface of the T2SL. TEM and X-ray diffraction show that the T2SL itself was grown to a high quality considering the large mismatch of the heteroepitaxy. Fourier transform infrared spectroscopy was used to measure the photoluminescence performance of the T2SL which was found to have a FWHM of 50 meV at a peak wavelength of 4.5 µm at 77 K. These results are a step forward towards integration of full InAs/InAsSb T2SL device structures onto Si substrates via MOCVD.

Reduced threading dislocation density in a germanium epitaxial film coalesced on an arrayed silicon-on-insulator strip

This paper reports a reduction in the threading dislocation density (TDD) of a Ge epitaxial film on a Si-on-insulator (SOI) wafer in terms of the Si-photonics device application. An array of submicron SOI strips is prepared as a patterned substrate, on which Ge is epitaxially grown by chemical vapor deposition. A continuous Ge film is formed by a coalescence of the adjacent Ge crystals on the arrayed SOI strip, while leaving semicylindrical voids on the exposed surface of the buried SiO2 (BOX) layer between the strips. The TDD of the coalesced Ge film is reduced to 1.0 ± 0.1 × 108 cm–2, which is approximately a half of 2.2 ± 0.2 × 108 cm–2 for a Ge film on an unpatterned SOI. A transmission electron microscope observation reveals that the TDD reduction is derived from a downward bending of the dislocation toward the void. An accumulation of the dislocations at the strip sidewalls also contributes to the TDD reduction.

Self-Assembled Size-Tunable Microlight-Emitting Diodes Using Multiple Sapphire Nanomembranes.

Microlight-emitting diode (Micro-LED) is the only display production technology capable of meeting the high-performance requirements of future screens. However, it has significant obstacles in commercialization due to etching loss and efficiency reduction caused by the singulation process, in addition to expensive costs and a significant amount of time spent on transfer. Herein, multiple-sapphire nanomembrane (MSNM) technology has been developed that enables the rapid transfer of arrays while producing micro-LEDs without the need for any singulation procedure. Individual micro-LEDs of tens of μm size were formed by the pendeo-epitaxy and coalescence of GaN grown on 2 μm width SNMs spaced with regular intervals. We have successfully fabricated micro-LEDs of different sizes including 20 × 20 μm2, 40 × 40 μm2, and 100 × 100 μm2, utilizing the membrane design. It was confirmed that the 100 × 100 μm2 micro-LED manufactured with MSNM technology not only relieved stress by 80.6% but also reduced threading dislocation density by 58.7% compared to the reference sample. It was proven that micro-LED arrays of varied chip sizes using MSNM were all transferred to the backplane. A vertical structure LED device could be fabricated using a 100 × 100 μm2 micro-LED chip, and it was confirmed to have a low operation voltage. Our work suggests that the development of the MSNM technology is promising for the commercialization of micro-LED technology.

Repeatability and Mechanisms of Threading Dislocation Reduction in InN Film Grown with In Situ Surface Modification by Radical Beam Irradiation

The objective of this study was to investigate the repeatability of in situ surface modification by radical beam irradiation to reduce threading dislocation density in InN film. The growth of InN template and N radical irradiation processes were repeated twice in situ in the radio-frequency plasma-excited molecular beam epitaxy chamber before the regrowth of InN film on the N radical irradiated template. Transmission electron microscopy was applied to study dislocation behaviors of the InN film grown. In this letter, we show cross-sectional-view transmission electron microscopy evidence of the threading dislocation reduction from ~2.8×1010 cm-2 in the first irradiated InN layer to ~2.0×1010 cm-2 in the second irradiated InN layer, and to ~1.3×1010 cm-2 in the top regrown InN layer. The mechanisms of threading dislocation reduction were also studied.

Origination and evolution of point defects in AlN film annealed at high temperature

While high temperature annealing has been proven to be an effective strategy to reduce threading dislocation density of AlN film, the point defect induced near-ultraviolet emission increases dramatically with the increase in annealing temperature, and thus limits its application in deep ultraviolet optoelectronic devices. Herein, the origination and evolution of point defects in high-temperature annealed AlN are studied and clarified by photoluminescence spectroscopy, secondary ion mass spectrometry, positron annihilation and first-principles calculation. We have confirmed that (1) the annealing induces the increased O impurity concentration by two orders of magnitude; (2) The increase of O impurity concentration in AlN after high temperature annealing is the key factor that causes the evolution of point defects and the enhancement of near ultraviolet defect peak; (3) the formation of more O content [VAl-n(ON)] and VN at different annealing temperatures are responsible for photoluminescence evolution. Present work reveals the formation mechanism of point defects in AlN and provides further support for improving the quality of AlN.

Threading Dislocation Reduction of Ge by Introducing a SiGe/Ge Superlattice

The influence of introducing a SiGe/Ge superlattice (SL) between Ge layers and Si substrate for the sake of the reduction of the threading dislocation density (TDD) without additional annealing is investigated. By introducing the SiGe/Ge SL and optimizing the layer stack, the TDD of the Ge layer becomes ∼1/3. In the case of 2.8 μm thick Ge without introducing the SiGe/Ge SL, the TDD at the surface is 7.6 × 108 cm−2. A slight TDD reduction is observed by introducing a Si0.2Ge0.8/Ge SL between the Si substrate and the Ge layer. By inserting 5, 10 and 20 cycles of Si0.2Ge0.8/Ge, the TDD is reduced to 7.1 × 108, 5.9 × 108 and 5.3 × 108 cm−2, respectively. The lateral lattice parameters of these SLs are ∼5.656 Å, which is a smaller value compared to that of bulk Ge, indicating plastic relaxation by misfit dislocation formation. Further TDD reduction is realized with increasing Si concentration in the SiGe/Ge SL without changing the cycle of the SL. However, surface roughening due to pit formation occurs if the Si concentration in the SL is higher than 50% because of increased strain at the interfaces between SiGe and Ge. With increasing SiGe and Ge thickness ratio in the SL layer and maintaining periodicity and cycles, the TDD is reduced to 2.8 × 108 cm−2 without degrading the surface roughness. This improvement is related to a relaxation of the SiGe/Ge SL by plastic deformation.

Optimized InAlAs graded buffer and tensile-strained dislocation filter layer for high quality InAs photodetector grown on Si

We demonstrate a low threading dislocation density (TDD) and smooth surface InAs layer epitaxially grown on Si by suppressing phase separation of InxAl1−xAs (x = 0 to 1) graded buffer and by inserting a tensile-strained In0.95Al0.05As dislocation filter layer. While keeping the total III–V layer below 2.7 μm to avoid thermal cracks, we have achieved a sixfold reduction of TDD in InAs on Si compared to the unoptimized structure. We found a strong correlation between the metamorphic InAs surface roughness and TDD as a function of InxAl1−xAs buffer thickness. An optimal thickness of 175 nm was obtained where both phase separation and 3D islanding growth were suppressed. Moreover, a tensile-strained In0.95Al0.05As dislocation filter layer and high growth temperature of the InAs cap layer further assisted the dislocation reduction process, which led to a TDD to 1.37 × 108 cm−2. Finally, an InAs p-i-n photodetector grown on the optimized InAs/Si template confirmed its high quality by showing an improved responsivity from 0.16 to 0.32 A/W at a 2 μm wavelength.

Designing an Epitaxially-Integrated DBR for Dislocation Mitigation in Monolithic GaAsP/Si Tandem Solar Cells

This work explores epitaxially integrated distributed Bragg reflectors (DBR) as a strategy to mitigate the impact of threading dislocations on the performance of monolithic GaAs0.75P0.25/Si tandem solar cells. The constraints present because of materials availability and the optical transmission profile of the GaAs0.75P0.25 top cell require the use of an enhanced bandwidth DBR design achieved by combining two narrow-band DBRs with different central wavelengths. The impact of this DBR structure on J SC, along with the competing effects of threading dislocation density (TDD), is investigated using a robust, experimentally informed analytical model. Implementing this DBR within the GaAs0.75P0.25/Si tandem cell structure is predicted to yield a short-circuit current enhancement equivalent to the ∼1.8× reduction in TDD, providing a clear demonstration of its promise as a design methodology for mitigating the impact of non-negligible defect populations.

Reduction of threading dislocation density beyond the saturation limit by optimized reverse grading

The threading dislocation density (TDD) in plastically relaxed Ge/Si(001) heteroepitaxial films is commonly observed to decrease progressively with their thickness due to mutual annihilation. However, there exists a saturation limit, known as the geometrical limit, beyond which a further decrease of the TDD in the Ge film is hindered. Here, we show that such a limit can be overcome in SiGe/Ge/Si heterostructures thanks to the beneficial role of the second interface. Indeed, we show that ${\mathrm{Si}}_{0.06}{\mathrm{Ge}}_{0.94}/\mathrm{Ge}/\mathrm{Si}(001)$ films display a TDD remarkably lower than the saturation limit of Ge/Si(001). Such a result is interpreted with the help of dislocation dynamics simulations. The reduction of TDD is attributed to the enhanced mobility acquired by preexisting threading dislocations after bending at the new interface to release the strain in the upper layer. Importantly, we demonstrate that the low TDD achieved in ${\mathrm{Si}}_{0.06}{\mathrm{Ge}}_{0.94}/\mathrm{Ge}/\mathrm{Si}$ layers is preserved also when a second, relaxed Ge layer is subsequently deposited. This makes the present reverse-grading technique of direct interest also for achieving a low TDD in pure-Ge films.

A TEM Study of AlN–AlGaN–GaN Multilayer Buffer Structures on Silicon Substrates

Two buffer structures based on AlxGa1 – xN solutions with silicon doping and without it have been studied by transmission electron microscopy. The structures have been grown on silicon substrates with the (111) orientation by metalorganic vapor-phase epitaxy with consistently decreasing Al content. A significant threading dislocation density reduction in the region of intermediate layers has been found at a change in the Al content from 32 to 23%. Phase decay and the phenomenon of compositional self-modulation in the AlxGa1 – xN layers in the direction of growth have been detected at an Al content equal to 32, 23, 12, and 4%. A model of the structure of layers in the region of composition modulation has been proposed.