Threading Defects Research Articles

Growth and structural characterization of embedded InAsSb on GaAs-coated patterned silicon by molecular beam epitaxy

The molecular beam epitaxial growth of InAsSb on GaAs-coated patterned Si substrates is reported. The epilayers are grown embedded in wells so a coplanar Si-InAsSb surface can be obtained. The InAsSb epilayer morphology is compared for different substrate conditions (Si−well, Si−mesa, GaAs) using Nomarski contrast microscopy. High-voltage electron microscopy shows that the threading defect density of the InAsSb layers is high but decreases with thickness. In the reduced area electron diffraction pattern of the GaAs-InAsSb interface, additional diffraction spots are visible due to microtwins in the InAsSb. High-resolution electron microscopy reveals a regular array of misfit dislocations relieving the 14.2% lattice mismatch in the early stage of growth. Stripping Hall measurements for InAs0.05Sb0.95 show a constant mobility as a function of depth for the top 2 μm of the film and the 300 and 77 K mobility values are comparable.

A New Approach for Low Defect Density GaAs On Patterned Si Substrates by Mocvd

High quality GaAs films have been deposited on sawtooth-patterned (0.2 μm period) Si substrates by MOCVD. Three inch diameter Si wafers were patterned using a combination of holographic lithography and wet chemical etching. A two-step deposition process was used resulting in planar films with surface morphology comparable to films deposited on unpatterned substrates. The initial low temperature nucleation layer was found to be amorphous and conformed to the patterned Si surface. Rapid thermal annealing and thermal cycle growth resulted in substantial reduction in the threading defect density. The MOCVD growth and characterization of these films and the possible mechanisms responsible for the reduction/elimination of the defects at the GaAs/Si interface are discussed.

TEM studies of MOVPE (Ga,In)As interfaces with InP substrates

In MOVPE growth of epilayers of the ternary composition Ga 0.47In 0.53As, nominally lattice matched to InP substrates, a complete change in the occupancy of the group V sublattice is involved. At the commencement of growth, the low concentration of PH 3 needed to stabïlize the InP surface must be changed to an AsH 3 mixture. To achieve the sharp interfaces required in many device applications it is consequently necessary to adopt a low growth rate and fast gas compositional switching. To assess the magnitude of the problem, interfaces obtained in two types of growth equipment have been studied by TEM, both in plan view and cross-section. A very disturbed interface region was found which gave rise to numerous threading defects extending into the ternary layer. Micrographs of the interface show Moiré fringes which can be interpreted as lattice spacing variations, corresponding to a lattice mismatch approaching the difference between InP and InAs lattices. The micrographs also show evidence that nucleation of the disturbed region is non-uniform. Modifications to the reactor to reduce the time taken for gas compositional switching, and the use of an InP buffer layer, resulted in a substantial improvement in the interface region, with a consequent reduction in the density of threading defects in the epilayer.

Electron Microscope Studies Of Vpe Gainas Layer Structures Suitable For Use As Infrared Leds

SUMMARYElectron microscope investigations have been carried out on vapour grown (100) GaAs/GaInAs structures designed for use as infrared emitters of wavelength 1·06 μm. The structures consist of a GaAs substrate, a graded layer in which the indium concentration is increased from zero to 17 atomic %, and a constant composition Ga0·83In0·17As layer which contains a p‐n junction. X‐ray microprobe analysis of cross‐sections of the slices established the uniformity of the grading. TEM analysis showed a dense and extensive asymmetric network of misfit dislocations (1 × 1012 m−2 (108 cm−2)) in the graded layer, threading dislocations and other anomalous contrast features extending from the graded layer through the p‐n junction to the surface (local densities of 1 × 1011–1 × 1012 m−2 (107–108 cm−2)), and a planar network of dislocations just below the surface (spacing 0·2–2 μm). SEM EBIC and CL studies of the layer above the junction revealed dark spots, and a cross‐grid of dark lines, which could be correlated with the threading defects, and the dislocation network just below the surface, respectively. The SEM results showed that these defects had a deleterious effect on the luminescent and electrical properties of the material in the vicinity of the p‐n junction, and would therefore impair the performance of devices made from these layer structures.