Execution Of Threads Research Articles

Speeding up single-query sampling-based algorithms using case-based reasoning

We present an extension to the single-query sampling-based algorithm for improving its response time using Case-Based Reasoning (CBR) technique. Unlike traditional experience-based planners, CBR depends on a single thread execution which reduces the required computation power. Additionally, it is always biased towards exploration rather than exploitation to overcome experience-based algorithms drawbacks. Results indicate that CBR extension has significantly improved sampling-based response time for similar served queries.

Synchronous Signals

In Ada 2012, the language expanded its support for concurrency with the addition of the Synchronous Barriers library package to the Real-Time Systems annex[1]. This package provides a mechanism to synchronize a group of tasks after the number of blocked tasks reaches a specified count value. One use for this feature is to interleave sequential processing with concurrent or parallel processing. For this usage, two syncrhonous barrier objects can be utilized where one barrier manages the transition from parallel to sequential code, and the other barrier manages the transition back from sequential to parallel code. In general, performance can be improved by minimizing the amount of synchronization in an application. The more that threads of execution can proceed independentally without interference with other threads, the more likely that the available CPUs can focus on completing the independent tasks rather than spending time synchronizing with the other threads. A Synchronous Signal is a synchronization primitive that provides a similar abstraction as a Synchronous Barrier, except it can reduce the amount of synchronization needed by a factor of two. In addition, only one object is needed, to manage both transitions instead of two. In this paper, the abstraction is explored and an interface to use the abstraction is presented. Two forms of the abstraction are considered; a blocking form and a non-blocking form, and the performance measurements are reported and compared against Synchronous Barriers usage. Finally, these examples are also compared and considered for use in a Ravenscar environment.

Scaling read aligners to hundreds of threads on general-purpose processors.

MotivationGeneral-purpose processors can now contain many dozens of processor cores and support hundreds of simultaneous threads of execution. To make best use of these threads, genomics software must contend with new and subtle computer architecture issues. We discuss some of these and propose methods for improving thread scaling in tools that analyze each read independently, such as read aligners.ResultsWe implement these methods in new versions of Bowtie, Bowtie 2 and HISAT. We greatly improve thread scaling in many scenarios, including on the recent Intel Xeon Phi architecture. We also highlight how bottlenecks are exacerbated by variable-record-length file formats like FASTQ and suggest changes that enable superior scaling.Availability and implementationExperiments for this study: https://github.com/BenLangmead/bowtie-scaling.Bowtie http://bowtie-bio.sourceforge.net.Bowtie 2 http://bowtie-bio.sourceforge.net/bowtie2.HISAT http://www.ccb.jhu.edu/software/hisat Supplementary information Supplementary data are available at Bioinformatics online.

System-Wide Time versus Density Tradeoff in Real-Time Multicore Fluid Scheduling

Recent parallel programming frameworks such as OpenCL and OpenMP allow us to enjoy the parallelization freedom for real-time tasks. The parallelization freedom creates the time versus density tradeoff problem in fluid scheduling, i.e., more parallelization reduces thread execution times but increases the density. By system-widely exercising this tradeoff, we propose optimal parameter tuning of real-time tasks aiming at maximizing the schedulability of multicore fluid scheduling. Our experimental study by both simulation and actual implementation shows that the proposed approach well balances the time and the density, and results in up to 80 percent improvement of the schedulability.

An integrated autonomous control mechanism to optimize sharing of multiple resources in Simultaneous Multi-Threading processors

Abstract Simultaneous Multi-Threading (SMT) processors allow concurrent execution of multiple independent threads with sharing of key datapath components to enhance system performance with more efficient resource utilization. However, due to the nature of SMT processing, imbalanced distribution of critical shared resources may easily clog some pipeline stages by slower threads and lead to unexpected system performance degradation. In this paper, an integrated autonomous control mechanism is proposed to optimize the use of two critical shared resources among multiple threads based on threads’ temporal behaviors in real time, by taking into account resource utilization snapshots at various stages of the pipeline. Our simulations based on M-Sim (Sharkey, 2005) [1] show that our proposed mechanism improves IPC (Instruction Per Clock Cycle) by a very significant margin (up to 100.4%) without sacrificing execution fairness among threads. Performance improvement from the proposed integrated approach on the two shared resources easily surpasses the aggregated benefits from two control mechanisms with each considering only one individual resource at a time.

Stretching algorithm for global scheduling of real-time DAG tasks

Parallelism is becoming more important nowadays due to the increasing use of multiprocessor systems. A Directed Acyclic Graph (DAG) is a general model of parallel tasks with inter-subtask parallelism. It consists of a collection of dependent subtasks under precedence constraints. In this paper, we study the problem of scheduling n periodic parallel real-time DAG tasks on m homogeneous multiprocessor systems. The dependencies between subtasks make scheduling process more challenging. We propose a stretching algorithm to be applied on each DAG task prior to scheduling process. Thus, DAGs are transformed into a set of independent sequential threads with intermediate offsets and deadlines. The threads obtained due to the transformation are of two types, (i) fully-stretched master threads with utilization equal to 1 and (ii) independent constrained-deadline threads. We propose a scheduling method over RTOS to ensure the execution of fully-stretched master threads on dedicated processors while the remaining processors $$\overline{m} \le m$$ , are used to schedule the independent constrained-deadline threads using any multiprocessor scheduling algorithm. In this work, we analyze the stretching algorithm while considering two global preemptive scheduling algorithms from different priority assignment families; the Global Earliest Deadline First (GEDF) from the fixed job priority family, and the Global Deadline Monotonic (GDM) from the fixed task priority family. We prove that GEDF scheduling of stretched threads has a resource augmentation bound equal to $$\frac{3+\sqrt{5}}{2}$$ for all task sets with $$n < \varphi \times \overline{m}$$ , where n is the number of tasks in the set and $$\varphi $$ is the golden ratio (the value of the golden ratio is $$\frac{1+\sqrt{5}}{2}$$ ). While GDM has a resource augmentation bound equal to $$2+\sqrt{3}$$ for all task sets with $$n < \frac{1+\sqrt{3}}{2} \times \overline{m}$$ .

CTS: An operating system CPU scheduler to mitigate tail latency for latency-sensitive multi-threaded applications

Large-scale interactive Web services break a user’s request to many sub-requests and send them to a large number of independent servers so as to consult multi-terabyte datasets instantaneously. Service responsiveness hinges on the slowest server, making the tail of the latency distribution of individual servers a matter of great concern. A large number of latency-sensitive applications hosted on individual servers use thread-driven concurrency model wherein a thread is spawned for each user connection. Threaded applications rely on the operating system CPU scheduler for determining the order of thread execution. Our experiments show that the default Linux scheduler (CFS) idiosyncrasies result in LCFS (Last Come First Served) scheduling of threads belonging to the same application. On the other hand, studies have shown that FCFS (First Come First Served) scheduling yields the lowest response time variability and tail latency, making the default scheduler of Linux a source of long tail latency for multi-threaded applications. In this paper, we present CTS, an operating system CPU scheduler to trim the tail of the latency distribution for latency-sensitive multi-threaded applications while maintaining the key characteristics of the default Linux scheduler (e.g., fairness). By adding new data structures to the Linux kernel, CTS tracks threads belonging to an application in a timely manner and schedules them in FCFS manner, mitigating the tail latency. To keep the existing features of the default Linux scheduler intact, CTS keeps CFS responsible for system-wide load balancing and core level process scheduling; CTS merely schedules threads of the CFS chosen process in FCFS order, ensuring tail latency mitigation without sacrificing the default Linux scheduler properties. Experiments with a prototype implementation of CTS in the Linux kernel demonstrate that CTS significantly outperforms the Linux default scheduler. For example, CTS mitigates the tail latency of a Null RPC server by up to 96%, a Thrift server by up to 90% and an Apache Web server by up to 51% at 99.9th percentile.

Tigr

Graph analytics delivers deep knowledge by processing large volumes of highly connected data. In real-world graphs, the degree distribution tends to follow the power law -- a small portion of nodes own a large number of neighbors. The high irregularity of degree distribution acts as a major barrier to their efficient processing on GPU architectures, which are primarily designed for accelerating computations on regular data with SIMD executions. Existing solutions to the inefficiency of GPU-based graph analytics either modify the graph programming abstraction or rely on changes to the low-level thread execution models. The former requires more programming efforts for designing and maintaining graph analytics; while the latter couples with the underlying architectures, making it difficult to adapt as architectures quickly evolve. Unlike prior efforts, this work proposes to address the above fundamental problem at its origin -- the irregular graph data itself. It raises a critical question in irregular graph processing: Is it possible to transform irregular graphs into more regular ones such that the graphs can be processed more efficiently on GPU-like architectures, yet still producing the same results? Inspired by the question, this work introduces Tigr -- a graph transformation framework that can effectively reduce the irregularity of real-world graphs with correctness guarantees for a wide range of graph analytics. To make the transformations practical, Tigr features a lightweight virtual transformation scheme, which can substantially reduce the costs of graph transformations, while preserving the benefits of reduced irregularity. Evaluation on Tigr-based GPU graph processing shows significant and consistent speedup over the state-of-the-art GPU graph processing frameworks for a spectrum of irregular graphs.

A Low-Energy Multi-Threaded Processor Design for Application Specific Embedded Systems

Energy consumption is a critical issue in embedded systems design. A basic way for an embedded processor system to be energy efficient is to complete execution early and consume low power. Multi threaded processors interleave thread execution, reducing the processor’s idle time, hence the overall execution time. Caches moderate the long and power hungry external memory accesses, allowing for both performance improvement and power saving. However, when the two techniques are applied together, the efficiency of the design may not be as high as expected. The multi threaded execution can adversely interfere cache operations, increasing cache misses and leading to overall performance loss and large energy consumption. This paper presents a microarchitecture level design to enable the synergy of the two design techniques for embedded processors. Particularly we focus on a single pipeline processor with an instruction cache for applications that offer embarrassing parallelism. Such a design can be used as a building block processor for large computing systems. We propose a thread synchronization and cache locking scheme to allow cached instructions to be maximally reused by all threads. The experiments on a set of applications show that for the designs with 1 way cache and 300MB memory, an average of 26% baseline energy can be saved, and the energy savings become more significant when the memory size is increased.

AMPLE: an anytime planning and execution framework for dynamic and uncertain problems in robotics

Acting in robotics is driven by reactive and deliberative reasonings which take place in the competition between execution and planning processes. Properly balancing reactivity and deliberation is still an open question for harmonious execution of deliberative plans in complex robotic applications. We propose a flexible algorithmic framework to allow continuous real-time planning of complex tasks in parallel of their executions. Our framework, named AMPLE, is oriented towards robotic modular architectures in the sense that it turns planning algorithms into services that must be generic, reactive, and valuable. Services are optimized actions that are delivered at precise time points following requests from other modules that include states and dates at which actions are needed. To this end, our framework is divided in two concurrent processes: a planning thread which receives planning requests and delegates action selection to embedded planning softwares in compliance with the queue of internal requests, and an execution thread which orchestrates these planning requests as well as action execution and state monitoring. We show how the behavior of the execution thread can be parametrized to achieve various strategies which can differ, for instance, depending on the distribution of internal planning requests over possible future execution states in anticipation of the uncertain evolution of the system, or over different underlying planners to take several levels into account. We demonstrate the flexibility and the relevance of our framework on various robotic benchmarks and real experiments that involve complex planning problems of different natures which could not be properly tackled by existing dedicated planning approaches which rely on the standard plan-then-execute loop.

Real-time physical register file allocation with neural networks for simultaneous multi-threading processors

Simultaneous multi-threading (SMT) processors improve system performance by allowing concurrent execution of multiple independent threads with shared key resources. Physical register file, shared among the threads in real-time, is one of the most critical resources in deciding overall system performance. Disproportional distribution of registers among the threads may easily hamper normal processing of some threads. In this paper, we develop a machine learning algorithm to efficiently allocate registers among concurrent executing threads based on current resource utilisation circumstances. An offline training process is first employed to establish a well-trained neural network which is then applied to dynamically adjust the resource distribution in real-time. Our experiment results on M-sim, which is a multi-threaded micro-architectural simulation environment, show that our proposed technique significantly improves the average system throughput by up to 42% without sacrificing execution fairness among the threads.

Automatically accelerating non-numerical programs by architecture-compiler co-design

Because of the high cost of communication between processors, compilers that parallelize loops automatically have been forced to skip a large class of loops that are both critical to performance and rich in latent parallelism. HELIX-RC is a compiler/microprocessor co-design that opens those loops to parallelization by decoupling communication from thread execution in conventional multicore architecures. Simulations of HELIX-RC, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks.

A path-level exact parallelization strategy for sequential simulation

Sequential Simulation is a well known method in geostatistical modelling. Following the Bayesian approach for simulation of conditionally dependent random events, Sequential Indicator Simulation (SIS) method draws simulated values for K categories (categorical case) or classes defined by K different thresholds (continuous case). Similarly, Sequential Gaussian Simulation (SGS) method draws simulated values from a multivariate Gaussian field. In this work, a path-level approach to parallelize SIS and SGS methods is presented. A first stage of re-arrangement of the simulation path is performed, followed by a second stage of parallel simulation for non-conflicting nodes. A key advantage of the proposed parallelization method is to generate identical realizations as with the original non-parallelized methods. Case studies are presented using two sequential simulation codes from GSLIB: SISIM and SGSIM. Execution time and speedup results are shown for large-scale domains, with many categories and maximum kriging neighbours in each case, achieving high speedup results in the best scenarios using 16 threads of execution in a single machine.

Thread scheduling using ant colony optimization: An intelligent scheduling approach towards minimal information leakage

In multithreaded programs, scheduler controls the execution of threads. As a result, the scheduler may arrange the execution sequence of threads in such a way that multithreaded programs may violate the non-interference confidentiality policy. Due to a violation of non-interference, multithreaded programs may leak security sensitive information. In the proposed work, Ant Colony Optimization (ACO) based intelligent scheduling policy has been proposed in the form of algorithms to schedule threads in multithreading environment in such a way that the execution sequence leads to minimal information leakage. In the present work, the proposed scheduler also deals with conflicting scheduling parameters and provides the algorithmic solution which can handle all conflicting entities of scheduling like throughput, delay, security-privacy and fairness. In this work, dynamic creation and deletion of threads are also handled during the scheduling. Although the focus of this work is on the scheduling of threads, the proposed policy can be used as a general purpose scheduling policy in many computing fields.

Adaptive parallel Louvain community detection on a multicore platform

Community detection is a demanded technique in analyzing complex and massive graph-based networks. The quality of the detected communities in an acceptable time is an important aspect of an algorithm, which aims at passing through an ultra large scale graph, for instance a social network graph. In this paper, an efficient method is proposed to tackle Louvain community detection problem on multicore systems in the line of thread-level parallelization. The main contribution of this article is to present an adaptive parallel thread assignment for the calculation of adding qualified neighbor nodes to the community. This leads to obtain a better load balancing method for the execution of threads. The proposed method is evaluated on an AMD system with 64 cores, and can reduce the execution time by 50% in comparison with the previous fastest parallel algorithms. Moreover, it was observed in the course of the experiments that our method could find comparably qualified communities.

SKIRT: Hybrid parallelization of radiative transfer simulations

We describe the design, implementation and performance of the new hybrid parallelization scheme in our Monte Carlo radiative transfer code SKIRT, which has been used extensively for modeling the continuum radiation of dusty astrophysical systems including late-type galaxies and dusty tori. The hybrid scheme combines distributed memory parallelization, using the standard Message Passing Interface (MPI) to communicate between processes, and shared memory parallelization, providing multiple execution threads within each process to avoid duplication of data structures. The synchronization between multiple threads is accomplished through atomic operations without high-level locking (also called lock-free programming). This improves the scaling behavior of the code and substantially simplifies the implementation of the hybrid scheme. The result is an extremely flexible solution that adjusts to the number of available nodes, processors and memory, and consequently performs well on a wide variety of computing architectures.

SURVEY ON SIGNATURE BASED INTRUCTION DETECTION SYSTEM USING MULTITHREADING

The traditional way of protecting networks with firewalls and encryption software is no longer sufficient and effective. Many intrusion detection techniques have been developed on fixed wired networks but have been turned to be inapplicable in this new environment. We need to search for new architecture and mechanisms to protect computer networks. Signature-based Intrusion Detection System matches network packets against a pre-configured set of intrusion signatures. Current implementations of IDS employ only a single thread of execution and as a consequence benefit very little from multi-processor hardware platforms. A multi-threaded technique would allow more efficient and scalable exploitation of these multi-processor machines.

LOCK-FREE DINING PHILOSOPHER

The past few years have marked the start of a historic transition from sequential to parallel computation.The necessity to write parallel programs is increasing as systems are getting more complex while processor speed increases are slowing down. Current parallel programming uses low-level programming constructs like threads and explicit synchronization using locks to coordinate thread execution. Parallel programs written with these constructs are difficult to design, program and debug. Also locks have many drawbacks which make them a suboptimal solution. Software Transactional Memory (STM) is a promising new approach to programming shared-memory parallel processors. It is a concurrency control mechanism that is widely considered to be easier to use by programmers than locking. It allows portions of a program to execute in isolation, without regard to other, concurrently executing tasks. A programmer can reason about the correctness of code within a transaction and need not worry about complex interactions with other, concurrently executing parts of the program. This paper shows the concept of writing code using Software Transactional Memory (STM) and the performance comparison of codes using locks with those using STM.

Cigarette-Smokers’ Problem with STM

The past few years have marked the start of a historic transition from sequential to parallel computation. The necessity to write parallel programs is increasing as systems are getting more complex while processor speed increases are slowing down. Current parallel programming uses low-level programming constructs like threads and explicit synchronization using locks to coordinate thread execution. Parallel programs written with these constructs are difficult to design, program and debug. Also locks have many drawbacks which make them a suboptimal solution. One such drawback is that locks should be only used to enclose the critical section of the parallel-processing code. If locks are used to enclose the entire code then the performance of the code drastically decreases. Software Transactional Memory (STM) is a promising new approach to programming shared-memory parallel processors. It is a concurrency control mechanism that is widely considered to be easier to use by programmers than locking. It allows portions of a program to execute in isolation, without regard to other, concurrently executing tasks. A programmer can reason about the correctness of code within a transaction and need not worry about complex interactions with other, concurrently executing parts of the program. If STM is used to enclose the entire code then the performance of the code is the same as that of the code in which STM is used to enclose the critical section only and is far better than code in which locks have been used to enclose the entire code. So STM is easier to use than locks as critical section does not need to be identified in case of STM. This paper shows the concept of writing code using Software Transactional Memory (STM) and the performance comparison of codes using locks with those using STM. It also shows why the use of STM in parallel-processing code is better than the use of locks.

Generality and Speed in Nonblocking Dual Containers

Nonblocking dual data structures extend traditional notions of nonblocking progress to accommodate partial methods, both by bounding the number of steps that a thread can execute after its preconditions have been satisfied and by ensuring that a waiting thread performs no remote memory accesses that could interfere with the execution of other threads. A nonblocking dual container, in particular, is designed to hold either data or requests . An insert operation either adds data to the container or removes and satisfies a request; a remove operation either takes data out of the container or inserts a request. We present the first general-purpose construction for nonblocking dual containers, allowing any nonblocking container for data to be paired with almost any nonblocking container for requests. We also present new custom algorithms, based on the LCRQ of Morrison and Afek, that outperform the fastest previously known dual containers by factors of four to six.