Third-party Intellectual Property Research Articles

Designing Energy-Efficient MPSoC with Untrustworthy 3PIP Cores

The adoption of large-scale MPSoCs and the globalization of the IC design flow give rise to two major concerns: high power density due to continuous technology scaling and security due to the untrustworthiness of the third-party intellectual property (3PIP) cores. However, little work has been undertaken to consider these two critical issues jointly during the design stage. In this paper, we propose a design methodology that minimizes the energy consumption while simultaneously protecting the MPSoC against the effects of hardware trojans. The proposed methodology consists of three main stages: 1) Task scheduling to introduce core diversity in the MPSoC in order to detect the presence of malicious modifications in the cores, or mute their effects at runtime, 2) Vendor assignment to the cores using a novel heuristic that chooses vendor-specific cores with operating speed that minimizes the total energy consumption of the MPSoC, and 3) Explore optimization opportunities for further energy savings by minimizing idle periods on the cores, which are caused by the inter-task data dependencies. Experimental results show that our solutions consume only 1/3 energy of existing solutions without increasing schedule length while satisfying the security constraints.

CAD-Base

Fabless semiconductor companies design system-on-chips (SoC) by using third-party intellectual property (IP) cores and fabricate them in offshore, potentially untrustworthy foundries. Owing to the globally distributed electronics supply chain, security has emerged as a serious concern. In this article, we explore electronics computer-aided design (CAD) software as a threat vector that can be exploited to introduce vulnerabilities into the SoC. We show that all electronics CAD tools—high-level synthesis, logic synthesis, physical design, verification, test, and post-silicon validation—are potential threat vectors to different degrees. We have demonstrated CAD-based attacks on several benchmarks, including the commercial ARM Cortex M0 processor [1].

Stigmergy-Based Security for SoC Operations From Runtime Performance Degradation of SoC Components

The semiconductor design industry of the embedded era has embraced the globalization strategy for system on chip (SoC) design. This involves incorporation of various SoC components or intellectual properties (IPs), procured from various third-party IP (3PIP) vendors. However, trust of an SoC is challenged when a supplied IP is counterfeit or implanted with a Hardware Trojan Horse. Both roots of untrust may result in sudden performance degradation at runtime. None of the existing hardware security approaches organize the behavior of the IPs at the low level, to ensure timely completion of SoC operations. However, real-time SoC operations are always associated with a deadline, and a deadline miss due to sudden performance degradation of any of the IPs may jeopardize mission-critical applications. We seek refuge to the stigmergic behavior exhibited in insect colonies to propose a decentralized self-aware security approach. The self-aware security modules attached with each IP works based on the Observe-Decide-Act paradigm and not only detects vulnerability but also organizes behavior of the IPs dynamically at runtime so that the high-level objective of task completion before a deadline is ensured. Experimental validation and low overhead of our proposed security modules over various benchmark IPs and crypto SoCs depict the prospects of our proposed mechanism.

Combining PUF with RLUTs

With the popularity of modern FPGAs, the business of FPGA specific intellectual properties (IP) is expanding rapidly. This also brings in the concern of IP protection. FPGA vendors are making serious efforts toward IP protection, leading to standardization schemes like IEEE P1735. However, efficient techniques to prevent unauthorized overuse of IP still remain an open question. In this article, we propose a two-party IP protection scheme combining the re-configurable look-up table primitive of modern FPGAs with physically unclonable functions (PUF). The proposed scheme works with the assumption that the FPGA vendor provides the assurance of confidentiality and integrity of the developed IP. The proposed scheme is considerably lightweight compared to existing schemes, prevents overuse, and does not involve FPGA vendors or trusted third parties for IP licensing. The validation of the proposed scheme is done on MCNC’91 benchmark and third-party IPs like AES and lightweight MIPS processors.

A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

Since integrated circuits are performed by several untrusted manufacturers, malicious circuits (hardware Trojans) can be implanted in any stage of the Internet-of-Things (IoT) devices. With the globalization of the IoT device manufacturing technologies, protecting the system-on-chip (SoC) security is always the keys issue for scientists and IC manufacturers. The existing SoC high-level synthesis approaches cannot guarantee both register-transfer-level and gate-level security, such as some formal verification and circuit characteristic analysis technologies. Based on the structural characteristics of hardware Trojans, we propose a multi-layer hardware Trojan protection framework for the Internet-of-Things perception layer called RG-Secure , which combines the third-party intellectual property trusted design strategy with the scan-chain netlist feature analysis technology. Especially at the gate level of chip design, our RG-Secure is equipped with a distributed, lightweight gradient lifting algorithm called lightGBM. The algorithm can quickly process high-dimensional circuit feature information and effectively improve the detection efficiency of hardware Trojans. In the meanwhile, a common evaluation index F-measure is used to prove the effectiveness of our method. The experiments show that RG-Secure framework can simultaneously detect register-transfer-level and gate-level hardware Trojans. For the trust-HUB benchmarks, the optimized lightGBM classifier achieves up to 100% true positive rate and 94% true negative rate; furthermore, it achieves 99.8% average F-measure and 99% accuracy, which shows a promising approach to ensure security during the design stage.

Hardware Trojan Detection in Third-Party Digital Intellectual Property Cores by Multilevel Feature Analysis

In modern integrated circuit (IC) designs, intellectual property (IP) cores are often outsourced and designed by third-party vendors, resulting in the partial relinquishment of the control over the IC design flow. Thus, reliable verifications are required to mitigate the threat of hardware Trojans (HTs) which may be inserted into IP cores by malicious vendors. Existing trustiness verification methods cannot take the merit of high efficiency and accuracy at the same time. In this paper, we propose a multilevel fast trustiness verification framework based on feature analysis to detect HTs in third-party digital IP cores. The proposed framework combines flip-flop level and combinational logic level feature analysis to achieve both high efficiency and accuracy. Experimental results demonstrate that both explicitly and implicitly triggered HTs can be detected in very short time with a negligible false positive rate. More importantly, our framework has the unique advantage of being scalable to defend against future and stealthier HTs by adding new features into the framework.

Towards Quantified Data Analysis of Information Flow Tracking for Secure System Design

Computing hardware has become an attractive attack surface due to the globalization of semi-conductor design and supply chain, and the wide integration of third-party intellectual property cores. Recently, gate-level information flow tracking (GLIFT) has been proposed to monitor the flow of information in secure hardware design by associating data objects with sensitivity labels and tracking the flow of labeled data. GLIFT can be used to model and verify security-related properties, such as confidentiality and integrity. However, existing work in this realm only considers binary labels. These are inadequate for understanding simultaneous information flow behaviors and the root source information flows. In this paper, we propose a precise multi-bit GLIFT method to perform simultaneous multi-bit flow tracking for understanding exactly which bits are affecting a data object at the same time. The proposed method provides more detailed insights into simultaneous information flow behaviors and thus allows proof of quantitative information flow data properties. We compare the complexity and verification performance for different information flow models using primitive gates, IWLS benchmarks, several cryptographic cores, and trust-HUB benchmarks. Experimental results have demonstrated that our method can reason about multi-bit information flow behaviors and identify potential security flaws.

Security-Aware Task Scheduling Using Untrusted Components in High-Level Synthesis

The high penetration of third-party intellectual property is accompanied with severe security issues, and thus, security constraints during task scheduling have recently been proposed for protecting multiprocessor system-on-chip systems. However, these security constraints incur significant overheads in terms of the schedule length and design cost. In this paper, the multi-dimensional design optimization space (schedule length, design cost, area, and security) is explored, and two task scheduling approaches in the context of security constraints are proposed. In resource-constrained task scheduling approach, the maximum clique of a vendor violation graph is accurately calculated, enabling a minimized number of security constraint violations under the vendor constraint. In addition, task scheduling is conducted alongside vendor assignment to optimize the schedule length. In performance-constrained task scheduling approach, a max-flow min-cut-based task clustering method is first proposed to iteratively reduce the schedule length of the graph containing all critical paths. Then, vendor assignment is performed by solving a graph coloring problem, and all tasks are finally scheduled with an optimization of hardware resources. The experimental results demonstrate that our resource-constrained task scheduling approach reduces the schedule length by 28.2% with all security constraints satisfied; besides, 18.0% cores are saved by our performance-constrained task scheduling approach.

TASPDetect: Reviving Trust in 3PIP By Detecting TASP Trojans

Trustworthiness is an emerging concern in the development of Multi-Processor System-on-Chip (MPSoC) systems, which often include Third-Party Intellectual Property (3PIP) cores. Malicious hardware trojans in these 3PIP components can create a plethora of system vulnerabilities. In this paper, we explore an imminent threat that originates from a 3PIP core: architectural state preserving trojans (TASP). We illustrate that a malicious TASP can affect the performance of a core without altering its architectural state, thereby disrupting the availability of on-chip resources in a MPSoC system. We propose three complementary techniques to detect active TASPs in a 3PIP core with overheads of less than 5%.

A defense mechanism against hardware Trojan insertion by third-party intellectual property (IP) design blocks in AES-based secured communication system

The available hardware Trojan insertion techniques in IC design and the prevention methods against these hardware Trojans are reviewed. The focus of the paper is on the hardware Trojan insertion by the third-party IP design blocks and its prevention method. The AES-based secured communication system codename Alpha is demonstrated to be susceptible to the hardware Trojan insertion that is induced by the third-party IP design blocks. In order to prevent this hardware Trojan to manifest in Alpha system, the Alpha system is modified and redesigned. The Trojan-infected Alpha system and modified Alpha system codename ModAlpha are implemented on the ATLYS board. The area utilization and timing information of both systems are extracted and analyzed. The hardware implementation results for both systems are also observed on the UART terminal after the message is inputted by the keyboard. It is proven that the Trojan-infected Alpha system leaks the encryption key on the UART terminal while the modified Alpha system produces the correct cipher text.

Towards Protected MPSoC Communication for Information Protection against a Malicious NoC

Multiprocessor System-on-Chip (MPSoC) design is based on the integration of several third-party Intellectual Property (IP) cores. Some of those IPs may include Trojans, extra hardware that can be triggered during operation time in order to perform an attack. Network-on-Chip (NoC), the communication IP of MPSoCs, can include Trojans that spy, modify and constrain the sensitive communication inside the chip. Although previous works address the malicious NoC threat, finding secure and efficient solutions is still a challenge. In this work, we propose a novel and secure network interface which implements a tunnel-based protocol that enables the secure exchange of sensitive data even in the presence of a malicious NoC. We test our technique with synthetic traffic as well as in several real application scenarios, and show that it is a secure and efficient solution.

Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach

Trustworthiness of system-on-chip designs is undermined by malicious logic (Trojans) in third-party intellectual properties (3PIPs). In this paper, duplication, diversity, and isolation principles have been extended to detect build trustworthy systems using untrusted, potentially Trojan-infected 3PIPs. We use a diverse set of vendors to prevent collusions between the 3PIPs from the same vendor. We identify design constraints for Trojan detection to achieving detection, collusion prevention, and isolating the Trojan-infected 3PIP, and incorporate them during high-level synthesis. In addition, we develop techniques to reduce the number of vendors. The effectiveness of the proposed techniques is validated using the high-level synthesis benchmarks.

Dynamic FPGA Detection and Protection of Hardware Trojan: A Comparative Analysis

Hardware Trojan detection and protection is becoming more crucial as more untrusted third parties manufacture many parts of critical systems nowadays. The most common way to detect hardware Trojans is comparing the untrusted design with a golden (trusted) one. However, third-party intellectual properties (IPs) are black boxes with no golden IPs to trust. So, previous attempts to detect hardware Trojans will not work with third-party IPs. In this work, we present novel methods for Trojan protection and detection on field programmable gate arrays (FPGAs) without the need for golden chips. Presented methods work at runtime instead of test time. We provide a wide spectrum of Trojan detection and protection methods. While the simplest methods have low overhead and provide limited protection mechanisms, more sophisticated and costly techniques are introduced that can detect hardware Trojans and even clean up the system from infected IPs. Moreover, we study the cost of using the FPGA partial reconfiguration feature to get rid of infected IPs. In addition, we discuss the possibility to construct IP core certificate authority that maintains a centralized database of unsafe vendors and IPs. We show the practicality of the introduced schemes by implementing the different methodologies on FPGAs. Results show that simple methods present negligible overheads and as we try to increase security the delay and power overheads increase.

Detection of Hardware Trojans in Third-Party Intellectual Property Using Untrusted Modules

During the design of an integrated circuit, there are several opportunities for adversaries to make malicious modifications or insertions to a design. These attacks, known as hardware Trojans, can have catastrophic effects on a circuit if left undetected. This paper describes a technique for identifying hardware Trojans with logic-based payloads that are hidden within third-party intellectual property. Through comparison of two similar but untrusted designs, functional differences can be identified for all possible input combinations within a window of time. This technique was tested on multiple Trojan benchmarks and was found to be very effective, both in detectability and in speed of testing. As this technique has very low costs to implement, it represents an easy way for designers to gain a level of trust in previously untrusted designs.

Sequence-Aware Watermark Design for Soft IP Embedded Processors

This paper describes a design approach for incorporating sequence-aware watermarks in soft intellectual property (IP) embedded processors. The influence of watermark sequence parameters on detection, area, and power overheads is examined, and consequently a method for incorporating sequence-aware watermarks in soft IP embedded processors is proposed. The intrinsic parameters of sequences, such as the activity factor and the overlapping factor, are introduced, and their impact on correlation results is demonstrated. Measurement and application-specified integrated circuits validate the design approach and demonstrate the resulting IP protection and subsequent costs for constrained embedded processors. Results presented in this paper show that the tradeoff occurs between the watermark robustness against third-party IP attacks and hardware implementation costs. The analysis of this tradeoff is provided, and an application specific watermark implementation is proposed.

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling

Multiprocessor system-on-chip (MPSoC) platforms face some of the most demanding security concerns, as they process, store, and communicate sensitive information using third-party intellectual property (3PIP) cores. The complexity of MPSoC makes it expensive and time consuming to fully analyze and test during the design stage. This has given rise to the trend of outsourcing design and fabrication of 3PIP components, that may not be trustworthy. To protect MPSoCs against malicious modifications, we impose a set of security-driven diversity constraints into the task scheduling step of the MPSoC design process, enabling the system to detect the presence of malicious modifications or to mute their effects during application execution. We pose the security-constrained MPSoC task scheduling as a multidimensional optimization problem, and propose a set of heuristics to ensure that the introduced security constraints can be fulfilled with a minimum impact on the other design goals such as performance and hardware. Experimental results show that without any extra cores, security constraints can be fulfilled within four vendors and 81% overhead in schedule length.

Regaining Trust in VLSI Design: Design-for-Trust Techniques

Designers use third-party intellectual property (IP) cores and outsource various steps in their integrated circuit (IC) design flow, including fabrication. As a result, security vulnerabilities have been emerging, forcing IC designers and end-users to reevaluate their trust in hardware. If an attacker gets hold of an unprotected design, attacks such as reverse engineering, insertion of malicious circuits, and IP piracy are possible. In this paper, we shed light on the vulnerabilities in very large scale integration (VLSI) design and fabrication flow, and survey design-for-trust (DfTr) techniques that aim at regaining trust in IC design. We elaborate on four DfTr techniques: logic encryption, split manufacturing, IC camouflaging, and Trojan activation. These techniques have been developed by reusing VLSI test principles.

Practical, Lightweight Secure Inclusion of Third-Party Intellectual Property

The security of computing systems relies on trust in hardware. This trust can no longer be assumed due to vulnerabilities in hardware designs. Security methodologies have been proposed for mitigating these threats, offering a variety of security guarantees and wide variance in terms of design-time and runtime costs. From an engineering standpoint it is not clear which of the plethora of solutions should be applied or how they should be implemented. We develop an engineering process for the practical and lightweight inclusion of untrusted third-party hardware design components. We find that by combining previously proposed techniques, we are able to build a microcontroller that uses each design module as if it were untrusted third-party intellectual property. Our experience supports the surprising claim that implementing a chip with untrusted components is not significantly more difficult than implementing a regular one.

RF authenticated protection scheme for SRAM-based FPGA IP cores

Field programmable gate arrays (FPGAs) have become increasingly popular due to their rapid development times and low costs. Many FPGA-based systems utilise third-party intellectual property (IP) in their development. With their increased use, the need to protect the IP against unauthorised use has become important. In this paper, we have proposed a novel wireless intellectual property protection (IPP) technique that overcomes the secure secret decryption key storage problem associated with traditional encryption-based IPP techniques that are widely used for IPP of static random access memory-based FPGA IP cores. The proposed scheme also provides an extra authentication protection for IP cores to make it more security efficient. The results derived from the testing of hardware prototype used for the evaluation of the proposed scheme are quite encouraging.

Third-Party Clearinghouses and Intellectual Property Licensing

We analyse the basic economic issues relating to third-party intellectual property clearinghouses that act as licensing intermediaries. We identify economic functions of clearinghouses and discuss ways that they can improve efficiency in licensing through centralisation and independence. We then examine clearinghouse strategy and policy with regard to establishing new clearinghouses, clearinghouse pricing and competition between clearinghouses. We also consider effects on incentives to invest in R&D and anti-trust issues.