Third-order Phase-locked Loop Research Articles

Enhancing the Filtering Capability and the Dynamic Performance of a Third-Order Phase-Locked Loop under Distorted Grid Conditions

This work proposes a structural enhancement and a new technique to design the loop filter (LF) of a third-order phase-locked loop (PLL) to enhance the PLL dynamic performance under abnormal grid conditions. The proposed PLL combines a moving average filter (MAF) and an arbitrarily delayed signal cancelation (ADSC) for structural enhancement to achieve DC-offset rejection and harmonics elimination. The window length of the MAF is selected to be one-sixth of the fundamental grid period to remove non-triple odd harmonics and speed up the PLL dynamic response. The triple harmonics are eliminated, adopting the line-to-line voltage concept, while the ADSC operator rejects the DC offset. The LF design is based on a modified third-order polynomial tuned using stochastic optimization to minimize the settling time of the frequency deviation, offering better dynamic performance over the symmetrical optimum method (SOM) and achieving synchronization within one grid cycle. The PLL mathematical model, small-signal model, and LF design based on the modified polynomial are discussed. Finally, the proposed PLL performance is verified numerically and experimentally with comparisons with other PLLs to demonstrate the effectiveness of the proposed work.

A novel high precision Doppler frequency estimation method based on the third-order phase-locked loop

In deep space exploration, many engineering and scientific requirements require the accuracy of the measured Doppler frequency to be as high as possible. In our paper, we analyze the possible frequency measurement points of the third-order phase-locked loop (PLL) and find a new Doppler measurement strategy. Based on this finding, a Doppler frequency measurement algorithm with significantly higher measurement accuracy is obtained. In the actual data processing, compared with the existing engineering software, the accuracy of frequency of 1 second integration is about 5.5 times higher when using the new algorithm. The improved algorithm is simple and easy to implement. This improvement can be easily combined with other improvement methods of PLL, so that the performance of PLL can be further improved.

A Novel Low Computational Burden Dual-Observer Phase-Locked Loop With Strong Disturbance Rejection Capability for More Electric Aircraft

In the past two decades, much research and industry effort has been dedicated to transportation electrification. In particular, aerospace industry, with the more electric aircraft (MEA) revolution, is shifting toward the usage of electrical in place of mechanical energy on board to save fossil fuel and reduce polluting emissions. For this reason, phase-locked loops (PLLs) systems have been well developed for synchronizing different power sources and loads within the aircraft electrical grid. Since one of the proposed solutions for MEA power grids is to operate at variable frequency from 360 to 800 Hz, a third-order model-based steady-state linear Kalman filter PLL (SSLKF-PLL) has been proposed in the literature to achieve fast tracking performance during such grid frequency variations. To suppress the potential disturbances due to harmonics in the grid, sensor scaling errors/unbalances, and dc offsets while maintaining low computational burden, this article aims to enhance the disturbance rejection ability of SSLKF-PLL by adding a repetitive observer (RO). Simulation and experimental tests show that RO allows stable and effective suppression of disturbances from all the abovementioned sources during variable frequency operation. The execution time of the proposed PLL is only 4.23 μs using a Xilinx Zynq-7000-based platform, where the added RO takes 2.664 μs to execute, and the SSLKF-PLL alone takes 1.566 μs.

Improving the accuracy of permanent magnet rotor position estimation for stepper motors using magnetic induction and harmonic rejection

To improve the accuracy of permanent magnet (PM) rotor position estimation for a hybrid stepper motor (HSM), the authors propose a sensorless control design based on the back electromagnetic force (back-EMF) caused by magnetic induction and harmonic rejection via an orthogonal third-order phase-locked loop (PLL3rd) and an integral harmonic filter (IHF). The accuracy of estimation is analysed considering PM rotor position estimation errors. The harmonics of the back-EMF signal are eliminated by the IHF before entering the PLL3rd, which synchronises and decreases position estimation error. This technique is a simple, reliable, and effective method for implementing sensorless control of an HSM. An industrial test-bench was used to implement the proposed scheme. The experimental results are presented to validate the effectiveness of the proposed estimation method.

An Adaptive Linear-Neuron-Based Third-Order PLL to Improve the Accuracy of Absolute Magnetic Encoders

Absolute magnetic encoders (AMEs) use two magnets: a ring multipolar magnet (MPM) generating high-resolution and improving the accuracy for the encoder, and a bipolar magnet in the center calculating the number cycle of MPM signals. The phase outputs of these AMEs are tracked from the sinusoidal signals of the MPM. However, these sine/cosine signals are disturbed by amplitude differences, offsets, phase-shift, harmonic components, and random noise. In order to solve this problem, this paper presents an adaptive linear neuron based on a third-order phase-locked loop (ALN-PLL) to improve the accuracy of AMEs. The proposed approach consists of two main parts: The first part is an ALN algorithm that uses the phase feedback of the third-order PLL in order to build the mathematical model of input signals, and then reject the disturbances. The second part is a third-order PLL that is designed based on a dominant pole approximation algorithm. The proposed PLL can reduce noise and eliminate dc-error during the phase step, frequency step, and frequency ramp. The simulation and experimental results demonstrate the effectiveness of the proposed approach.

Real-Time Estimation for Roll Angle of Spinning Projectile Based on Phase-Locked Loop on Signals from Single-Axis Magnetometer.

As roll angle measurement is essential for two-dimensional course correction fuze (2-D CCF) technology, a real-time estimation of roll angle of spinning projectile by single-axis magnetometer is studied. Based on the measurement model, a second-order frequency-locked loop (FLL)-assisted third-order phase-locked loop (PLL) is designed to obtain rolling information from magnetic signals, which is less dependent on the amplitude and able to reduce effect from geomagnetic blind area. Method of parameters optimization of tracking loop is discussed in the circumstance of different speed and it is verified by six degrees of freedom (six degrees of freedom (DoF)) trajectory. Also, the measurement error is analyzed to improve the accuracy of designed system. At last, experiments on rotary table are carried out to validate the proposed method indicating the designed system is able to track both phase and speed accurately and stably. The standard deviation (SD) of phase error is no more than 3°.

Joint Carrier Synchronization Algorithm by Open-Loop Acquisition and Closed-Loop Tracking in High-Dynamic Environments

Considering the difficulty of carrier synchronization and the low tracking accuracy in high-dynamic environments, the joint open-loop acquisition and closed-loop tracking carrier synchronization algorithm is presented. Firstly, the algorithm derives the coarse estimation of Doppler frequency and Doppler rate via open-loop acquisition, then the residual Doppler frequency and Doppler rate are confined into a small range. Secondly, the residual Doppler rate is tracked by using a third-order phase-locked loop(PLL). The present algorithm has the advantages of fast acquisition and high tracking accuracy. Finally, the numerical simulation is conducted to verify the present synchronization algorithm. The simulation results indicate that at the signal to noise ratio(SNR) of and normalized Doppler frequency and Doppler rate ranging from to, the bit-error-rate(BER) performance degradation is as low as comparing with theoretical value.

Exploring the Dynamics of a Third-Order Phase-Locked Loop Model

We study the dynamics and characterize the bifurcation structure of a phase-locked loop (PLL) device modeled by a third-order autonomous differential equation with sinusoidal phase detector. The development of this work was performed using rigorous analysis and numerical experiments. Through theoretical analysis the bifurcation structures related to two fundamental equilibrium points of the system are described. By using extensive numerical experiments we investigate the intricate organization between periodic and chaotic domains in parameter space (named here parameter plane as the PLL model has only two control parameters) and obtain two following remarkable findings: (i) there are self-organized generic stable periodic structures along specific directions in parameter plane, whose periods are defined by a mathematical rule and, (ii) the existence of transient chaos phenomenon responsible for long chaotic temporal evolution preceding the asymptotic (periodic) dynamics for some particular control parameter pairs is characterized. Our theoretical and numerical results present an astonishing concordance. We believe that the present study, specially the parameter plane analysis, may have a great importance to experimental studies and general applications involving PLL devices when, for example, one would like to avoid the chaotic regimes.

GPS navigation data bit decoding error during strong equatorial scintillation

Strong equatorial scintillation is often characterized by simultaneous fast phase changes and deep amplitude fading. The combined effect poses a challenge for GNSS receiver carrier tracking performance. One of the consequences of the strong scintillation is increased navigation message data bit decoding error. Understanding the rate of the data bit decoding error under equatorial scintillation is essential for high accuracy and high integrity applications. We present the statistical relationship between the data bit decoding error occurrences and the intensity of amplitude scintillation based on the processing of intermediate frequency GPS scintillation data collected on Ascension Island in March 2013. A third-order phase lock loop (PLL) is implemented to process the data and to access the data bit error typically expected in conventional receivers. A Kalman filter-based PLL is also used to process the same data to demonstrate that the data bit decoding error can be reduced through advanced carrier tracking designs.

A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector

A high-order cascaded phase-locked loop (PLL) architecture using a sub-sampling delay-locked loop (DLL) is proposed to break the tradeoff between the loop bandwidth and the number of integrator in the feedback loop without significantly degrading the settling time or reference spur. A clock-skew-sampling phase detector is also proposed to extend the stable detection range of the sub-sampling phase detector. Implemented in a 65-nm CMOS process, a prototype of the proposed two-stage third-order cascaded PLL measures a 4.2- $\mu \text{s}$ settling time, 1.05-ps integrated jitter, and −113-dBc/Hz in-band phase noise at a 2.1-GHz output frequency while consuming 3.84 mW at 1.2-V supply voltage and occupying a core chip area of 0.043 mm2.

Robust GPS Carrier Tracking Model Using Unscented Kalman Filter for a Dynamic Vehicular Communication Channel

The carrier tracking loop in a GPS receiver is considered to be an important process but also a weak link since the loss of signal lock can occur in a variety of situations. Low carrier-to-noise ratios and highly dynamic environments are common scenarios for a vehicular communication channel when random phase fluctuations in a dynamic environment are common. We propose a novel and robust carrier tracking approach by dynamically integrating an adaptive unscented Kalman filter assisted by a third-order phase lock loop in order to improve the robustness of tracking capability and accuracy in dense and dynamic environments. Experiments are conducted to investigate the tracking performance of the proposed carrier tracking approach and compare it with existing algorithms for generic GPS receiver. Results indicate that the proposed approach has a better performance in tracking capability and tracking accuracy in highly dynamic environments, and the proposed method achieves a better performance on vehicular communication channels.

Adaptive Gain Control Method of a Phase-Locked Loop for GNSS Carrier Signal Tracking

The global navigation satellite system (GNSS) has been widely used in both military and civil fields. This study focuses on enhancing the carrier tracking ability of the phase-locked loop (PLL) in GNSS receivers for high-dynamic application. The PLL is a very popular and practical approach for tracking the GNSS carrier signal which propagates in the form of electromagnetic wave. However, a PLL with constant coefficient would be suboptimal. Adaptive loop noise bandwidth techniques proposed by previous researches can improve PLL tracking behavior to some extent. This paper presents a novel PLL with an adaptive loop gain control filter (AGCF-PLL) that can provide an alternative. The mathematical model based on second- and third-order PLL was derived. The error characteristics of the AGCF-PLL were also derived and analyzed under different signal conditions, which mainly refers to the different combinations of carrier phase dynamic and signal strength. Based on error characteristic curves, the optimal loop gain control method has been achieved to minimize tracking error. Finally, the completely adaptive loop gain control algorithm was designed. Comparable test results and analysis using the new method, conventional PLL, FLL-assisted PLL, and FAB-LL demonstrate that the AGCF-PLL has stronger adaptability to high target movement dynamic.

A Low-Jitter Full-Rate 25-Gb/s CDR for 100-Gb/s Optical Interconnects in 0.13-μm SiGe BiCMOS

ABSTRACTA low-jitter full-rate 25-Gb/s clock and data recovery (CDR) chip for 100-Gb/s optical interconnects is proposed. Fabricated in 0.13-μm SiGe BiCMOS technology, the chip is implemented in a third-order type-II bang-bang phase-locked loop (BBPLL) topology. To achieve optimal switching speed, all SiGe heterojunction bipolar transistors (HBTs) in high-speed blocks are biased at peak fT current density. Transistors are sized by carefully balancing speed versus power consumption. Emitter-coupled logic (ECL) and current-mode logic (CML) are employed in logic components. Compared with conventional spiral inductors, the employment of RF transmission lines in resonators of the VCO reduces the area of the VCO and, thus, the whole chip, without sacrificing the performance. The core circuits occupy an area of 0.48 mm2. The CDR recovers a clock with an rms jitter of 750 fs and a peak-to-peak jitter only of 3.46 ps.

Weak and Dynamic GNSS Signal Tracking Strategies for Flight Missions in the Space Service Volume.

Weak-signal and high-dynamics are of two primary concerns of space navigation using GNSS (Global Navigation Satellite System) in the space service volume (SSV). The paper firstly defines a reference assumption third-order phase-locked loop (PLL) as the baseline of an onboard GNSS receiver, and proves the incompetence of this conventional architecture. Then an adaptive four-state Kalman filter (KF)-based algorithm is introduced to realize the optimization of loop noise bandwidth, which can adaptively regulate its filter gain according to the received signal power and line-of-sight (LOS) dynamics. To overcome the matter of losing lock in weak-signal and high-dynamic environments, an open loop tracking strategy aided by an inertial navigation system (INS) is recommended, and the traditional maximum likelihood estimation (MLE) method is modified in a non-coherent way by reconstructing the likelihood cost function. Furthermore, a typical mission with combined orbital maneuvering and non-maneuvering arcs is taken as a destination object to test the two proposed strategies. Finally, the experiment based on computer simulation identifies the effectiveness of an adaptive four-state KF-based strategy under non-maneuvering conditions and the virtue of INS-assisted methods under maneuvering conditions.

Hopf bifurcation and chaos in a third-order phase-locked loop

Phase-locked loops (PLLs) are devices able to recover time signals in several engineering applications. The literature regarding their dynamical behavior is vast, specifically considering that the process of synchronization between the input signal, coming from a remote source, and the PLL local oscillation is robust. For high-frequency applications it is usual to increase the PLL order by increasing the order of the internal filter, for guarantying good transient responses; however local parameter variations imply structural instability, thus provoking a Hopf bifurcation and a route to chaos for the phase error. Here, one usual architecture for a third-order PLL is studied and a range of permitted parameters is derived, providing a rule of thumb for designers. Out of this range, a Hopf bifurcation appears and, by increasing parameters, the periodic solution originated by the Hopf bifurcation degenerates into a chaotic attractor, therefore, preventing synchronization.

A low-jitter third-order self-biased PLL with adaptive fast-locking scheme for SerDes interfaces

This paper presents a 3rd-order self-biased phase-locked loop (PLL) with adaptive fast-locking scheme for serialize/deserialize (SerDes) interfaces. In order to obtain short and almost equal power-up latency in a wide range of reference frequencies, a fast-locking circuit block including 2 switched-capacitor frequency-to-voltage (F---V) converters and an adaptive discharger is proposed to speed up the power-up process. Additionally, the current in the charge pump (CP) of the traditional self-biased PLL tends to be influenced by the kick-back noise from the voltage-controlled oscillator (VCO). In order to reduce the jitter resulted from the VCO kick-back noise, an additional bias generator is inserted between the original bias generator and the VCO to isolate the bias signals for the CP and the VCO. The simulated clock jitter under 100-mV, 1-MHz supply noise is 27 ps at an output frequency of 2 GHz, which is much lower than that of the traditional counterpart. The presented PLL is integrated in a SerDes interface chip fabricated in a 0.25-μm standard CMOS technology. Measurement results show that the presented PLL achieves a power-up latency of 4---6.5 μs in the output frequency range of 200 MHz---2 GHz, and the peak-to-peak data jitter of the SerDes chip is 110 ps at a data rate of 2.5 Gbps. The presented PLL consumes 217 mW under a 2.5-V power supply, and the block area is 350 × 600 μm2.

An Autonomous Satellite Time Synchronization System Using Remotely Disciplined VC-OCXOs

An autonomous remote clock control system is proposed to provide time synchronization and frequency syntonization for satellite to satellite or ground to satellite time transfer, with the system comprising on-board voltage controlled oven controlled crystal oscillators (VC-OCXOs) that are disciplined to a remote master atomic clock or oscillator. The synchronization loop aims to provide autonomous operation over extended periods, be widely applicable to a variety of scenarios and robust. A new architecture comprising the use of frequency division duplex (FDD), synchronous time division (STDD) duplex and code division multiple access (CDMA) with a centralized topology is employed. This new design utilizes dual one-way ranging methods to precisely measure the clock error, adopts least square (LS) methods to predict the clock error and employs a third-order phase lock loop (PLL) to generate the voltage control signal. A general functional model for this system is proposed and the error sources and delays that affect the time synchronization are discussed. Related algorithms for estimating and correcting these errors are also proposed. The performance of the proposed system is simulated and guidance for selecting the clock is provided.

Performance analysis of a federated ultra-tight global positioning system/inertial navigation system integration algorithm in high dynamic environments

The Doppler frequency changes rapidly due to high dynamics of vehicle, which leads to the loose lock and even the abnormal performance of global positioning system (GPS) receiver. To solve this problem, a federated ultra-tight integration algorithm based on pre-filters is proposed to optimal estimate both receiver tracking control commands and inertial navigation system (INS) navigation solutions. Firstly, the INS error model and GPS receiver tracking loop structure are built to present the fundamental architecture of the proposed ultra-tightly coupled system. Meanwhile, in order to reduce the load of the integrated filter, the pre-filters are incorporated to the ultra-tightly coupled system, and the state variables are fed into the integrated Kalman filter. Secondly, the intrinsic relevance between the phase and frequency biases of replica signals and INS states is analyzed to accomplish the deep fusion of INS and tracking loop. Finally, semi-physical simulations are performed by using a GPS signal simulator to generate signals of two high dynamic trajectories. The experimental results indicate that the proposed ultra-tight integration algorithm can achieve a good performance on reliable positioning and robust tracking in high dynamic environments, compared with the conventional approaches such as tightly coupled integration strategy and third-order phase-locked loops.

Designing All-Pole Filters for High-Frequency Phase-Locked Loops

Since the phase-locked loop (PLL) circuit was proposed in the 1930s, it is being used for a lot of situations when precise frequency and phase references are required. Among these applications, synchronous telecommunication networks experienced a strong development in order to support the explosive information traffic that the modern society demands. Consequently, bandwidth became a decisive parameter, implying higher and higher frequencies for the clock signals exchanged between the nodes of the networks and detected by PLLs. The necessity to improve clock precision that follows the bandwidth increase provoked the improvement of the filter component of the PLLs, avoiding instability and high-frequency components in the reference signals. Here, a technique of designing this kind of filter is presented, considering second-order filters, implying third-order PLLs. Simulations show that following this technique produces very fast tracking processes, enabling precise operation even for very high frequencies.

Stability analysis of GPS carrier tracking loops by phase margin approach

Stability, which is significantly related to the loop parameters, is an important factor in the traditional GPS tracking loop design. Through the analysis of phase margin values in the discrete GPS PLL tacking loop, we are able to theoretically reveal the relationship between loop stability, equivalent noise bandwidth B n , predetection integration time T, and loop parameters. We calculate the theoretical limitations for B n T, that is, the product of equivalent noise bandwidth multiplied by predetection integration time, for second- and third-order phase-locked loop, respectively. The results are verified by actual data from GPS receivers.