Abstract
Since the phase-locked loop (PLL) circuit was proposed in the 1930s, it is being used for a lot of situations when precise frequency and phase references are required. Among these applications, synchronous telecommunication networks experienced a strong development in order to support the explosive information traffic that the modern society demands. Consequently, bandwidth became a decisive parameter, implying higher and higher frequencies for the clock signals exchanged between the nodes of the networks and detected by PLLs. The necessity to improve clock precision that follows the bandwidth increase provoked the improvement of the filter component of the PLLs, avoiding instability and high-frequency components in the reference signals. Here, a technique of designing this kind of filter is presented, considering second-order filters, implying third-order PLLs. Simulations show that following this technique produces very fast tracking processes, enabling precise operation even for very high frequencies.
Highlights
Phase-locked loop (PLL) was conceived by de Bellescize in 1932 [1] and has been used to generate frequency and phase signals for several types of applications such as demodulation, digital signal transmission, and clock recovering in synchronous networks
The double-frequency jitter, which is less critical in the digital versions of phase and frequency detectors, becomes more significant with the development of high speed optical networks and master oscillation drifts spoil the synchronous state reachability [7, 9]
It was shown that, starting with normalized forms of the loop transfer functions, parameters defining the limits of instability for the PLLs can be calculated, permitting one to obtain transfer functions free of or with acceptable overshoots
Summary
Phase-locked loop (PLL) was conceived by de Bellescize in 1932 [1] and has been used to generate frequency and phase signals for several types of applications such as demodulation, digital signal transmission, and clock recovering in synchronous networks. In the last thirty years, digital electronics revolution produced high speed integrated service networks based on master-slave time distribution systems with very precise central clocks sending signals to slave nodes that, by using cheap and precise PLLs, reconstruct the necessary time basis [2] Along this time, the implementation of circuits to execute the PLL functions evolved from analog to digital circuits and even software PLLs are used in engineering applications [1], including synchronous communication networks. The double-frequency jitter, which is less critical in the digital versions of phase and frequency detectors, becomes more significant with the development of high speed optical networks and master oscillation drifts spoil the synchronous state reachability [7, 9] To solve this problem, one can use high-order filters in the PLL, increasing the order of the whole loop, but providing adequate high-frequency operation.
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