Thin-profile Fine-pitch Ball Grid Array Research Articles

Reliability of SAC 105 and SAC1205N under Drop Tests

Abstract In this paper, the solder joint failure and the solder joint fatigue life in the Thin-profile Fine-pitch Ball Grid Array (TFBGA) Package was investigated by performing the drop test, and implementing a simulation model. Owing to the need to meet the increasing demands for functionality, microelectronic package reliability can be compromised and has become the key issue when executing drop tests. During impact in drop test, the deformation of PCB due to bending and mechanical shocks can cause solder joint crack. While this is a well-known issue, observing the solder joint responses during the test execution can be a challenge. Therefore, in this work, a simulation model approach has been developed to investigate the stress and strain of the solder joint during the drop test. In this research, the JEDEC Condition B drop test was simulated, characterized by 1500G peak acceleration and 0.5 ms duration. The drop test simulation model was successful in predicting the solder joint fatigue life with different solder joint materials, such as SAC105 and SAC1205N, while also facilitating result comparison to identify the most optimal structure.

Characteristics of a System in a Package with Silver Wires

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.

Thermal Cycle Consideration in Applying Lead-Free TFBGA Simulation to a Design

Three-dimensional (3D) stacked die packaging has become the trend to improve efficiency for transmitting signals, reduce the volume of the package, and help with functions integration. It is more and more applied popularly in telecommunications. Solder joints, interconnections in the packaging structure, are more easily damaged by critical stress from thermal cycle loading when the component is operating, because the coefficient of the thermal expansion of various materials mismatch. People have studied the common single die during the thermal cycle loading for a long time, but the researches for the stacked die BGA are not as complete. In addition, to protect the environment and comply with legislation, the semiconductor industry wants to find a lead-free material to replace the lead solder joints. Therefore, most extant or new types of packaging started using lead-free material to do thermal cycle testing. The critical solder ball location is not the same as in a single die package where at the die corner, due to it is influenced by stacked die with different geometry, the difference in dice length helps to redistribute the die stress. In this paper, we used FEA software, ANSYS, to build up a 3D thin-profile, fine-pitch, ball grid array (TFBGA) model. The modeling investigated the effect on solder joints under thermal cycle and included deformation, von-Mises stress and strain energy density (SED). Then we utilized Darveaux's approach, which is a common methodology used to calculate the fatigue life based on energy and damage accumulation theories, to predict the fatigue life of the critical solder joint and modify our model with the theory. We changed various kinds of SAC solder joints with different ratios of the components and Anand's constants, analyze the divergence and compared them with the lead solder material. We develop a model to forecast the failure phenomenon and fatigue damage on an electronic package. This would help engineers and designers raise the reliability of the package. In addition, we hope to find a lead-free material that can be substituted for the lead solder material. If this is the case, based on simulating results, we hope to improve it and have much a better reliability performance than the original lead solder.

Effect of the combination of surface finishes and solder balls on JEDEC drop reliability of chip-scale packages

► This study looks at ENEPIG, as it is paired with three solder compositions. ► Board-level chip-scale packages subjected to a JEDEC drop test. ► Sb, Ni and Pt were minor doped for enhancing strength and good wettability. ► The drop performances of ENEPIG are found better than those of Ni/Au. ► Most of the failure modes are on the test board side along the brittle interfaces. Cost reduction pressure has been amplified by the escalation of the price of gold. Reducing gold thickness is the only alternative in the hedge against such escalation but may compromise bondability and reliability. In order for a molten bond to exist between two metallic materials, the formulation of IMCs is inevitable. A bond too thick or too thin could harm the interface bondability or gold embrittlement respectively. In order to protect against such harm, the surface finish and solder must be considered. This study, therefore, looks at ENEPIG, a gold-reduction surface finish, as it is paired with three solder compositions: SAC125Sb, SAC125NiSb, and SAC105Pt. This investigation pairs these three components on board-level thin-profile fine-pitch ball grid array chip-scale packages and tests them with an industrial standard electroplated Ni/Au. Test performance is examined by a JEDEC drop reliability test.

Optimal design of thin-profile fine-pitch ball grid array package under drop impact test

This article describes the board-level drop reliability of thin-profile fine-pitch ball grid array (TFBGA) subjected to Joint Electron Device Engineering Council (JEDEC) drop test conditions featuring an impact pulse profile with a peak acceleration of 1500 G and a pulse duration of 0.5 ms. The solder ball is assumed to be an elastoplastic model and the other components linear elastic ones. Both the global/local finite element and the finite grid region methods are introduced to improve the accuracy and the convergence during the meshing process. Meanwhile, the contact impact process during the drop test is translated into the effective support excitation load on the printed circuit board (PCB) through the support excitation scheme to simplify the analysis. By means of optimal parameters of the Taguchi robust design, the average stress of the solder ball at the PCB side surface becomes 80.9 MPa, which shows a 57 per cent reduction compared to the original stress of 189.7 MPa. As a result, the impact reliability of the TFBGA package is significantly improved. Finally, the JEDEC drop test is conducted to verify the optimal results obtained by the Taguchi method.

Influence of Power Cycling Durations on Thermal and Fatigue Reliability Characteristics of Board-Level Chip-Scale Packages

The sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, was performed in this work to investigate thermal characteristics along with fatigue reliability of a thin-profile fine-pitch ball grid array chip-scale package subjected to power cycling. The numerical model was calibrated using steady-state and power cycling experiments. Following the calibrated numerical model, different power cycling durations on the thermal characteristics and fatigue reliability of the solder joints were examined. Numerical results indicate that, compared with thermal cycling, power cycling requires many more cycles to achieve a stabilized plasticity index between test cycles. The fatigue reliability would therefore be greatly underestimated if only such an index of the first several cycles is followed in the predictions.

Reliability evaluations for board-level chip-scale packages under coupled power and thermal cycling test conditions

To evaluate conjointly the effects of ambient temperature fluctuation and operation bias on the reliability of board-level electronic packages, a coupled power and thermal cycling test has been proposed. In this study, the sequential thermal–mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is performed to investigate thermal characteristics along with fatigue reliability of board-level thin-profile fine-pitch ball grid array chip-scale packages under coupled power and thermal cycling test conditions. Effects of different power cycling durations are studied. A pure thermal cycling condition is also examined and compared. Numerical results indicate that, for the coupled power and thermal cycling test, a shorter power cycling duration in general leads to a shorter fatigue life. However, the temperature compensation effect elongates the fatigue life under certain power cycling durations.

Board-Level Solder Joint Reliability Analysis of Thermally Enhanced BGAs and LGAs

Thermally enhanced ball grid arrays (BGAs) are designed to have reduced thermal resistance through features such as heat slug, heat spreader, and thermal solder joints. This paper studies the design comparison of five types of thermally enhanced BGAs, i.e., conduction cooled BGA (C/sup 2/BGA), metal-core BGA, exposed-die land grid array (LGA), slug LGA, and spreader LGA. The solder joint reliability performance of thermally enhanced BGAs is benchmarked with conventional thin-profile fine-pitch ball grid array (TFBGA). Both global and local three-dimensional finite-element analysis (FEA) models are established to predict the fatigue life of solder joints during thermal cycle testing. Detailed pad design with realistic geometry of solder balls and nonlinear material properties are considered in the model. The fatigue model is based on a modified Darveaux's approach with nonlinear viscoplastic analysis of solder joints. For the test vehicles studied, the critical solder joints are located near the package corner. Design variations investigated include the effects of key package dimensions and material properties. Design variations are mainly reported using C/sup 2/BGA package as the trend for the other four thermally enhanced BGAs was similar. The choice of mold compound (MC) material is critical, and a material with higher coefficient of thermal expansion (CTE/sub 1/) and lower modulus is preferred. Die size, die attach, and slug-attach material have little effect on solder joint reliability. It is observed that there is good correlation of fatigue life between modeling prediction and thermal cycle testing for C/sup 2/BGA. Reliability of C/sup 2/BGA thermal solder joints is proven to be excellent, and heat can be effectively conducted away from the die to the PCB. This is crucial to the design of C/sup 2/BGA. In addition, solder joint fatigue life is found to be related to package warpage induced during thermal cycling test. A design with less package warpage usually has a longer fatigue life.

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.

Board level solder joint reliability analysis and optimization of pyramidal stacked die BGA packages

Due to requirements of cost-saving and miniaturization, stacked die BGA has recently gained popularity in many applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of wirebond stacked die BGA is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux's approach with non-linear viscoplastic analysis of solder joints. The critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house TFBGA (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyses are performed to study the effects of 16 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, smaller top and bottom dice sizes, thicker top or bottom die, thinner PCB, thicker substrate, higher solder ball standoff, larger solder mask opening size, smaller maximum ball diameter, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. The effect of number of layers of stacked-die is also investigated. Finally, design optimization is performed based on selected critical design variables.

Impact life prediction modeling of TFBGA packages under board level drop test

Reliability performance of IC packages during drop impact is critical, especially for handheld electronic products. Currently, there is no model that provides good correlation with experimental measurements of acceleration and impact life. In this paper, detailed drop tests and simulations are performed on TFBGA (thin-profile fine-pitch BGA) and VFBGA (very-thin-profile fine-pitch BGA) packages at board level using testing procedures developed in-house. The packages are susceptible to solder joint failures, induced by a combination of PCB bending and mechanical shock during impact. The critical solder ball is observed to occur at the outermost corner solder joint, and fails along the solder and PCB pad interface. Various testing parameters are studied experimentally and analytically, to understand the effects of drop height, drop orientation, number of PCB mounting screws to fixture, position of component on board, PCB bending, solder material, etc. Drop height, felt thickness, and contact conditions are used to fine-tune the shape and level of shock pulse required. Board level drop test can be better controlled, compared with system or product level test such as impact of mobile phone, which sometimes has rather unpredictable results due to higher complexity and variations in drop orientation. At the same time, dynamic simulation is performed to compare with experimental results. The model established has close values of peak acceleration and impact duration as measured in actual drop test. The failure mode and critical solder ball location predicted by modeling correlate well with testing. For the first time, an accurate life prediction model is proposed for board level drop test to estimate the number of drops to failure for a package. For the correlation cases studied, the maximum normal peeling stresses of critical solder joints correlate well with the mean impact lives measured during the drop test. The uncertainty of impact life prediction is within ±4 drops, for a typical test of 50 drops. With this new model, a failure-free state can be determined, and drop test performance of new package design can be quantified, and further enhanced through modeling. This quantitative approach is different from traditional qualitative modeling, as it provides both accurate relative and absolute impact life prediction. The relative performance of package may be different under board level drop test and thermal cycling test. Different design guidelines should be considered, depending on application and area of concern.

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.