Si and SiGe epitaxy via UHVCVD requires an extremely clean and oxide free substrate but has the advantage of allowing low temperature epitaxy (LTE). In-situ bake-off of thin native oxides is possible at high temperatures, but is not an option for low temperature epitaxy. As a result, LTE processes are sensitive to surface preparation and the duration between oxide removal and epitaxy growth. Traditional techniques for observing interfacial contamination, such as secondary ion mass spectroscopy, are not easily integrated into a fabrication line. In addition, the off-line measurements of monitor wafers cannot detect contamination soon enough before the product wafers have gone through extensive further processing. A new monitor has been developed and demonstrated for observing the contamination of the substrate and process that occurs after the pre-epitaxy cleaning steps. This novel monitor used an ion implanted substrate along with defect etches. The sensitivity of this monitor can be controlled by adjusting the implant dose allowing tailoring to specific process targets and needs. A dilute Secco wet etch and HCl chemical vapor etch were both demonstrated for decorating the dislocation defects caused by interfacial contaminants. Using TEM, these defects were confirmed as originating from the substrate-epitaxy interface. In-line and off-line defect counting systems were then used to quantify the defect density of the novel monitor. These monitors were shown to have sensitivity to defects caused by range of interfacial contaminants. The result of this newly integrated method is a fully line integrated defect monitor using already commonplace equipment and chemicals, that has a rapid turnaround, and that is broadly sensitive to substrate surface contaminants.