Thin N-type Layer Research Articles

Low Temperature Phosphorus Doping in Silicon Using Catalytically Generated Radicals

In this paper, we report the possibility of forming a phosphorus (P)-doped layer on silicon (Si) at low temperatures. Using the radicals catalytically generated from phosphine (PH3), a thin n-type layer is formed on a crystalline Si (c-Si) wafer at 150 °C. The secondary ion mass spectrometry (SIMS) profile of doped P atoms indicates that P atoms exist in the vicinity of the c-Si surface, and the depth at which P atom concentration decreases to 1/10 of the surface concentration is less than 12 nm for 300 s of radical treatment. The sheet carrier density on radical-treated c-Si wafers measured using the Hall effect shows that P atoms act as donors without annealing. The sheet carrier concentration of the P-doped layer is increased by adding hydrogen (H2) to the PH3 source gas. The effect of adding H2 to PH3 suggests that the surface reaction of atomic H plays an important role in the doping process.

Enhanced hole transport from Au to Zn-phthalocyanine by an insertion of a thin n-type layer

A thin C60 or bathocuproine (BCP) layer of 5 nm thickness is inserted to the Au/Zn-phthalocyanine (ZnPc) interface of a Au/ZnPc/In/Al Schottky-junction cell, and the effect of the insertion on the dark current is investigated. The forward dark current density is increased from 0.5mA∕cm2 to 9.7 and 9.2mA∕cm2 by the insertions of the C60 and BCP layers, respectively. The increase is not attributed to a change in the barrier height for the hole injection, but to a decrease of the concentration of trapped negative charges on the ZnPc surface.

Silver diffusion in p‐type CdTe and (CdZn)Te near room temperature

Silver diffusion in undoped p-Cd1−xZnxTe (x = 0; 0.04) from an AgNO3 aqueous solution or evaporated Ag surface layer close to room temperature (RT) is investigated. We show that thin n-type layer with thickness up to 30 μm, which is stable at RT, is created near the surface. The annealing at slightly increased temperature (60–100 °C) results in a temperature activated propagation of the p-n junction, which also depends on the biasing. The decreasing of hole density in the p+-type bulk during aging at RT proves that fast Ag diffusion occurs at RT. Additionally an electro-migration of Ag was observed at 60 °C. (© 2004 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Pseudo-SOI: p-n-p channel-doped bulk MOSFET for low-voltage high-speed applications

A pseudo-silicon-on-insulator (P-SOI) MOSFET fabricated using a bulk substrate has been developed for high device performance, comparable to those of a fully depleted (FD) SOI MOSFET, without problems caused by the usage of an SOI substrate. It features a p-n-p channel profile, in which a sandwiched thin n-type layer is fully depleted by the internal built-in potential. The thin n-type layer expands the depletion layer in the inversion state and reduces the vertical electric field at the MOS interface. As a result, the P-SOI MOSFET has a high drain-current drivability, a small subthreshold swing, and a low substrate-bias coefficient. A TiN gate electrode, which has a near midgap work function, is used to achieve optimum threshold voltage. It also increases the drain current by reducing the gate-electrode depletion. Counter doping to the buried p-type layer below the source and drain reduces junction capacitances. The subthreshold swing of the fabricated 0.25-/spl mu/m-gate-length P-SOI MOSFET becomes 73 mV/decade. Its drain current is 25% higher, substrate-bias coefficient is 40% lower, and source/drain junction capacitance is 60% lower, than those of a control MOSFET.

Rapid thermal annealing of Mg + and P + dually implanted InP

125 keV M + ions and 160 keV P + ions were implanted at RT, 100° C and 200° C with doses ranging from 1 × 10 14 to 1 × 10 15 cm −2 to study the effect of the dual implantations on the electrical properties of Fe doped InP. The samples were characterized by electrochemical C- V measurement and RBS-channelling techniques. It has been found that Mg + + P + dual implantations into InP can result in an enhanced activation of implanted dopants. The highest peak hole concentration and dopant activation obtained in this work were 1.1 × 10 19 cm −3 and 68% in the case of Mg + + P + dual implantations at a dose of 1 × 10 15 cm −2 while that for Mg + single implantation at the same dose were 5.4 ×10 18 cm −3 and 40%. A thin n-type layer was found in the carrier concentration profile of Mg + singly implanted samples whereas there was not such a layer in that of Mg + + P + dually implanted ones. RBS spectra showed that the implantation at 100° C leads to damage similar to that in the sample implanted at 200° C. A deep penetration of Mg into InP during annealing, which is supposed to be related to the (Mg,Fe) complex, can be suppressed to some extent by P + co-implantation.

Recoil implantation of Si into GaAs by as ion bombardment

Vacuum deposited Si on GaAs structures with Si film thicknesses of 950 and 1200 A were bombarded with As ions. As bombarding energy ranged between 150 and 280 keV, and the dose was 1 × 10 15 /cm 2 . Thermal annealing was carried out at 850° C for 15 min in N 2 utilizing the Si layer as an annealing cap. The surface Si layer was stripped in an organic etchant. Hall measurements with successive stripping revealed that a thin n-type layer with a maximum carrier concentration of 4 x 10 18 /cm 3 was created by recoil implantation. The results were compared with Monte Carlo computer simulation. The difference between carrier and atomic distribution obtained from SIMS was discussed.

DC analysis and design of the majority carrier accumulation MOSFET

Abstract A novel MOSFET device structure is proposed that operates on the principle of majority carrier accumulation in the channel. For an n-channel device, the structure consists of a thin n-type layer on a p-type substrate. By appropriate choice of the n-layer thickness and the donor and acceptor concentrations the n-layer can be completely depleted due to the built-in junction potential or if necessary by applying a suitable substrate bias. The DC current-voltage characteristics are calculated using the depletion approximation.