Thin-film Transistor Process Research Articles

Flexible x-ray imaging detector based on direct conversion in amorphous selenium

In this paper, the authors propose a mechanically flexible direct conversion x-ray detector as a potential solution for portable and conformal digital x-ray imaging. It consists of a micropillar structured layer of 100-μm-thick amorphous selenium (a-Se) on a flexible thin film transistor (TFT) backplane with a pixel size of 70 μm as a substrate. The flexible substrate is made of an optically transparent polyimide with a heat resistance of more than 200 °C. It is bonded on a glass carrier for rigid substrate handling during the amorphous silicon (a-Si) TFT process. Separating the flexible substrate from the glass carrier is partly facilitated by a debonding layer sandwiched between them. A two-dimensional electrical simulation analysis revealed a possible charge generation and collection mechanism within the micropillared a-Se layer. An x-ray image captured by the curved flexible detector indicated that a pillarlike a-Se conversion layer can be used to perform x-ray imaging. This is, to the best of our knowledge, the first demonstration of a flexible digital x-ray direct conversion detector.

TFT‐based, multi‐stage, active pixel sensor for alpha particle detection

A multi-stage thin film transistor (TFT)-based active pixel sensor (APS), capable of successfully detecting small impulses of charge resulting from incident alpha particle strikes, is presented. Detection of alpha particles is important in the field of neutron detection, where fully integrated thin-film-based detectors are an attractive alternative to conventional 3He-based proportional counters owing to their low-cost and large-area scaling capability, combined with the use of readily available materials. A typical TFT process, however, produces only N-type devices with low electron mobilities – making high-gain CMOS amplifier designs unfeasible. The disadvantages of using a TFT-only APS design are mitigated by cascading multiple low-gain TFT amplifiers, which results in a higher overall pixel gain – subsequently allowing for the successful detection and readout of alpha particle strikes. Presented is a new APS fabricated in an indium gallium zinc oxide TFT process is presented, and successful initial alpha response measurements are reported.

Study of Novel Floating-Gate Oxide Semiconductor Memory Using Indium–Gallium–Zinc Oxide for Low-Power System-on-Panel Applications

A novel floating-gate oxide semiconductor (FLOTOS) memory using a wide-band-gap indium–gallium–zinc oxide (IGZO) is presented for low-power system-on-panel applications. An IGZO thin-film-transistor (TFT) is used as a memory transistor for controlling read current as well as a switching transistor for storing charges in a storage capacitor (Cs). The FLOTOS memory is fabricated using a standard IGZO TFT process without any additional process or mask steps. The proposed precharge-assisted threshold voltage compensation technique makes it possible to realize an infinite number of write cycles and a low-power write operation with a bit-line voltage of 5 V. Furthermore, excellent data retention longer than 10 h is obtained at 60 °C even under the worst bias-stress condition of read operation with the ultra low off-state leakage (2.8×10-20 A/µm) of the IGZO TFTs, which is estimated to be smaller by more than 7 orders of magnitude than that of polycrystalline silicon TFTs.

Amorphous Silicon Thin Film Transistor Biosensing System

ABSTRACTElectronic systems are a very good platform for sensing biological signals for fast point-of-care diagnostics or threat detection. One of the solutions is the lab-on-a-chip integrated circuit (IC), which is low cost and high reliability, offering the possibility for label-free detection. In recent years, similar integrated biosensors based on the conventional complementary metal oxide semiconductor (CMOS) technology have been reported. However, post-fabrication processes are essential for all classes of CMOS biochips, requiring biocompatible electrode deposition and circuit encapsulation.In this work, we present an amorphous silicon (a-Si) thin film transistor (TFT) array based sensing approach, which greatly simplifies the fabrication procedures and even decreases the cost of the biosensor. The device contains several identical sensor pixels with amplifiers to boost the sensitivity. Ring oscillator and logic circuits are also integrated to achieve different measurement methodologies, including electro-analytical methods such as amperometric and cyclic voltammetric modes. The system also supports different operational modes. For example, depending on the required detection arrangement, a sample droplet could be placed on the sensing pads or the device could be immersed into the sample solution for real time in-situ measurement. The entire system is designed and fabricated using a low temperature TFT process that is compatible to plastic substrates. No additional processing is required prior to biological measurement. A Cr/Au double layer is used for the biological-electronic interface. The success of the TFT-based system used in this work will open new avenues for flexible label-free or low-cost disposable biosensors.

Facilitation of the four-mask process by the double-layered Ti/Si barrier metal for oxide semiconductor TFTs

The double-layered Ti/Si barrier metal is demonstrated for the source/drain Cu interconnections in oxide semiconductor thin-film transistors (TFTs). The transmission electromicroscopy and ion mass spectroscopy analyses revealed that the double-layered barrier structure suppresses the interfacial reaction and the interdiffusion at the interface after thermal annealing at 350°C. The underlying Si layer was found to be very useful for the etch stopper during wet etching for the Cu/Ti layers. The oxide TFTs with a double-layered Ti/Si barrier metal possess excellent TFT characteristics. It is concluded that the present barrier structure facilitates the back-channel-etch-type TFT process in the mass production line, where the four- or five-mask process is used.

Nickel Nanocrystals Embedded in Metal–Alumina–Nitride–Oxide–Silicon Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor for Low-Voltage Nonvolatile Memory Application

In this work, a nickel nanocrystal (Ni-NC) assisted metal–alumina–nitride–oxide–silicon (MANOS) thin-film transistor (TFT) nonvolatile memory (NVM) was fabricated by a standard low temperature polycrystalline silicon (LTPS) TFT process. The size range and density of Ni-NCs were approximately 5–13 nm and 5 ×1011 cm-2, respectively. The programming/erasing (P/E) voltages are decreased down to -10 and +8 V, respectively, by the Fowler–Nordheim tunneling mechanism from gate injection. In this P/E voltage condition, a large memory window (∼4.2 V) was observed by current–voltage measurement. Then, the speed and voltages of P/E were measured and discussed completely. The data retention of the Ni-NC assisted MANOS-LTPS-TFT-NVM is extracted to be 1.62 V of memory window after 104 s.

Stability of IZO and a-Si:H TFTs Processed at Low Temperature (200 $^{\circ}{\hbox{C}}$)

Mixed-oxide thin-film transistors (TFTs) have been extensively researched due to their improved stability under electrical bias stress compared to amorphous-silicon TFTs. However, there are many challenges before they can reach the manufacturing stage. At the Flexible Display Center (FDC), Arizona State University, Tempe, we are developing a low temperature indium-zinc-oxide (IZO) TFT process suitable for flexible substrates such as polyethylene naphthalate (PEN). We report the effect of bias stress on the performance of these IZO TFTs and compare it with a-Si:H TFTs. We also report the design and fabrication of a 3.8-in QVGA electrophoretic display on PEN substrate using IZO TFT backplane.

Development of Liquid Crystal Display Panel Integrated with Drivers Using Amorphous In–Ga–Zn-Oxide Thin Film Transistors

We designed, prototyped, and evaluated a liquid crystal panel integrated with a gate driver and a source driver using amorphous In–Ga–Zn-oxide thin film transistors (TFTs). Using bottom-gate bottom-contact (BGBC) thin film transistors, superior characteristics could be obtained. We obtained TFT characteristics with little variation even when the thickness of the gate insulator (GI) film was reduced owing to etching of source/drain (S/D) wiring, which is a typical process for the BGBC TFT. Moreover, a favorable ON-state current was obtained even when an In–Ga–Zn-oxide layer was formed over the S/D electrode. Since the upper portion of the In–Ga–Zn-oxide layer is not etched, the BGBC structure is predicted to be effective in thinning the In–Ga–Zn-oxide layer in the future. Upon evaluation, we found that the prototyped liquid crystal panel integrated with the gate and source drivers using the TFTs with improved characteristics had stable drive.

Polysilicon Channel TFT With Separated Double-Gate for Unified RAM (URAM)—Unified Function for Nonvolatile SONOS Flash and High-Speed Capacitorless 1T-DRAM

Unified random access memory (URAM) with a separated double-gate is demonstrated on a fully depleted polysilicon (poly-Si) thin-film-transistor (TFT) template. Integration of a front-gate dielectric of tunneling oxide/nitride/control oxide (O/N/O) and a floating poly-Si channel provides the two versatile functions of nonvolatile silicon oxide-nitride oxide-semiconductor Flash memory and high-speed capacitorless single-transistor 1T-DRAM in a single transistor. In this design, the memory mode of URAM is selected according to user specifications. As the back-channel is assigned for capacitorless 1T-DRAM while the front-channel is devoted for Flash memory, spatial separation minimizes undesired soft programming in the front O/N/O layer and allows for capacitorless 1T-DRAM operation irrespective of the data state of the nonvolatile memory. This feature presents interference-free operation between the two modes. In addition, the virtue of the TFT process allows the potential for stackable memory for ultra-high-density era.

A Driving Scheme for Active-Matrix Organic Light-Emitting Diode Displays Based on Current Feedback

This paper presents a method of driving active-matrix organic light-emitting diode (AMOLED) displays with amorphous silicon (a-Si) thin-film transistors (TFTs). By using current feedback, the method effectively compensates for the effect of shift in the threshold voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) of a-Si TFTs on the OLED current. A CMOS transresistance amplifier is used as the column driver to cancel the effect of large parasitic capacitance of data lines. An accelerating pulse is used at the start of the programming cycle to improve the settling at low currents. A detailed analysis has been done to investigate the effect of circuit components on the sensitivity of the OLED current to <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shift and the settling behavior of the circuit. Prototypes of pixel circuits and the transresistance amplifier were fabricated in an a-Si TFT process and a 0.8- mum 20-V CMOS technology, respectively. Measurements show less than 5% change in the OLED current for 2.5-V shift in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of TFTs. Settling times smaller than 50 mus were achieved for parasitic capacitances of 50-200 pF and programming currents as small as 200 nA.

33.3: A 14.1‐Inch WXGA+ LCD Panel Using Hybrid Silicon Thin Film Transistors

AbstractA hybrid silicon technology (HyST) thin film transistor (TFT) process using a diode‐pumped solid state (DPSS) laser has been developed by implementing low‐temperature poly‐Si (LTPS) TFTs with a‐Si:H TFTs on the same substrate. HyST TFTs are deployed on the peripheral area of a panel for integrated gate driver circuits and a‐Si:H TFTs are used as switching devices for pixels in the active display area. This technology is based on the current a‐Si:H TFT fabrication processes without additional ion‐doping and activation processes. Field effect mobilities of 4 ∼ 5 cm2/V⋅s and 0.5 cm2/V⋅s for HyST and a‐Si:H TFTs, respectively, are obtained. Low power consumption, high speed, small integration area, high reliability, and low photosensitivity are achieved by means of HyST TFTs, compared to gate driving circuits integrated with a‐Si:H TFTs. A 14.1‐inch WXGA+ (1440×900) LCD panel has been demonstrated using the new HyST TFT process.

A Novel Amorphous InGaZnO Thin Film Transistor Structure without Source/Drain Layer Deposition

In this paper, new structured amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) without conventional source/drain (S/D) layer deposition were introduced. The S/D layers were formed in a-IGZO channel layer by hydrogen (H2) plasma treatments. As the increased plasma treatment time, the resistivity of plasma treated a-IGZO as S/D decreased drastically from 104 to 4.8 ×10-3 Ω cm due to the carrier generation by plasma treatment for 240 s. The carrier concentration mechanism of the H2 plasma treated sample could be attributed to the preferential sputtering of oxygen by H2 bombardment due to formation of an oxygen vacancy and removal of adsorbed O2. The new proposed TFTs exhibited a field-effect mobility of 7.14 cm2 V-1 s-1, an on/off ratio of 7.95 ×106, a threshold voltage of 0.94 V, and a subthreshold swing of 1.06 V/decade. These results demonstrated the possibility of low cost TFT process because S/D electrode deposition was unnecessary.

Fabrication of Flexible TFTs on a Heat-Resistant Transparent Polymer using the Standard a-Si TFT Process above 300ºC

A method for fabricating thin-film transistors (TFTs) on flexible substrates using a spin-coated heat-resistant transparent polyimide analog polymer, polybenzoxazole (PBO), was developed. Since this material is heat-resistant up to 350ºC, it can withstand the conventional above-300ºC a-Si TFT process. With XeCl excimer laser exposure, the PBO layer with a-Si TFTs could be easily separated from the glass substrate without any damage to the TFTs.

38.3: All‐Digital Phase‐Locked Loop with Low‐Temperature Poly‐Silicon Thin Film Transistor for System‐on‐Glass

AbstractThis paper describes an all‐digital phase‐locked loop (ADPLL) for system‐on‐glass (SoG) with low‐temperature poly‐Silicon (LTPS) thin film transistor (TFT). Due to the large variations and mismatches of LTPS TFT, it is very difficult to implement an analog PLL on glass substrate and ADPLL is employed for the timing generation in SoG. The ADPLL is implemented with a 2μm LTPS TFT process technology and consists of 5‐bit delay‐line time‐to‐digital converter (TDC), 7‐bit digitally controlled oscillator (DCO) and digital integrator. with a 20MHz reference clock, the ADPLL is locked within 36 periods of reference clock and shows 930ps peak‐to‐peak jitter.

Thermally Processed High-Mobility MOS Thin-Film Transistors on Transferable Single-Crystal Elastically Strain-Sharing Si/SiGe/Si Nanomembranes

Demonstration of high-performance MOS thin-film transistors (TFTs) on elastically strain-sharing single-crystal Si/SiGe/Si nanomembranes (SiNMs) that are transferred to foreign substrates is reported. The transferable SiNMs are realized by first growing pseudomorphic SiGe and Si layers on silicon-on-insulator (SOI) substrates, and then, selectively removing the buried oxide (BOX) layer from the SOI. Before the release, only the SiGe layer is compressively strained. Upon release, part of the compressive strain in the SiGe layer is transferred to the thin Si layers, and the Si layers, thus, become tensile strained. Both the initial compressive strain state in the SiGe layer and the final strain sharing state between the SiGe and the Si layers are verified with X-ray diffraction measurements. The TFTs are fabricated employing the conventional high-temperature MOS process on the strain-shared SiNMs that are transferred to an oxidized Si substrate. The transferred strained-sharing SiNMs show outstanding thermal stability and can withstand the high-temperature TFT process on the new host substrate. The strained-channel TFTs fabricated on the new host substrate show high current drive capability and an average electron effective mobility of 270 cm2/V ldr s. The results suggest that transferable and thermally stable single-crystal elastically strain- sharing SiNMs can serve as excellent active material for high-speed device application with a simple and scalable transfer method. The demonstration of MOS TFTs on the transferable nanomembranes may create the opportunity for future high-speed Si CMOS heterogeneous integration on any substrate.

The characteristics of solid phase crystallized (SPC) polycrystalline silicon thin film transistors employing amorphous silicon process

We investigated the electrical properties of polycrystalline silicon (poly-Si) thin film transistors (TFTs) employing field-enhanced solid phase crystallization (FESPC). An n+ amorphous silicon (n+ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal instead of ion doping. By using C–V measurement method, we could explain the diffused phosphorous ions (P+ ions) on the channel surface caused a negatively shifted threshold voltage (VTH) of −7.81V at a drain bias of 0.1V, and stretched out a subthreshold swing (S) of 1.698V/dec. This process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process and also offers a better uniformity when compared to the conventional laser-crystallized poly-Si TFT process because of non-laser crystallization.

The Characteristics of New n-Type Polycrystalline Silicon Thin-Film Transistors Employing Alternating Magnetic-Field-Enhanced Rapid Thermal Annealing

We fabricated a new top-gate n-type depletion-mode polycrystalline silicon (poly-Si) thin-film transistor (TFT) employing alternating magnetic-field-enhanced rapid thermal annealing. An n+ amorphous silicon (n+ a-Si) layer was deposited to improve the contact resistance between the active Si and source/drain (S/D) metal. The proposed process was almost compatible with the widely used hydrogenated amorphous silicon (a-Si:H) TFT fabrication process. This new process offers better uniformity when compared to the conventional laser-crystallized poly-Si TFT process, because it involves nonlaser crystallization. The poly-Si TFT exhibited a threshold voltage (VTH) of -7.99 V at a drain bias of 0.1 V, a field-effect mobility of 7.14 cm2/V ldr s, a subthreshold swing (S) of 0.68 V/dec, and an ON/OFF current ratio of 107. The diffused phosphorous ions (P+ ions) in the channel reduced the VTH and increased the S value.

Electrical analysis of bottom gate TFT with novel process architecture

Bottom gate thin film transistors (TFTs) with microcrystalline and amorphous Si (a‐Si) double active layers (DAL) were fabricated. Since the process of DAL TFTs can use that of conventional a‐Si TFTs, these DAL TFT process has advantages, such as low cost, large substrate, and mass production capacity. In order to analyze the degradation characteristics in saturation region for driving TFTs of active matrix organic light emitting diode, three different dynamic stresses were applied to DAL TFTs and a‐Si TFTs. The threshold voltage shift of DAL TFTs and a‐Si TFTs during 10,000 second stress is 0.3V and 2V, respectively. DAL TFTs were more reliable than a‐Si TFTs.

Amorphous Silicon Display Backplanes on Plastic Substrates

Amorphous silicon (a-Si) thin-film transistor (TFT) backplanes are very promising for active-matrix organic light-emitting diode displays (AMOLEDs) on plastic. The technology benefits from a large manufacturing base, simple fabrication process, and low production cost. The concern lies in the instability of the TFTs threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> ) and its low device mobility. Although V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> -instability can be compensated by means of advanced multi-transistor pixel circuits, the lifetime of the display is still dependent on the TFT process quality and bias conditions. A-Si TFTs with field-effect mobility of 1.1 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /Vmiddots and pixel driver circuits have been fabricated on plastic substrates at 150 degC. The circuits are characterized in terms of current drive capability and long-term stability of operation. The results demonstrate sufficient and stable current delivery and the ability of the backplane on plastic to meet AMOLED requirements

A Novel Selected Area Laser Assisted (SALA) System for Crystallization and Doping Processes in Low-Temperature Poly-Si Thin-Film Transistors

CMOS poly-Si thin-film transistors (TFTs) were fabricated through crystallization and GILD processes by a novel selected area laser assisted (SALA) system. The system enables a local area irradiation of small beams of a pulsed solid-state laser of frequency tripled Nd:YAG. The novel TFT process eliminated 3 doping mask steps of the conventional process. On-off current ratios for both types of poly-Si TFTs were improved by SALA. The field effect mobility of n- and p-channel TFTs is 84 cm 2 /Vs and 75 cm 2 /Vs, respectively.