Thin-film Transistor Nonvolatile Memory Research Articles

Non-Volatile Memory Thin-Film Transistors Using Oxide Semiconductor as Both Active and Charge Trapping Layer

Non-Volatile Memory Thin-Film Transistors Using Oxide Semiconductor as Both Active and Charge Trapping Layer

Impacts of pulse conditions on endurance behavior of ferroelectric thin-film transistor non-volatile memory

In this work, the ferroelectric thin-film transistor (Fe-TFT) with polycrystalline-silicon (poly-Si) channel and HfZrO x gate dielectric is fabricated to study the characteristics of non-volatile memory (NVM). Significant threshold voltage (V TH) modulation can be achieved with low pulse voltages less than ±3.5 V and pulse widths within 1 μs. In order to achieve the NVM characteristics of low voltage and high speed operation, the impact of the program/erase (PRG/ERS) pulse voltage (V PRG/V ERS) and pulse width on endurance is a critical consideration. In the study of the pulse width effect on endurance, it can be observed that the V TH in PRG-state exhibits the wake-up effect at both short and long pulse widths. In addition, with the increase of pulse width, the V TH in the PRG-state exhibits significant fatigue effect and subthreshold swing (SS) degradation effect. For V TH in the ERS-state, the increase of the pulse width also exhibits the fatigue effect and the SS degradation effect, which is dominated by the SS degradation effect at long pulse widths. In the study of the pulse voltage effect on endurance, the increase of V PRG shows the imprint effect that the V TH in either PRG- or ERS-state reveals a decreasing trend. When the V ERS increases, the SS of the PRG- and ERS-states is degraded, and the fatigue effect of the PRG-state is enhanced. Moreover, the retention characteristics of poly-Si Fe-TFTs exhibit stable characteristics at both room temperature and 50 °C.

High-performance amorphous In-Ga-Zn-O thin-film transistor nonvolatile memory with a novel p-SnO/n-SnO2 heterojunction charge trapping stack

Amorphous In–Ga–Zn–O (a-IGZO) thin-film transistor (TFT) memories with novel p-SnO/n-SnO2 heterojunction charge trapping stacks (CTSs) are investigated comparatively under a maximum fabrication temperature of 280 °C. Compared to a single p-SnO or n-SnO2 charge trapping layer (CTL), the heterojunction CTSs can achieve electrically programmable and erasable characteristics as well as good data retention. Of the two CTSs, the tunneling layer/p-SnO/n-SnO2/blocking layer architecture demonstrates much higher program efficiency, more robust data retention, and comparably superior erase characteristics. The resulting memory window is as large as 6.66 V after programming at 13 V/1 ms and erasing at –8 V/1 ms, and the ten-year memory window is extrapolated to be 4.41 V. This is attributed to shallow traps in p-SnO and deep traps in n-SnO2, and the formation of a built-in electric field in the heterojunction.

Phase‐Separated, Printed Organic Thin‐Film Transistor‐Based Nonvolatile Memory with Enhanced Data Retention

AbstractA nonvolatile memory thin film transistor (TFT) is an essential building block in all electronic applications for calculation and identification. In particular, organic memory TFTs using bilayered polymer electrets have attracted significant attention due to excellent mechanical flexibility and fast operating speed. However, the data retention characteristics over an extended period of time remains a major reliability issue for nonvolatile memory devices. Here, the enhancement of data retention in flexible and printed organic memory TFTs by introducing a phase‐separated tunneling layer is demonstrated. The tunneling layer is formed during an active layer printing process with a blend ink of small‐molecule organic semiconductor and polystyrene insulator. The effect of the dielectric tunneling layer on data retention characteristics is systematically investigated. The printed nonvolatile memory devices with the phase‐separated tunneling layer exhibit significantly improved data retention time of over 10 years, validating the feasibility of applying flexible memory into wearable electronics and smart Internet‐of‐Things devices.

The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal–insulator–silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (ΔVFB) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 107 were obtained at the initial sweep of the devices. As an NVM, ΔVFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The ΔVFB was returned to the pristine condition with a negative voltage pulse of −1 V and 1 μs under a 400–700 nm light illumination of ~10 mWcm−2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial ΔVFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.

Charge-trap-assisted flexible nonvolatile memory applications using oxide-semiconductor thin-film transistors

We introduce mechanically flexible nonvolatile memory thin-film transistors (MTFTs) for future highly functional flexible and stretchable electronic devices and systems. The proposed memory devices are uniquely composed of oxide-semiconductor thin films and operated with charge-trap and detrap mechanisms for nonvolatile memory operations. Charge-trap-assisted MTFTs (CT-MTFTs) using In–Ga–Zn–O active and ZnO charge-trap layers are designed and fabricated on flexible poly(ethylene naphthalate) and colorless polyimide films prepared on carrier glass substrates. We describe the fabrication processes and evaluation methodologies for realizing flexible CT-MTFTs in a detailed way and discuss related technical issues. The device characteristics and memory performance of the fabricated flexible CT-MTFTs, including when the devices are mechanically strained, are extensively discussed. We also propose further improvements for remaining issues on device performance from the viewpoints of memory operations and mechanical flexibility.

Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method

A low-voltage programmable gate-all-around (GAA) nanosheet poly-Si thin-film transistor (TFT) nonvolatile memory (NVM), which uses band-to-band tunneling induced hot electron (BBHE) programming, is demonstrated. The BBHE method is extremely efficient for programming data in the p-type GAA nanosheet TFT NVM because the GAA nanosheet structure enhances the source-to-drain component of the electric field in its channel. Therefore, the enhanced electric field of the BBHE phenomenon creates energetic electrons that surmount the tunneling oxide barrier easily and pass shallow traps in the charge trapping layer of the GAA TFT NVM. Consequently, the p-type GAA TFT NVM achieves low-voltage programming bias and satisfactory data retention

Solution processed nonvolatile polymer transistor memory with discrete distributing molecular semiconductor microdomains as the charge trapping sites

In this work, we demonstrate a polymer poly(3-hexylthiophene-2,5-diyl) (P3HT) based organic thin-film transistor nonvolatile memory, in which the four-layer stacked core architecture is sequentially processed by a method of fully solution spin-coating. The floating-gate layer consists of separated molecular semiconductor 6,13-bis(triisopropylsilylethynyl)pentacene (TIPS-Pen) microdomains distributing in the matrix of polymer poly(styrene) (PS), which is formed by phase-separation during the spin-coating from their blend solution. At the writing/erasing operation, the holes transfer between P3HT active layer and TIPS-Pen microdomains, which results in an prominent memory property, with a memory window of 14 V, memory on/off ratio larger than 350, reliable memory endurance over 500 cycles and a good retention capability over 5000 s with obvious distinguishing reading current at binary 0 and 1 states.

Paolo Samorì

Angewandte Chemie International EditionVolume 56, Issue 49 p. 15498-15498 Author ProfileFree Access Paolo Samorì First published: 17 August 2017 https://doi.org/10.1002/anie.201707626Citations: 4AboutSectionsPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinkedInRedditWechat Graphical Abstract “My science “hero” is Richard Feynman. The most important thing I learned from my students is innocent curiosity ...” This and more about Paolo Samorì can be found on page 15498. Paolo Samorì The author presented on this page has recently published his 10th article in Angewandte Chemie in the last 10 years: “Ultrafast Delamination of Graphite into High-Quality Graphene Using Alternating Currents”: S. Yang et al., Angew. Chem. Int. Ed. 2017, 56, 6669; Angew. Chem. 2017, 129, 6770. The work of P. Samorì has been featured on the cover of Angewandte Chemie: “Dynamers at the Solid–Liquid Interface: Controlling the Reversible Assembly/Reassembly Process between Two Highly Ordered Supramolecular Guanine Motifs”: A. Ciesielski, S. Lena, S. Masiero, G. P. Spada, P. Samorì, Angew. Chem. Int. Ed. 2010, 49, 1963; Angew. Chem. 2010, 122, 2007. Date of birth: May 3, 1971 Position: Distinguished Professor, Université de Strasbourg, and Director, Institut de Science et d'Ingénierie Supramoléculaires (ISIS), Strasbourg E-mail: samori@unistra.fr Homepage: www.nanochemistry.fr ORCID: 0000-0001-6256-8281 Education: 1995 Laurea, University of Bologna 2000 PhD, Humboldt Universität zu Berlin Awards: 2010 Junior member of the Institut Universitaire de France (IUF); 2011 Fellow of the Royal Society of Chemistry; 2012 CNRS Silver Medal; 2014 Fellow of the European Academy of Sciences; 2014 Member of the Academia Europaea; 2017 Grignard–Wittig Lecture (GDCh); 2017 Catalan–Sabatier Prize (RSEQ) Current research interests: Multifunctional nanomaterials for electronics, energy, and sensing applications; two-dimensional materials; organic electronics; supramolecular chemistry; nanoscience Hobbies: Nature, fishing, hunting My science “hero” is Richard Feynman. The most important thing I learned from my students is innocent curiosity. The secret of being a successful scientist is openness, passion, and perseverance: never give up! If I had one year of paid leave I would make a world tour with my family. The principal aspect of my personality is that I am always willing to learn from anyone I meet. My favorite musician is David Bowie. The biggest challenge facing scientists is finding a solution to energy and environmental problems. Looking back over my career, I am happy to be a chemist! My favorite drink is red wine – spicy and berry-flavored (Grenache and/or Syrah). If I were a car I would be a red Ferrari (with paint based on a diketopyrrolopyrrole dye). My biggest inspiration is Nature – any living matter around me. I advise my students to keep their eyes fully open when they are doing an experiment to catch any unexpected behavior or result. My 5 top papers: 1“Cooperative light-induced molecular movements of highly ordered azobenzene SAMs”: G. Pace, V. Ferri, C. Grave, M. Elbing, M. Zharnikov, M. Mayor, M. A. Rampi, P. Samorì, Proc. Natl. Acad. Sci. USA. 2007, 104, 9937. (Photochemical switching can occur over entire molecular 2D crystalline domains.) 2“Molecular Tectonics on Surfaces: Bottom-Up Fabrication of 1D Coordination Networks that Form 1D and 2D Arrays on Graphite”: M. Surin, P. Samorì, A. Jouaiti, N. Kyritsakas, M. W. Hosseini, Angew. Chem. Int. Ed. 2007, 46, 245; Angew. Chem. 2007, 119, 249. (Nanopatterning of 1D or 2D multifunctional arrays on surfaces with sub-nanometer precision.) 3“Self-assembly of an Amphiphilic π-Conjugated Dyad into Fibers: Ultrafast and Ultrasensitive Humidity Sensor”: M. A. Squillaci, L. Ferlauto, Y. Zagranyarski, S. Milita, K. Müllen, P. Samorì, Adv. Mater. 2015, 27, 3170. (The self-assembly of electroactive π–π stacked fibrillar structures can be triggered by irradiation with visible light.) 4“Light-enhanced liquid-phase exfoliation and photoswitching current in graphene–azobenzene composites”: M. Döbbelin et al., Nat. Commun. 2016, 7, 11090. (Reversible photomodulated current was observed in two-terminal devices based on these composites.) 5“Flexible non-volatile optical memory thin-film transistor device with over 256 distinct levels based on an organic bicomponent blend”: T. Leydecker, M. Herder, E. Pavlica, G. Bratina, S. Hecht, E. Orgiu, P. Samorì, Nat. Nanotech 2016, 11, 769. (A blend of a reference polymer semiconductor and a photochromic diarylethene that can be switched with ultraviolet and green light irradiation.) Citing Literature Volume56, Issue49December 4, 2017Pages 15498-15498 ReferencesRelatedInformation

Solution-processed highly efficient Au nanoparticles and their reduced graphene oxide nanocomposites as charge trapping media for ZnO thin film transistor nonvolatile memory

Solution-processed, non-volatile undoped and Hf-doped ZnO thin film transistor (TFT) memory was demonstrated by inserting gold nanoparticles (AuNPs) and AuNPs reduced graphene oxide (AuNPs-rGO) nanocomposite charge trapping media between undoped and Hf-doped ZnO and SiO2 dielectrics. The one step reduction and decoration of graphene oxide with AuNPs to create the nanocomposites used thermostable Nisin peptides. Undoped and Hf-doped ZnO TFT memory devices made with AuNPs and AuNPs-rGO exhibited large gate bias-dependent clockwise hysteresis windows. The memory devices exhibited excellent programmable windows of up to 40 V during program/erase operations. This is attributed to trapping and de-trapping of charge carriers by the AuNPs and the AuNPs-rGO nanocomposites. The resulting memory devices exhibited remarkable long-term retention characteristics. Hf-doped ZnO TFT memory devices made with AuNPs or AuNPs-rGO nanocomposites exhibited higher ON/OFF ratios than those made with undoped ZnO. The memory devices made with AuNPs-rGO nanocomposites exhibited ON/OFF ratios greater than 104.

Atomic-layer-deposition-assisted ZnO nanoparticles for oxide charge-trap memory thin-film transistors

ZnO nanoparticles (NPs) with monolayer structures were prepared by atomic layer deposition (ALD) to use for a charge-trap layer (CTL) for nonvolatile memory thin-film transistors (MTFTs). The optimum ALD temperature of the NP formation was demonstrated to be 160 °C. The size and areal density of the ZnO NPs was estimated to be approximately 33 nm and 4.8 × 109 cm−2, respectively, when the number of ALD cycles was controlled to be 20. The fabricated MTFTs using a ZnO-NP CTL exhibited typical memory window properties, which are generated by charge-trap/de-trap processes, in their transfer characteristics and the width of the memory window (MW) increased from 0.6 to 18.0 V when the number of ALD cycles increased from 5 to 30. The program characteristics of the MTFT were markedly enhanced by the post-annealing process performed at 180 °C in an oxygen ambient due to the improvements in the interface and bulk qualities of the ZnO NPs. The program/erase (P/E) speed was estimated to be 10 ms at P/E voltages of −14 and 17 V. The memory margin showed no degradation with the lapse in retention time for 2 × 104 s and after the repetitive P/E operations of 7 × 103 cycles.

Preparation of Mono-Layered Ag Nanoparticles for Charge-Trap Sites of Memory Thin-Film Transistors Using In-Ga-Zn-O Channel

We propose a methodology for the formation of silver (Ag) nanoparticle monolayer as charge trapping layer of nonvolatile memory thin-film transistor using an indium-gallium-zinc oxide semiconductor channel layer. Atomic-layer-deposited Al2O3-amine treatment Ag configuration were employed as tunneling/charge-trap layers, respectively. The memory devices showed wide memory window of 8.0 V, when the gate voltage was swept from −20 to 20 V. The high on/off current ratios of 5.81 × 105 and 1.29 × 103 could be obtained for the memory device, when the program pulse duration was reduced to 1 μs and 5 ns, respectively. The Ag nanoparticle monolayer could be prepared by using the amine-functionalized Al2O3 layer. The areal density of Ag nanoparticle was controlled by modulating the Ag ratio in polystyrene (PS) mixture and optimized at Ag:PS ratio of 5:5.

Formation of ZnO Nanoparticles by Atomic Layer Deposition for the Nonvolatile Memory Thin-Film Transistor Applications

Charge-trap-type memory device employing oxide-semiconductor charge-trap layers (CTL), such as ZnO and In-Ga-Zn-O (IGZO), have been intensively investigated for nonvolatile memory TFT applications [1]. Although encouraging device characteristics could be obtained for the proposed memory TFT, they can be expected to be far improved by using nano-particle (NP) mono-layers as alternative CTLs thanks to their isolated structures. So far, various methods such as spray pyrolysis and high-temperature-assisted self-assembly have been suggested to form discrete NP mono-layers [2]. However, low controllability in areal density of NPs and high process temperature limit device performance as well as process compatibility on flexible substrate.In this work, we propose a low-temperature atomic-layer-deposition (ALD) process for the formation of ZnO NPs with an island-growth mechanism and fabricated the memory TFTs using the ZnO-NP CTLs. We also investigate the effects of ALD conditions for the ZnO NPs on the device performance of the fabricated ZnO-NP memory TFTs (NP-MTFT). The gate-stack structure of top-gate NP-MTFTs were designed as In-Sn-O (ITO) gate electrode (150 nm)/Al2O3 blocking oxide (50 nm)/ZnO NP CTL/Al2O3 tunneling layer (10 nm)/IGZO active channel layer (20 nm)/ITO source-drain electrode (100 nm). ALD cycles for the ZnO NPs were varied to 5, 20, 30, and 40 and the deposition temperature was modulated from 100 to 190oC to investigate the effects of ALD conditions on the island formation of ZnO NPs. Diethylzinc (DEZn) and H2O was used as Zn and O precursors, respectively. The size and areal density of the ZnO NPs prepared at 160oC with 20 ALD cycles were estimated to be approximately 33 nm and 3×109 cm-2, respectively. It was interesting to note the changes in arithmetic average of surface roughness (Ra) at various ALD temperatures when the ALD cycles increased from 5 to 20 cycles. The variations in Ra were summarized to be from 0.24 to 0.28 nm at 100oC, from 0.26 to 0.40 nm at 130oC, from 0.98 to 2.13 nm at 160oC, and from 0.21 to 0.22 nm at 190oC. Consequently, it was found that the island growth of ZnO NPs could not be available at 100 and 190oC. On the other hand, at 160oC, the ZnO NPs could be successfully formed with appropriate deposition rate with increasing the ALD cycles.The NP-MTFTs employing these ZnO NP CTLs exhibited typical charge-trap nonvolatile memory device behaviors. The memory window (MW) width of the fabricated NP-MTFTs monotonously increased with increasing the ALD cycles from 0.6 to 14.6 V when VGS was swept in the forward and reverse directions in the range of ±20V at a drain bias (VDS) of 0.1 V. The MW (12.2 V) of the NP-MTFT drastically was increased for the 20-cycle device compared with that for the 5-cycle device. This result suggests that the areal density of ZnO NPs could be effectively modulated by controlling the ALD cycles of DEZ between 5 and 20 cycles. The on- and off-program characteristics of the NP-MTFTs were evaluated as a function of program voltage pulse width. The read-out operations were performed at VGS of -2 V and VDS of 0.1 V. The ratios of programmed IDS of on-states to that of off-states (Ion/Ioff) were obtained as more than 3×107 and did not experienced marked degradation when the program pulse width decreased from 1 s to 1 µs. These results suggest that the proposed NP-MTFT exhibited nonvolatile memory operations with wide memory window and high-speed program time. This is the first demonstration for the NP-MTFTs using the ALD-assisted ZnO-NP CTLs. Flexible memory device will be fabricated as future works and detailed device characteristics will be discussed at the presentation. [1] S. J. Kim, W. H. Lee, C. W. Byun, C. S. Hwang, and S. M. Yoon, IEEE Electron. Dev. Lett. 36 (11) 1153, 2015.[2] Z. Liu, C. H. Lee, V. Narayanan, G. Pei, and E. C. Kan, IEEE Trans. Electron. Dev. 49 (9), 1606, 2002.

Formation of ZnO Nanoparticles by Atomic Layer Deposition for the Nonvolatile Memory Thin-Film Transistor Applications

A low-temperature atomic-layer-deposition (ALD) process for the formation of ZnO nanoparticles (NPs) was demonstrated, in which the ALD temperature and cycles for diethylzinc precursor were controlled to be 160 oC and 20 cycles. The size and areal density of ZnO NPs were confirmed to be approximately 33 nm and 3×109 cm-2, respectively. Nonvolatile memory thin-film transistors were fabricated by employing the ZnO NPs as charge-trap centers for memory operations. The memory window was found to increase from 0.6 to 17.8 V with increasing the ALD cycles from 5 to 20. On- and off-program operations were also confirmed even with voltage pulses as short as 1 µs.

Flexible non-volatile optical memory thin-film transistor device with over 256 distinct levels based on an organic bicomponent blend.

Organic nanomaterials are attracting a great deal of interest for use in flexible electronic applications such as logic circuits, displays and solar cells. These technologies have already demonstrated good performances, but flexible organic memories are yet to deliver on all their promise in terms of volatility, operational voltage, write/erase speed, as well as the number of distinct attainable levels. Here, we report a multilevel non-volatile flexible optical memory thin-film transistor based on a blend of a reference polymer semiconductor, namely poly(3-hexylthiophene), and a photochromic diarylethene, switched with ultraviolet and green light irradiation. A three-terminal device featuring over 256 (8 bit storage) distinct current levels was fabricated, the memory states of which could be switched with 3 ns laser pulses. We also report robustness over 70 write-erase cycles and non-volatility exceeding 500 days. The device was implemented on a flexible polyethylene terephthalate substrate, validating the concept for integration into wearable electronics and smart nanodevices.

Effect of Ti Content on the Structural and Electrical Characteristics of ErTixOyCharge Storage Layer in InGaZnO Thin-Film Transistor Nonvolatile Memories

This paper describes the effect of titanium content on the structural and electrical properties of ErTi x O y charge storage layers in amorphous indium–gallium–zinc oxide ( $\alpha $ -IGZO) thin-film transistor (TFT) nonvolatile memory (NVM) devices. X-ray diffraction, Auger electron spectroscopy, and X-ray photoelectron spectroscopy were used to study the film structural, depth profiling, and chemical features, respectively, of these films as the functions of the growth conditions (Ti plasma powers of 60, 100, and 140 W). The ErTi x O y IGZO TFT NVM devices fabricated at the 100-W condition exhibited a larger memory window of 4.1 V, a smaller charge loss of 13% (after ten years), and a better endurance characteristic (up to $10^{5}$ program/erase cycles), as compared with other conditions. This result suggests that the Er2TiO5 film featuring a high dielectric constant and reducing an Er(OH) x layer can provide the higher charge-trapping efficiency and deeper electron trapping levels.

Read-Out Modulation Scheme for the Display Driving Circuits Composed of Nonvolatile Ferroelectric Memory and Oxide–Semiconductor Thin-Film Transistors for Low-Power Consumption

New circuit architecture composed of nonvolatile memory thin-film transistors (M-TFTs) and oxide–semiconductor TFTs (Ox-TFTs) has been proposed to realize low-power consumption and compact size for dynamic driving circuit applications. In order to compensate the slow operation speed of the nonvolatile M-TFTs in the dynamic driving circuits, we proposed the read-out modulation (ROM) scheme. The device operation characteristics of the M-TFTs were confirmed under various specified conditions to effectively apply the ROM, in which a top-gate structure was fabricated to be ferroelectric poly(vinylidene fluoride-trifluoroethylene) gate insulator/Al2O3/In–Ga–ZnO active layers. Full fabrication processes for the M-TFTs were optimized, so that they can be integrated with Ox-TFTs on the same glass substrate. The memory device characteristics, including the current ratios between ON- and OFF-programmed drain current ( $I_{D}$ ) values ( $I_{p-\mathrm {\mathrm{\scriptscriptstyle ON}}}/I_{p-\mathrm {\mathrm{\scriptscriptstyle OFF}}})$ before and after the ROM, drain-bias dependence of the $I_{p-\mathrm {\mathrm{\scriptscriptstyle ON}}}/I_{p-\mathrm {\mathrm{\scriptscriptstyle OFF}}}$ , and the program $I_{D}$ scalability, were confirmed for the fabricated M-TFT. These results suggest the feasibility of a low-power display driver circuit embedded with the nonvolatile M-TFTs.

Novel Multi-Level Cell TFT Memory With an In–Ga–Zn-O Charge Storage Layer and Channel

Amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor nonvolatile memory devices with an IGZO charge storage layer were evaluated for the first time for multi-level cell memory applications. The pristine device was defined as the original state (OS), which can be switched to the programmed state (PS) after a positive gate voltage pulse (for example, 12 V for 10 ms), and to the erased state (ES) after a negative gate voltage pulse (for example, −15 V for 10 ms). The writing mechanism was attributed to Fowler–Nordheim tunneling of electrons from the channel to the charge storage layer under a positive gate bias and inverse tunneling under a negative gate bias. The devices demonstrated superior electrical programmable and erasable characteristics. A memory window of 2.4 V between OS and PS was maintained after 100 programming/erasing cycles, and a memory window of 2.66 V between OS and ES as well. The memory windows relative to OS are equal to 1.91 and 1.30 V for PS and ES, respectively, for a retention time of $10^{5}$ s.

Highly Reliable Top-Gated Thin-Film Transistor Memory with Semiconducting, Tunneling, Charge-Trapping, and Blocking Layers All of Flexible Polymers

The core components of a floating-gate organic thin-film transistor nonvolatile memory (OTFT-NVM) include the semiconducting channel layer, tunneling layer, floating-gate layer, and blocking layer, besides three terminal electrodes. In this study, we demonstrated OTFT-NVMs with all four constituent layers made of polymers based on consecutive spin-coating. Ambipolar charges injected and trapped in a polymer electret charge-controlling layer upon gate program and erase field successfully allowed for reliable bistable channel current levels at zero gate voltage. We have observed that the memory performance, in particular the reliability of a device, significantly depends upon the thickness of both blocking and tunneling layers, and with an optimized layer thickness and materials selection, our device exhibits a memory window of 15.4 V, on/off current ratio of 2 × 10(4), read and write endurance cycles over 100, and time-dependent data retention of 10(8) s, even when fabricated on a mechanically flexible plastic substrate.

Multilevel memory characteristics by light-assisted programming in floating-gate organic thin-film transistor nonvolatile memory

In this work, we study charge trapping in floating-gate organic thin-film transistor nonvolatile memories (FG-OTFT-NVMs) fabricated by a simple method. The inner discrete distribution aluminum nanoparticles (Al-Nps) and the continuous compact thin alumina film were formed to act as the floating-gate and the tunneling dielectric layer, respectively by thermally evaporated Al at a slow rate and then heat annealed in dry air. The devices exhibited remarkable photoresponse and memory effect. Compared with the unidirectional threshold voltage (VT) shifts of memories by programming/erasing (P/E) in dark, larger bidirectional VT shifts were obtained by light-assisted programming, and therefore the memory performances were enhanced. A multilevel memory behavior was observed in our memories, which depended on programming conditions. The charge trapping mechanisms of memories operated in dark and under illumination are discussed, respectively. The results indicate that optimal memory performance requires charge carriers of both polarities, because it is a very efficient method to enlarge the memory window and to lower the P/E voltage by overwriting trapped charges by injected charges of opposite polarity.