Thin-film Transistor Circuits Research Articles

High-performance of low temperature solution-processed P-channel CuGaO thin film transistors

The exploration of p-type metal-oxide semiconductors (MOS) has garnered growing interest, particularly for their potential applications in next-generation optoelectronic devices, display backplanes, and low-power consumption complementary MOS (CMOS) circuits. Here, we introduced low-temperature solution-processed copper gallium oxide (CuGaO) films for p-channel thin-film transistors (TFTs). Hall Effect measurements confirmed the p-type conduction of CuGaO, revealing a conductivity and mobility of 3.76 ×10−2 S/cm and 7.89 cm2V–1s–1, respectively. The p-channel CuGaO-250 TFT demonstrated a field-effect mobility (μFE) of 1.24 cm2V–1s–1, the lowest subthreshold swing (SS) of 519 mV/dec, and an ON/OFF current ratio (ION/IOFF) of ∼104 at a low operating voltage. The notable improvement in TFT performance can be attributed to the quality of the CuGaO-250 film, a smooth surface morphology, and a reduction of interfacial traps between the semiconductor and the gate insulator. Hence, low-temperature fabrication of the p-channel CuGaO TFT holds promise for implementing metal oxide-based TFT and complementary metal oxide semiconductor (CMOS) circuits in next-generation displays.

Nanosurface-reconstructed perovskite for highly efficient and stable active-matrix light-emitting diode display.

Perovskite quantum dots (QDs) are promising for various photonic applications due to their high colour purity, tunable optoelectronic properties and excellent solution processability. Surface features impact their optoelectronic properties, and surface defects remain a major obstacle to progress. Here we develop a strategy utilizing diisooctylphosphinic acid-mediated synthesis combined with hydriodic acid-etching-driven nanosurface reconstruction to stabilize CsPbI3 QDs. Diisooctylphosphinic acid strongly adsorbs to the QDs and increases the formation energy of halide vacancies, enabling nanosurface reconstruction. The QD film with nanosurface reconstruction shows enhanced phase stability, improved photoluminescence endurance under thermal stress and electric field conditions, and a higher activation energy for ion migration. Consequently, we demonstrate perovskite light-emitting diodes (LEDs) that feature an electroluminescence peak at 644 nm. These LEDs achieve an external quantum efficiency of 28.5% and an operational half-lifetime surpassing 30 h at an initial luminance of 100 cd m-2, marking a tenfold improvement over previously published studies. The integration of these high-performance LEDs with specifically designed thin-film transistor circuits enables the demonstration of solution-processed active-matrix perovskite displays that show a peak external quantum efficiency of 23.6% at a display brightness of 300 cd m-2. This work showcases nanosurface reconstruction as a pivotal pathway towards high-performance QD-based optoelectronic devices.

Active-matrix digital microfluidics design for field programmable high-throughput digitalized liquid handling

Digital liquid sample handling is an enabling tool for cutting-edge life-sciences research. We present here an active-matrix thin-film transistor (TFT) based digital microfluidics system, referred to as Field Programmable Droplet Array (FPDA). The system contains 256×256 pixels in an active area of 10.65cm2, which can manipulate thousands of addressable liquid droplets simultaneously. By leveraging a novel TFT device and circuits design solution, we manage to programmatically manipulate droplets at single-pixel level. The minimum achievable droplet volume is around 0.5 nL, which is two orders of magnitude smaller than the smallest droplet ever reported on active-matrix digital microfluidics. The movement of droplets can be either pre-programmed or controlled in real-time. The FPDA system shows great potential of the ubiquitous thin-film electronics technology in digital liquid handling. These efforts will make it possible to create a true programmable lab-on-a-chip device to enable great advances in life science research.

Compositional Engineering of Cu-Doped SnO Film for Complementary Metal Oxide Semiconductor Technology.

Metal oxide semiconductor (MOS)-based complementary thin-film transistor (TFT) circuits have broad application prospects in large-scale flexible electronics. To simplify circuit design and increase integration density, basic complementary circuits require both p- and n-channel transistors based on an individual semiconductor. However, until now, no MOSs that can simultaneously show p- and n-type conduction behavior have been reported. Herein, we demonstrate for the first time that Cu-doped SnO (Cu:SnO) with HfO2 capping can be employed for high-performance p- and n-channel TFTs. The interstitial Cu+ can induce an n-doping effect while restraining electron-electron scatterings by removing conduction band minimum degeneracy. As a result, the Cu3atom%:SnO TFTs exhibit a record high electron mobility of 43.8 cm2 V-1 s-1. Meanwhile, the p-channel devices show an ultrahigh hole mobility of 2.4 cm2 V-1 s-1. Flexible complementary logics are then established, including an inverter, NAND gates, and NOR gates. Impressively, the inverter exhibits an ultrahigh gain of 302.4 and excellent operational stability and bending reliability.

Composition Engineering of Indium Zinc Oxide Semiconductors for Damage-Free Back-Channel Wet Etching Metallization of Oxide Thin-Film Transistors.

In contrast to lift-off and shadow mask processes, the back-channel wet etching (BCWE) process is suitable for industrial-scale metallization processes for the large-area and mass production of oxide thin-film transistors (TFTs). However, chemical attacks caused by the corrosive metal etchants used in the BCWE process cause unintended performance degradation of oxide semiconductors, making it difficult to implement oxide TFT circuits through industrial-scale metallization processes. Herein, we propose composition engineering of oxide semiconductors to enhance the chemical durability and electrical stability of oxide semiconductors. The chemical durability of InZnO against Al etchants can be improved by increasing the content of indium oxide, which has a higher chemical resistance than zinc oxide. As a result, A damage-free BCWE-based metallization process was successfully demonstrated for oxide TFTs using In-rich InZnO semiconductors. Furthermore, In-rich InZnO TFTs with wet-etched Al electrodes exhibited electrical performance comparable to that of lift-off Al electrodes, without chemical attack issues.

47‐2: Photosensitive characteristics and application of photosensitive device based on TFT process

A glass‐based TFT (thin film transistor circuit) module with ambient light detection function was designed and manufactured on the display panel, and the photoelectric characteristics of TFT photosensitive devices were measured and obtained. After the data analysis and processing, the photoelectric characteristic curves with good linearity were obtained. After algorithmically optimizing the intrinsic data, the thin‐film transistor photosensitive element achieved the same photoelectric characteristic as the silicon‐based photosensitive element. Measurements of the photoelectric characteristics of the TFT photosensitive device showed that the photoelectric performance of the sensor is repeatable and relatively undetermined. The photoelectric characteristics demonstrate the corresponding relationship of multiple direction functions. Different products show different current values under the same illumination, but the overall photoelectric characteristics still maintain the trend of multiple direction functions. In the experiment, 200 TFT photosensitive device units were connected into a set of photosensitive elements array, and placed under the ambient illumination of 0~30000 LUX. The output current range of the photosensitive array after parallel connection is 0~200 mA. The results indicate that the photoelectric characteristic of TFT photosensitive device has linear relationship after effective data processing and algorithm computing. After testing with different products, the device characterizes the ambient light with less than 5% accuracy. Therefore, the glass‐based TFT module with ambient light detection function can accurately reflect the data of ambient light, realizing the practicability of the photosensitive device based on TFT technology.

Using SiNx double-layer deposition to reduce electrode incidence of short circuits due to impurity particles in thin film transistor preparation

Aviation safety relies on accurate scope presentation of air navigation displays, and lack of display information due to poor dot line may cause the pilot to misjudge the air conditions. Impurity particles occurred during preparing thin film transistor (TFT) circuit may be a leading reason for poor dot line. This work attempts to replace existing SiNx single-layer deposition with double-layer, so that the incidence risk can be lower through reducing number and size of the impurity particles. Double-layer deposition approach has the dot line structures and performances to that of single-layer, and can meet the requirements of display usage. Results of field test demonstrate that double-layer deposition reduces defect rate of display more efficient than single-layer. Proposed mechanism of double-layer deposition illuminates that 2nd-SiNx can cover holes generated by falling impurity particles to avoid short circuits in both indium tin oxide (ITO) and source-drain (SD) contact.

How to print high-mobility metal oxide transistors—Recent advances in ink design, processing, and device engineering

High-throughput printing-based fabrication has emerged as a key enabler of flexible electronics given its unique capability for low-cost integration of circuits based on printed thin film transistors (TFTs). Research in printing inorganic metal oxides has revealed the potential for fabricating oxide TFTs with an unmatched combination of high electron mobility and optical transparency. Here, we highlight recent developments in ink chemistry, printing physics, and material design for high-mobility metal oxide transistors. We consider ongoing challenges for this field that include lowering process temperatures, achieving high speed and high resolution printing, and balancing device performance with the need for high mechanical flexibility. Finally, we provide a roadmap for overcoming these challenges with emerging synthetic strategies for fabricating 2D oxides and complementary TFT circuits for flexible electronics.

P‐13.1: Source‐Contacted Metal Isolation Layer for Camera under Panel in Smartphones†

Camera under panel (CUP) technology is essential for truly full‐screen display in smartphones. We present here an excellent design used on the Mi Mix 4 phone by shrinking the pixel size and increasing pixel brightness in the CUP area. Considering the different degradation rates of TFT devices between active area and CUP area, a source‐contacted metal isolation layer (MIL) under the thin‐film transistors (TFTs) is employed to obtain superior electrical reliability. This MIL technology can shield mobile charges within polyimide (PI) substrate and help improve initial current drop level of TFT circuit, thus achieving a uniform display quality and a seamless viewing experience. It was also found that long‐term image sticking time can be significantly reduced to less than 3min. These results may lead to widespread applications in the field of flexible displays.

Yield and leakage current of organic thin-film transistor logic gates toward reliable and low-power operation of large-scale logic circuits for IoT nodes

This paper reports on a strategy for yield improvement and static leakage current reduction by a standard cell design for large-scale organic thin-film transistor (OTFT) circuits. Printable or flexible devices are suitable for IoT nodes, and digital OTFT circuits comprise the peripheral circuits of such devices. Sufficiently high yields and low static power consumptions are essential for battery operations of IoT nodes having functional digital circuits. Our design method to address the weak n-type OTFT on-current results in improved logic gate yields without any cell area increase. We improved the yield of the inverter, NAND, and NOR gates using a standard cell design, and achieved a 100% yield for the inverter and NOR gates and 88% yield for the NAND gates. Signal propagations with the rail-to-rail operation were measured on test chips. Leakage currents of 585 pA and 2.94 nA were achieved for the inverter and NOR gates, respectively.

Printed carbon nanotube thin film transistors based on perhydropolysilazane-derived dielectrics for low power flexible electronics

Electric double layer (EDL) electrolyte dielectrics have attracted great interest for low voltage and low power consumption portable thin film transistor (TFT) devices and circuits due to their high gate modulation efficiency. In this work, fully printed single-walled carbon nanotube (SWCNT) TFTs are fabricated using proton conducting inorganic perhydropolysilazane (PHPS) derivatives as the EDL dielectrics at low frequencies (<1 kHz) that can be processed in humidity even at quite low temperature (<100 °C) and relatively short reaction time (∼10 min). Fabricated fully printed SWCNT TFTs exhibit excellent electrical properties with low operating voltage (±1 V), high on/off ratio (∼106), small subthreshold swing (70–110 mV/dec), good stability and the average carrier mobility of 6.3 cm2 V−1 s−1. In addition, the precise control of the SWCNT TFTs’ threshold voltage and polarity (from depleted p-type to enhanced p and n-type, and well-balanced ambipolar) is successful demonstrated by adjusting the printable sc-SWCNT ink concentrations and electron doping technology (using ethanolamine as the electron doping agent). Furthermore, fully printed flexible complementary metal oxide semiconductor (CMOS) and CMOS-like inverters based on as-prepared SWCNT TFTs represent extremely low static power consumption (0.1 pW/μm and 0.05 pW/μm, respectively), high voltage gain (up to 45 at VDD = 0.7 V) and relatively large noise margins.

Transparent, P‐channel CuISn Thin‐film Transistor with Field Effect Mobility of 45 cm2 V–1 s–1 and Excellent Bias Stability

AbstractThe p‐type semiconducting materials are essential building blocks for high performance complementary metal‐oxide semiconductor (CMOS) thin‐film transistor (TFT) circuits. Here, the development of the transparent and high performance of p‐channel copper‐iodide‐tin (CuISn) TFTs is reported. Sn alloy in CuI exhibits remarkable changes in structural and physical properties, which are studied by scanning electron microscopy, high‐resolution transmission electron microscopy, and X‐ray photoelectron spectroscopy, and Hall effect measurements. It is confirmed that 25% Sn‐alloyed CuI has p‐type conductivity with carrier concentration of 2.1 × 1017 cm–3 and Hall mobility of 63.8 cm2 V–1 s–1. The TFT made with 25% CuISn exhibits the high field‐effect mobility (μFE) of 45.5 cm2 V–1 s–1, which is 10‐fold higher than that of the pristine CuI TFT. The CuISn TFT on polyimide substrate exhibits the μFE of 42.5 cm2 V–1 s–1 and ON/OFF current ratio of ≈107. In addition, the CuISn TFT shows excellent stability with the threshold voltage shift of 0.6 V under negative gate bias stress. In addition, the hetrojunction with Li doped ZnO, CuISn/LZO p‐n junction exhibit excellent rectifying characteristics with the diode ideality factor of 1.3 and forward to reverse current ratio of ≈107, which is three order higher than that of CuI/LZO diode. Therefore, the p‐channel CuISn TFTs can be widely used to open up cost‐effective transparent CMOS TFT circuits, displays, and flexible electronics.

Arithmetic and Logic Circuits Based on ITO-Stabilized ZnO TFT for Transparent Electronics

In this paper, general logic cell and module designs in basic digital signal processing (DSP), for transparent, flexible chips and wearable electronics are presented. Modified Circuits from ratioed logic and pass transistor logic styles are modified and proposed, based on n-type-only indium tin oxide (ITO) stabilized ZnO thin-film transistors (TFTs) process. Elaborations on logic circuits with purely n-type TFT transistors were carried out to extend the logic swing of circuit outputs and accelerate the signal propagation in complex logic functions with simplified pull-up/pull-down or passive networks. To implement logic complexes on multiple OR-of-ANDs functions with better performance, tailored active controlled ratioed logic style is adopted with faster speed and smaller area by simplifying the transistor networks properly. All the circuits were fabricated on transparent glass plate. The featured 2-input/3-input XOR gate, 4-1 MUX and D flip flop (DFF) can operate with maximum featured delays of 2- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6~\mu \text{s}$ </tex-math></inline-formula> at 5 V power supply, with comparatively over 50% less delays and areas than other state-of-art works. The featured 4-bit adder performs maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16.41~\mu \text{s}$ </tex-math></inline-formula> delay at 5 V in measurement. A 4-bit multiplier is also presented based on the adder and DFF. These proposed TFT circuits exhibited smaller area with relatively moderate-high performance in comparison, which were promising building blocks for transparent flexible DSP electronics with low-speed requirements.

Layout-to-Bitmap Conversion and Design Rules for Inkjet-Printed Large-Scale Integrated Circuits

Digital inkjet printing (IJP) can greatly reduce the manufacturing cost and waste of flexible large-area electronics by adding micro-fine patterns onto plastic foils. Advanced system design using IJP has been limited by the lack of an electronic design automation (EDA) approach. An EDA approach based on a vector-based layout drawing requires parameterized IJP design rules. This study proposes a layout-to-bitmap (L2B) conversion procedure and line-based design rules that leverage the existing circuit layout EDA tools for advanced IJP designs. The L2B conversion is accomplished by optimizing the parameters of the horizontal and vertical lines by varying the drop spacings and platen temperatures. Next, the line-based layouts are converted to bitmap files which are used as IJP input data for printing multiple metal layers. This study systematically investigated the development of an IJP process employing Ag nanoparticles. The physical characteristics of the proposed process were evaluated based on theories concerning inkjet-printed bead formation. The design rules for fabricating printed thin-film transistor (TFT) circuits were documented. Documentation is the first step in creating an IJP process design kit for advanced electronics design. Using the optimized L2B conversion procedure and the design rules, a 10 × 10 array of printed organic TFTs was fabricated to demonstrate the reliability of the developed process. Additionally, the fabricated printed organic TFTs indicated that the proposed process could be extended to large-scale system designs.

Efficient transparent quantum-dot light-emitting diodes with an inverted architecture

Transparent quantum-dot light-emitting diodes (Tr-QLEDs) with an inverted architecture has been developed. The inverted Tr-QLEDs are designed for integrating with thin-film transistors (TFTs) circuit easily. The 1,4,5,8,9,11-hexaazatriphenylenehexacarbonitrile (HAT-CN) is employed as a hole injection layer (HIL) as well as a buffer layer in the inverted Tr-QLEDs. An optimized HAT-CN as dual-functional modified layer facilitates charge injection balance and meanwhile reduces the plasma damage caused by sputtering process. High performance device with a peak current efficiency (CE) and maximum external quantum efficiency (EQE) of 14.7 cd/A and 11.3% was obtained, wherein the EQE is the highest record for Tr-QLEDs. The transmittance of the Tr-QLEDs at 550 nm reached up to 78%. These Tr-QLEDs possess potential for the next-generation transparent displays applications.

High Performance of Solution-Processed Amorphous p-Channel Copper-Tin-Sulfur-Gallium Oxide Thin-Film Transistors by UV/O3 Photocuring.

The development of p-type metal-oxide semiconductors (MOSs) is of increasing interest for applications in next-generation optoelectronic devices, display backplane, and low-power-consumption complementary MOS circuits. Here, we report the high performance of solution-processed, p-channel copper-tin-sulfide-gallium oxide (CTSGO) thin-film transistors (TFTs) using UV/O3 exposure. Hall effect measurement confirmed the p-type conduction of CTSGO with Hall mobility of 6.02 ± 0.50 cm2 V-1 s-1. The p-channel CTSGO TFT using UV/O3 treatment exhibited the field-effect mobility (μFE) of 1.75 ± 0.15 cm2 V-1 s-1 and an on/off current ratio (ION/IOFF) of ∼104 at a low operating voltage of -5 V. The significant enhancement in the device performance is due to the good p-type CTSGO material, smooth surface morphology, and fewer interfacial traps between the semiconductor and the Al2O3 gate insulator. Therefore, the p-channel CTSGO TFT can be applied for CMOS MOS TFT circuits for next-generation display.

The Display Week 2021 Symposium Preview

The Display Week 2021 Symposium Preview

Compact modeling of metal-oxide TFTs based on artificial neural network and improved particle swarm optimization

The application of artificial neural network (ANN) can give a very accurate and fast model for semiconductor devices used in circuit simulations. In this paper, we have applied multi-layer perceptron (MLP) neural network based on limited memory Broyden–Fletcher–Goldfarb–Shanno (L-BFGS) method to model the flexible metal-oxide thin-film transistors (TFTs). An improved particle swarm optimization (PSO) is employed to find suitable initial parameters for the ANN model, which consists of a centroid opposition-based learning algorithm and a mutation strategy based on Euclidean distance to enhance the searching ability further. This hybrid modeling routine can improve the accuracy of predictions of both the I–V and small signal parameters ( $$g_d$$ , $$g_m$$ , etc.) characteristics, which are in good agreement with experimental data and fully demonstrate the validity of the proposed model. Furthermore, the model is implemented into a simulator with Verilog-A. The circuit-level tests of TFT show that the ANN compact model with PSO enables accurate performance estimation of metal-oxide TFT circuits.

(Invited) P-Type Thin Film Oxide Semiconductors for Thin Film Transistor-Based CMOS Logic

The development of products, and perhaps most notably displays, which rely on thin film transistors (TFTs) has been enabled by the availability of high quality, thin film semiconducting materials. Hydrogenated amorphous silicon (a-Si:H) was the first such material to meet the demands of the display industry. Other materials have since also gained importance including polycrystalline silicon, organic semiconductors and, most recently, oxide semiconductors. In this latter case, indium gallium zinc oxide (IGZO) has been successfully commercialised at scale. However, TFT circuits using any of these materials are based on NMOS or PMOS logic rather than CMOS preventing their use where low power consumption is essential such as display driving circuits, memories or logic as it has not proved to be possible to produce n-channel and p-channel TFTs with sufficiently similar performance characteristics in one material system. In the case of the thin film silicon-based materials, this is because the hole mobility is much lower than the electron mobility, whilst in organic semiconductors it is the p-type materials that are superior to the n-type. In this paper, the situation in oxide semiconductors is considered in detail.There are several oxide semiconductors which have been used to make excellent TFTs, perhaps most notably amorphous (a-)IGZO and amorphous zinc tin oxide (a-ZTO). Both of these materials are naturally n-type as their charge neutrality level is close to the conduction band edge. As a result, it has not proved to be possible to successfully introduce sufficient acceptor-type impurities in order to stably produce a p-type behaviour in these materials; completely different p-type thin film oxide semiconductors are therefore required. Cuprous oxide (Cu2O) is one such material, and this will be used as an exemplar in this work, although alternatives such as tin oxide (SnO) and nickel oxide (NiO) have also been reported.This move to alternative material systems presents other challenges. The conduction band minimum in n-type oxides is dominated by spatially extensive and spherically symmetric metal s-shell electron orbitals, and this allows an amorphous phase to be induced by stoichiometry control of oxide semiconductor which has no grain boundaries and is highly uniform but which retains a high electron mobility. However, the valence band maximum in the p-type materials is dominated by oxygen 2p-orbitals (sometimes with metal d-orbital hybridisation is found in Cu2O) which are highly directional. This means that any attempt to introduce an amorphous microstructure would result in a significant reduction in hole mobility compared with the crystalline state (it is this effect that is responsible for a-Si:H having an electron mobility that is 1,000 times lower than its crystalline counterpart).The types of deposition techniques (most commonly sputtering) that are used to produce thin film oxide semiconductors do not permit the production of single-crystalline thin film materials; nanocrystalline microstructures are created instead. This leads to the presence of grain boundaries, which are highly problematic as they contain a high density of defect states. As a result, they act as trap sites for holes and significantly reduce carrier mobility compared with the single crystal state. Some degree of mitigation is possible by controlling grain orientation during growth, and for Cu2O it is possible to select either the (100) or (111) orientation [1]. Grain size may also be increased and boundary defects decreased after growth by annealing [2]. The result is TFTs with a significantly lower field effect mobility (typically less than 1 cm2 V–1 s–1) than is found in the n-type oxide TFTs (typically over 10 cm2 V–1 s–1). Furthermore, these defective grain boundaries can allow the accumulation of electrons in the off-state leading to much higher off-state currents than would be expected [3]. As a result the switching ratio of p-type oxide TFTs is much lower (typically less than 103) than in equivalent n-type devices (>107).Despite these limitations, it is still possible to combine p-type and n-type oxide TFTs to make CMOS logic gates, but it is important to consider carefully the application requirements and the associated compromises that must be made in circuit design.The funding for this work by the Engineering and Physical Sciences Research Council through grant numbers EP/M013650/1, EP/P027032/1 and EP/L015455/1 is gratefully acknowledged.[1] Han, S. and Flewitt, A.J., Thin Solid Films, 704, 138000 (2020)[2] Han, S., et al., Appl. Phys. Lett., 109, 173502 (2016)[3] Han, S. and Flewitt, A.J., IEEE Electron Dev. Lett., 28, 1394 (2017)

Total Gain Recovery in Floating Gate Thin-Film Transistors for Neuromorphic and Edge Computing

We propose a floating-gate (FG) thin-film transistor architecture which alleviates a significant limitation present since the inception of FG field-effect transistors, namely the loss of gain due to parasitic capacitive coupling on the FG [1].The interest in large area electronics has grown beyond traditional applications, such as display and sensing arrays, with recent trends including neuromorphic and edge computing. However, the challenges of fabricating robust thin film transistor (TFT) circuits have remained despite the many significant achievements in material systems and process development. In order to realise the full benefit of low-cost, high-throughput manufacturing methods, device shortcomings need to be addressed [2]. In FG devices, specifically, one major limitation is the degradation of gain compared to conventional devices, as a result of capacitive coupling of the channel and drain potentials to the floating gate. The problem is far more severe in contact-controlled TFTs, such as the staggered-electrode, high-gain source-gated transistor (SGT) [3, 4], and crippling in conventional TFTs manufactured in materials such as InGaZnO [5].SGT operation differs from conventional field-effect TFTs, whereby the semiconductor is fully depleted at the source edge by an energy barrier (e.g. Schottky), which is reverse biased by the application of drain voltage. Charge injection is modulated via the gate/source overlap, producing very low saturation voltage and ultra-low output conductance gd [3]. This latter feature yields the distinctive and extremely high intrinsic gain observed in such devices. A large voltage drop occurs across the source depletion region, producing the notable early saturation and, consequently, the channel potential is maintained at a value close to the drain potential for operating conditions in which a conventional TFT would still be working in the linear region. As such, when a floating gate is used in a SGT, the FG couples strongly to both the drain and the channel. FG potential varies considerably with drain voltage, thus increasing charge injection along the source, ultimately raising gd . While gd is still orders of magnitude lower than that of a TFT or FG TFT (see Figure 1), many analog applications would benefit from a solution to this problem [1].Here, we present a staggered-electrode contact-controlled device, the multimodal transistor (MMT), which shares SGT charge injection principles, however the switching mechanism of its channel is controlled by a separate gate [6]. In a FG MMT, the source gate responsible for charge injection and channel switching gate are designed as FGs (FG1 and FG2, respectively) and a main control gate (CG) may overlap both FGs. FG MMTs have been fabricated in low T°C technology [6] with Ni source and drain contacts. ICP-CVD (Inductively Coupled Plasma Chemical Vapour Deposition) via the Corial 210D reactor was used to deposit µ-Si as active layer, as well as the insulators of the gate stack (Figure 1a). Temperature never exceeded 250°C in any of the processing steps.The MMT exhibits the same high-gain properties of the SGT and preserves it even in FG configuration. With the channel and drain potentials coupling to FG2, its potential is raised significantly higher than FG1 (see Figures 1b and 1c for TCAD simulation with Silvaco Atlas), which is effectively shielded. As charge injection is exclusively modulated by FG1, the low saturation and extremely low gd are maintained, in contrast to the FG SGT (see Figure 1c). Thus, extremely high gain can be obtained from the FG MMT structure, with a wide range of applicability to traditional analog applications such as displays and sensors, as well as emerging neuromorphic circuits.Figure. 1 a) Photomicrograph of a µ-Si floating gate MMT (FG MMT); b) FG2 potential is significantly raised, while FG1 is shielded from parasitic capacitive coupling from the channel and drain potential, keeping charge injection at the source constant with drain voltage. c) Output conductance gd comparison confirms FG MMT gd is significantly lower than that of the equivalent FG SGT.