Thin-film Transistor Architecture Research Articles

Trench-Structured High-Current-Driving Aluminum-Doped Indium–Tin–Zinc Oxide Semiconductor Thin-Film Transistor

This letter presents a thin-film transistor architecture, in which a “trench” is introduced between the source and drain electrode to enhance current flow. The top-gate top-contact oxide Trench thin-film transistor has a superior on-current per width of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$27.7~\mu \text{A}/ \mu \text{m}$ </tex-math></inline-formula> at a drain voltage of 4.1 V. It also has a good subthreshold swing of 0.122 V/dec and turn-on voltage of −0.4 V. This study explores the operating mechanism of the high-current-driving Trench oxide thin-film transistor.

On–off ratio improvement in organic electrochemical transistors from addition of a PMMA layer at the electrolyte dielectric/semiconductor interface

The high capacitance from an electrolyte dielectric layer used in a thin film transistor architecture results in the development of electrolyte-gated organic field effect transistors (EGOFETs), which are able to operate at lower voltages compared with the commonly organic field effect transistors. When ions diffuse into the semiconductor, changing its conductive properties, the resulting devices are named organic electrochemical transistors (OECTs). In this case, an increase in channel conductivity occurs due to ionic doping. Depending on the gate voltage range operation, it is possible to obtain a de-doping process, suitable for achieving a low off-current. In this work, a simple and easy method is proposed based on an additional dielectric layer deposition of poly(methyl methacrylate) at the electrolyte dielectric/semiconductor interface, which provides: (i) good efficiency to block the diffusion of anions into the channel, resulting in an EGOFET for a gate voltage range up to −0.6V and (ii) an improvement in the on–off ratio in approximately three orders of magnitude for OECTs due to the low off-current obtained without promoting ionic de-doping in the channel, for a gate voltage range up to −1.1V. Both modes of operation were obtained in the same transistor structure. In addition, parameters such as field effect mobility, on–off ratio, and threshold voltage were also estimated for different transistor structures and gate voltage ranges.

Total Gain Recovery in Floating Gate Thin-Film Transistors for Neuromorphic and Edge Computing

We propose a floating-gate (FG) thin-film transistor architecture which alleviates a significant limitation present since the inception of FG field-effect transistors, namely the loss of gain due to parasitic capacitive coupling on the FG [1].The interest in large area electronics has grown beyond traditional applications, such as display and sensing arrays, with recent trends including neuromorphic and edge computing. However, the challenges of fabricating robust thin film transistor (TFT) circuits have remained despite the many significant achievements in material systems and process development. In order to realise the full benefit of low-cost, high-throughput manufacturing methods, device shortcomings need to be addressed [2]. In FG devices, specifically, one major limitation is the degradation of gain compared to conventional devices, as a result of capacitive coupling of the channel and drain potentials to the floating gate. The problem is far more severe in contact-controlled TFTs, such as the staggered-electrode, high-gain source-gated transistor (SGT) [3, 4], and crippling in conventional TFTs manufactured in materials such as InGaZnO [5].SGT operation differs from conventional field-effect TFTs, whereby the semiconductor is fully depleted at the source edge by an energy barrier (e.g. Schottky), which is reverse biased by the application of drain voltage. Charge injection is modulated via the gate/source overlap, producing very low saturation voltage and ultra-low output conductance gd [3]. This latter feature yields the distinctive and extremely high intrinsic gain observed in such devices. A large voltage drop occurs across the source depletion region, producing the notable early saturation and, consequently, the channel potential is maintained at a value close to the drain potential for operating conditions in which a conventional TFT would still be working in the linear region. As such, when a floating gate is used in a SGT, the FG couples strongly to both the drain and the channel. FG potential varies considerably with drain voltage, thus increasing charge injection along the source, ultimately raising gd . While gd is still orders of magnitude lower than that of a TFT or FG TFT (see Figure 1), many analog applications would benefit from a solution to this problem [1].Here, we present a staggered-electrode contact-controlled device, the multimodal transistor (MMT), which shares SGT charge injection principles, however the switching mechanism of its channel is controlled by a separate gate [6]. In a FG MMT, the source gate responsible for charge injection and channel switching gate are designed as FGs (FG1 and FG2, respectively) and a main control gate (CG) may overlap both FGs. FG MMTs have been fabricated in low T°C technology [6] with Ni source and drain contacts. ICP-CVD (Inductively Coupled Plasma Chemical Vapour Deposition) via the Corial 210D reactor was used to deposit µ-Si as active layer, as well as the insulators of the gate stack (Figure 1a). Temperature never exceeded 250°C in any of the processing steps.The MMT exhibits the same high-gain properties of the SGT and preserves it even in FG configuration. With the channel and drain potentials coupling to FG2, its potential is raised significantly higher than FG1 (see Figures 1b and 1c for TCAD simulation with Silvaco Atlas), which is effectively shielded. As charge injection is exclusively modulated by FG1, the low saturation and extremely low gd are maintained, in contrast to the FG SGT (see Figure 1c). Thus, extremely high gain can be obtained from the FG MMT structure, with a wide range of applicability to traditional analog applications such as displays and sensors, as well as emerging neuromorphic circuits.Figure. 1 a) Photomicrograph of a µ-Si floating gate MMT (FG MMT); b) FG2 potential is significantly raised, while FG1 is shielded from parasitic capacitive coupling from the channel and drain potential, keeping charge injection at the source constant with drain voltage. c) Output conductance gd comparison confirms FG MMT gd is significantly lower than that of the equivalent FG SGT.

N-type to p-type transition upon phase change in Ge6Sb1Te2 compounds

In this work, we study the electronic properties of Ge6Sb1Te2 compounds in thin-film transistor architectures on plastic substrates, which enable the extraction of field-effect mobility μFE, carrier density, and polarity in highly resistive thin-films. We find that the Ge-rich compound exhibits n-type conductivity in the amorphous phase with a gradual transition to p-type behavior upon thermal annealing. At a temperature of 350 °C, the material undergoes a phase change, which is confirmed by x-ray diffraction measurements. After the phase change, μFE and the conductivity increase and the polarity becomes p-type, while the carrier density does not change significantly. Furthermore, we compare the properties of Ge6Sb1Te2 to the commonly studied material composition of Ge2Sb2Te5 in the Hall measurement and find that the carrier density of the Ge-rich compound is reduced by 2 orders of magnitude, which indicates that the significantly lower concentration of Ge vacancies leads to a reduction of p-type doping.

Indirect X-ray Detectors Based on Inkjet-Printed Photodetectors with a Screen-Printed Scintillator Layer.

Organic photodetectors (PDs) based on printing technologies will allow to expand the current field of PD applications toward large-area and flexible applications in areas such as medical imaging, security, and quality control, among others. Inkjet printing is a powerful digital tool for the deposition of smart and functional materials on various substrates, allowing the development of electronic devices such as PDs on various substrates. In this work, inkjet-printed PD arrays, based on the organic thin-film transistor architecture, have been developed and applied for the indirect detection of X-ray radiation using a scintillator ink as an X-ray absorber. The >90% increase of the photocurrent of the PDs under X-ray radiation, from about 53 nA without the scintillator film to about 102 nA with the scintillator located on top of the PD, proves the suitability of the developed printed device for X-ray detection applications.

3-D Dual-Gate Photosensitive Thin-Film Transistor Architectures Based on Amorphous Silicon

In contrast to the conventional planar p-i-n photodiode and a metal-semiconductor–metal photodetector, the 3-D dual-gate photosensitive thin-film transistor (TFT) architectures presented here attain excellent photoresponse characteristics. Operating the device in the subthreshold regime further boosts the photoconductive gain as a result of light-induced decrease in the threshold voltage. This paper presents design considerations along with a performance comparison between 3-D photosensitive TFTs that have $\pi $ - and FIN-shaped channels and conventional TFT with a planar channel. Our paper shows that the $\pi $ -shaped structure tends to have a higher sensitivity while the FIN-shaped counterpart is more responsive with wider dynamic range. For both structures, a measured photoconductive gain of $10^{\textsf {4}} \sim 10^{\textsf {6}}$ % is obtained with spectral responsivity ranging from near UV to near IR, and the photoresponse time in the range of tens of milliseconds. The 3-D dual-gate photosensitive TFT architecture appears to be very promising for large-area, low-level UV, visible, and IR detection applications.

Wavy Architecture Thin-Film Transistor for Ultrahigh Resolution Flexible Displays.

A novel wavy-shaped thin-film-transistor (TFT) architecture, capable of achieving 70% higher drive current per unit chip area when compared with planar conventional TFT architectures, is reported for flexible display application. The transistor, due to its atypical architecture, does not alter the turn-on voltage or the OFF current values, leading to higher performance without compromising static power consumption. The concept behind this architecture is expanding the transistor's width vertically through grooved trenches in a structural layer deposited on a flexible substrate. Operation of zinc oxide (ZnO)-based TFTs is shown down to a bending radius of 5 mm with no degradation in the electrical performance or cracks in the gate stack. Finally, flexible low-power LEDs driven by the respective currents of the novel wavy, and conventional coplanar architectures are demonstrated, where the novel architecture is able to drive the LED at 2 × the output power, 3 versus 1.5 mW, which demonstrates the potential use for ultrahigh resolution displays in an area efficient manner.

Flexible Transparent Field‐Effect Diodes Fabricated at Low‐Temperature with All‐Oxide Materials

Flexible fully transparent diodes with high rectification ratio of 5 × 108 are fabricated with all-oxide materials at low temperature. The devices are optically transparent in the visible spectra range and electrically robust under mechanically bending. Distinguished from other diodes, these diodes utilize diode-connected thin-film transistor architecture and follow field-effect principles.

Monolithic metal oxide transistors.

We devised a simple transparent metal oxide thin film transistor architecture composed of only two component materials, an amorphous metal oxide and ion gel gate dielectric, which could be entirely assembled using room-temperature processes on a plastic substrate. The geometry cleverly takes advantage of the unique characteristics of the two components. An oxide layer is metallized upon exposure to plasma, leading to the formation of a monolithic source-channel-drain oxide layer, and the ion gel gate dielectric is used to gate the transistor channel effectively at low voltages through a coplanar gate. We confirmed that the method is generally applicable to a variety of sol-gel-processed amorphous metal oxides, including indium oxide, indium zinc oxide, and indium gallium zinc oxide. An inverter NOT logic device was assembled using the resulting devices as a proof of concept demonstration of the applicability of the devices to logic circuits. The favorable characteristics of these devices, including (i) the simplicity of the device structure with only two components, (ii) the benign fabrication processes at room temperature, (iii) the low-voltage operation under 2 V, and (iv) the excellent and stable electrical performances, together support the application of these devices to low-cost portable gadgets, i.e., cheap electronics.

Design freedom in multilayer thin-film devices.

In fabricating inorganic thin-film devices, the relative etch rates of materials in a given etch chemistry often limit the obtainable multilayer structures. Alternatively, in fabricating multilayer organic devices by solution processing, the ability to formulate the active organic materials in orthogonal solvent systems is limiting. The pattered-by-printing method uses the combination of selective area deposition (SAD) and atomic layer deposition (ALD) to form high-quality metal oxide thin-film devices. We print an inhibiting polymer ink that patterns the functional inorganic materials that are deposited via spatial ALD (SALD). The process is inherently orthogonal, as the polymer ink does not etch or swell the inorganic functional layers. Each functional layer is additively patterned as deposited, with device isolation and vias defined by the printed inhibitor. The combination of process orthogonality and additive patterning removes processing-related constraints on device design, and readily allows for any combination of bottom- and top-gate thin-film transistor architectures to be formed on the same substrate. The freedom of this approach is further demonstrated by both all-enhancement-mode circuits and enhancement-depletion-mode circuits. In addition, we present a new tool to tune circuit performance by local control of dielectric thickness.

Wavy channel thin film transistor architecture for area efficient, high performance and low power displays

AbstractWe demonstrate a new thin film transistor (TFT) architecture that allows expansion of the device width using continuous fin features – termed as wavy channel (WC) architecture. This architecture allows expansion of transistor width in a direction perpendicular to the substrate, thus not consuming extra chip area, achieving area efficiency. The devices have shown for a 13% increase in the device width resulting in a maximum 2.5× increase in ‘ON’ current value of the WCTFT, when compared to planar devices consuming the same chip area, while using atomic layer deposition based zinc oxide (ZnO) as the channel material. The WCTFT devices also maintain similar ‘OFF’ current value, ∼100 pA, when compared to planar devices, thus not compromising on power consumption for performance which usually happens with larger width devices. This work offers an interesting opportunity to use WCTFTs as backplane circuitry for large‐area high‐resolution display applications. (© 2014 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Sub-threshold current in organic thin film transistors: Influence of the transistor layout

This paper highlights an intrinsic difference between organic thin film transistor architectures, namely planar and staggered structures, using a numerical drain current model. From simulation results it is demonstrated that the transistor structure in itself impacts the sub-threshold slope, the onset voltage and the threshold voltage. This is due to the location of the source contact with respect to the accumulation layer. The potential profile induced in the device by the gate–source voltage differs in planar or staggered architectures, and the gate control is shown to be much more efficient in the planar configuration. This paper describes in detail the electrical behavior of both OTFT configurations, based on numerical simulations.

Dual-gate organic thin film transistors as chemical sensors

An organic/inorganic hybrid sensing device is proposed based on a dual-gate organic thin film transistor architecture using polythiophenes as semiconductors and AlOx as the top dielectric. When a polar molecule adsorbs on the top dielectric, the threshold voltage of the bottom gate transistor shifts leading to several orders of magnitude increase of the current at an appropriately chosen gate voltage. The devices are tested by exposing them to a saturated water atmosphere, which leads to a four orders of magnitude current increase within one minute. This sensor design maintains some advantages of organic semiconductors such as low-temperature processing and fabrication on flexible substrates. Finally, it can be operated at low voltages with the potential for extremely low-power operation.

A new laser-processed polysilicon TFT architecture

A new top gate polysilicon thin-film transistor (TFT) architecture is introduced which requires only a single laser process step to simultaneously crystallize the channel and activate the source-drain. The dummy-gate TFT (DGTFT) uses a light blocking layer patterned with the gate mask combined with two backside expose steps to allow a self-aligned device structure. N-channel TFTs fabricated using the new process have field effect mobilities greater than 100 cm/sup 2//Vs. By controlling the backside exposures it is also possible to form offset or graded doping structures to reduce field enhanced leakage currents.