Abstract
This paper highlights an intrinsic difference between organic thin film transistor architectures, namely planar and staggered structures, using a numerical drain current model. From simulation results it is demonstrated that the transistor structure in itself impacts the sub-threshold slope, the onset voltage and the threshold voltage. This is due to the location of the source contact with respect to the accumulation layer. The potential profile induced in the device by the gate–source voltage differs in planar or staggered architectures, and the gate control is shown to be much more efficient in the planar configuration. This paper describes in detail the electrical behavior of both OTFT configurations, based on numerical simulations.
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