Thin-film Thermoelectric Coolers Research Articles

Co-optimization of electrical-thermal–mechanical behaviors of an on-chip thermoelectric cooling system using response surface method

Thin-film thermoelectric coolers (TFTECs) have emerged as a potentially optimal solution for on-chip cooling. Most previous optimization studies have focused on improving the cooling performance of TFTECs. However, a fully functional and robust TFTEC requires a combination of performance, reliability, and power consumption in 3D integration with comprehensive consideration of electrical-thermal–mechanical coupling effects. In this work, a system-level co-optimization of an on-chip thermoelectric cooling system is performed using an electrical-thermal–mechanical coupling model. Response surface method is used to obtain predictive models to evaluate the performance of TFTEC with respect to leg height, electrode height, electrical and thermal contact resistances. The interactions between the design factors and their effects on device resistance, active cooling, and thermal stress are investigated. The results reveal that electrode height is the most critical factor affecting device resistance and active cooling. Leg height is the most important factor affecting maximum thermal stress. Based on multi-objective optimization, the optimal configuration of design factors is obtained. A device resistance of 5.75Ω, active cooling of 3.8°C, and thermal stress of 1646.2MPa can be achieved simultaneously. Compared to the initial configuration, device resistance is increased by 4.9%, active cooling is increased by 111%, and thermal stress is reduced by 3.4%.

The Transient Cooling Performance of a Compact Thin-Film Thermoelectric Cooler with Horizontal Structure

Thermoelectric cooling is an ideal solution for chip heat dissipation due to its characteristics of no refrigerant, no vibration, no moving parts, and easy integration. Compared with a traditional thermoelectric device, a thin-film thermoelectric device significantly improves the cooling density and has tremendous advantages in the temperature control of electronic devices with high-power pulses. In this paper, the transient cooling performance of a compact thin-film thermoelectric cooler with a horizontal structure was studied. A 3D multi-physics field numerical model with the Thomson effect considered was established. And the effects of impulse current, thermoelectric leg length, pulse current imposition time, and the size of the contact thermal resistance on the cooling performance of the device were comprehensively investigated. The results showed that the model achieved an active cooling temperature difference of 25.85 K when an impulse current of 0.26 A was imposed. The longer the length of the thermoelectric leg was, the more unfavorable it was to the chip heat dissipation. Due to the small contact area between different sections of the device, the effect of contact thermal resistance on the cooling performance of the device was moderate.

A novel cascaded thin-film thermoelectric cooler for on-chip hotspot cooling

Thin-film thermoelectric coolers (TFTECs) are a potential solution for on-chip thermal management of power devices. However, substrate heat leakage, large TE leg resistance, and low integration level can degrade the performance of in-plane TFTECs, making it difficult to achieve large cooling temperature differences. Serious challenges still remain in the structural engineering of in-plane TFTECs, which need to be improved to fully exert the cooling performance. In this work, a novel cascaded in-plane TFTEC based on a flexible polyimide substrate is proposed to achieve high-efficiency on-chip hotspot cooling. The device is designed with a radial structure to increase the heat absorption area ratio. Two cascade rings are used to divide the device into three stages to enhance the heat flow in the planar direction and to further increase the number of legs and the cold end area. The effects of substrate thickness, cascade material, electrode height and leg height on the cooling performance are analyzed using the finite element method. When the substrate thickness is 25 μm, the electrode height is 5 μm, and the leg height is 5 μm, the cascaded in-plane TFTEC can achieve a minimum cooling temperature of −44.6 °C and a maximum cooling temperature difference of 69.6 °C at a current of 25 mA. The effect of contact resistance is limited to 4 % since the planar configuration can provide large-area contact.

Performance assessment and optimization of a thin-film thermoelectric cooler for on-chip transient thermal management

On-demand cooling of thin-film thermoelectric cooler (TFTEC) is a promising technique for energy-saving and high efficiency. However, the transient cooling process of TFTEC is complex and systematic, involving temperature-dependent material properties, geometry factors, parasitic parameters and control parameters. In this work, a system-level optimization of the on-chip transient thermal management (TTM) performance of a Bi2Te3-based TFTEC is performed using a transient three-dimensional numerical model. The response surface method is applied to obtain a predictive model for evaluating the transient cooling performance of TFTEC in terms of four different design factors of thermoelectric leg height, electrode height, current pulse width and amplitude. The relationships between the above design factors and responses including passive cooling, active cooling, temperature overshoot, and time delay and their interactive effects are investigated. Finally, single- and multi-objective optimizations are employed to optimize these responses in different scenarios. The results show that the TFTEC with the optimal configuration enables a passive cooling of 15.57 °C and an active cooling of 5.85 °C simultaneously for a chip hotspot with a transient heat flux of 1300 W/cm2. Furthermore, the hotspot temperature can be limited to 7.15℃ lower than the predefined temperature limit, while the high-power pulse loading time can be extended by 690.2 ms.

A system level optimization of on-chip thermoelectric cooling via Taguchi-Grey method

In this paper, a framework for the system level optimization of the thin-film thermoelectric cooler (TFTEC) in 3D electronic packaging is developed based on Taguchi-Grey method. The influences of the size effect, the geometric effect, the parasitic effect and the localized hotspot are comprehensively considered. An L25 (56) orthogonal array is employed to assess the influences of the leg height, the fill-ratio, the electrode height, the gap distance, the hotspot size and the hotspot heat flux on the passive and active cooling effects of the TFTEC. The results show that the electrode height, acting as the primary factor, contributes 45.5% and 45.3% on the passive cooling and active cooling, respectively. The contribution ratios of hotspot size and hotspot heat flux to passive cooling reach 21.4% and 14.7%, respectively. The contribution ratios of leg height and gap distance to active cooling reach 25.7% and 18.8%, respectively. The optimum design factors for maximizing the cooling effects are also approached by the Grey relational analysis. A passive cooling of 16.82 °C and a maximum active cooling of 12.29 °C are achieved, leading to a total localized cooling of 29.11 °C for a chip hotspot.

The simulated cooling performance of a thin-film thermoelectric cooler with coupled-thermoelements connected in parallel

The thermoelements of the traditional thin-film thermoelectric cooler (TEC) are connected electrically in series, thus the performance of traditional thin-film TEC reduces sharply when there is something wrong with any thermoelement. On account of this deficiency, we proposed a novel thin-film TEC with a couple of thermoelements electrically connected in parallel and then electrically connected in series to the next couple of thermoelements. The performance and reliability of the novel thin-film TEC is compared with the traditional thin-film TEC. The maximum cooling capacity, the maximum cooling temperature, and the coefficient of performance of the novel and the traditional thin-film TEC are systematically studied and compared when 0, 2, and 4 thermoelements are disabled, respectively. The results show that the performance and reliability of the novel thin-film TEC are superior to that of the traditional thin-film TEC, while the optimal electric current of the novel thin-film TEC current is 2.14 times of that for the traditional thin-film TEC. This work is of great significance to improving the performance and reliability of thin-film thermoelectric devices consisting of dozens of small thermoelements.

A Strategy to Reduce the Peak Temperature of the Chip Working under Dynamic Power Using the Transient Cooling Effect of the Thin-Film Thermoelectric Cooler

A Strategy to Reduce the Peak Temperature of the Chip Working under Dynamic Power Using the Transient Cooling Effect of the Thin-Film Thermoelectric Cooler

Optimization of Interface Materials between Bi2Te3-Based Films and Cu Electrodes Enables a High Performance Thin-Film Thermoelectric Cooler.

Thermoelectric interface materials (TEiMs) are key to optimizing the electrical contact and stability of the interface between thermoelectric material and metal electrode in high-performance thin-film thermoelectric coolers (TECs). Herein, we explored TEiMs applicable to representative Bi-Te films and found that Cr and Ag are effective TEiMs for p-type Bi0.5Sb1.5Te3 and n-type Bi2Te3, respectively. By introducing 200 nm Cr and 200 nm Ag as TEiMs for p-type Bi0.5Sb1.5Te3/Cu and n-type Bi2Te3/Cu interfaces, Cu diffusion is suppressed, and excellent electrical contact is achieved (1.81 × 10-12 Ω m2 for p-type and 3.32 × 10-12 Ω m2 for n-type) and remains stable after heat treatment (2.37 × 10-12 Ω m2 for p-type and 1.63 × 10-12 Ω m2 for n-type). Furthermore, the cooling flux of TECs with optimized TEiMs increases from 122.74 to 296.56 W/cm2, while the performance degradation caused by contact resistance decreases from 50.81 to 4.15%. In addition, our results show that diffusion occurs between not only Cu but also Ag and the thermoelectric material, as TEiMs diffuse slightly. The diffusion of Cu and Ag at the interface can optimize the electrical contact of Bi2Te3/Cu but strongly degrade the electrical contacts of Bi0.5Sb1.5Te3/Cu. Our work provides an optimal selection of TEiMs for high-performance Bi-Te thin film coolers and provides guidance for further miniaturization of devices.

Electrodeposited Thin-Film Micro-Thermoelectric Coolers with Extreme Heat Flux Handling and Microsecond Time Response.

Thin-film thermoelectric coolers are emerging as a viable option for the on-chip temperature management of electronic and photonic integrated circuits. In this work, we demonstrate the record heat flux handling capability of electrodeposited Bi2Te3 films of 720(±60) W cm-2 at room temperature, achieved by careful control of the contact interfaces to reduce contact resistance. The characteristic parameters of a single leg thin-film devices were measured in situ, giving a Seebeck coefficient of S = -121(±6) μV K-1, thermal conductivity of κ = 0.85(±0.08) W m-1 K-1, electrical conductivity of σ = 5.2(±0.32) × 104 S m-1, and electrical contact resistivity of ∼10-11 Ω m2. These thermoelectric parameters lead to a material ZT = 0.26(±0.04), which, for our device structure, allowed a net cooling of ΔTmax = 4.4(±0.12) K. A response time of τ = 20 μs was measured experimentally. This work shows that with the correct treatment of contact interfaces, electrodeposited thin-film thermoelectrics can compete with more complicated and expensive technologies such as metal organic chemical vapor deposition (MOCVD) multilayers.

Effect of Thermoelectric Leg Thickness in a Planar Thin Film TEC Device on Different Substrates

Recently, mobile application processors (APs) have suffered from thermal issues such as local hot spot generation. Several approaches for chip cooling, such as dynamic thermal management, and heat pipe cooling, have been attempted so far, but, these solutions cannot completely eliminate increasing thermal issues. Therefore, in this study, we fabricated a planar type of thin film thermoelectric cooler (TEC) as an active cooling device for a mobile AP chip. We studied the effect of thickness on a planar thin film TEC device related to Joule heating and demonstrated the Peltier cooling effect on polyimide (PI) and Si substrates. The optimal thicknesses of n-type Bi2Te3 and p-type Sb2Te3 films were evaluated by ANSYS® simulation, and are 5.05 μm and 5.45 μm, respectively. It was shown that heat moves to the TE leg on the PI substrate, while the Si substrate serves as a heat sink according to the IR thermography analysis. The optimal thickness of the TE showed a temperature difference between the cold junction and hot junction up to 1.3 °C.

Recent development and application of thin-film thermoelectric cooler

Recently, the performance and fabrication of thin-film thermoelectric materials have been largely enhanced. Based on this enhancement, the thin-film thermoelectric cooler (TEC) is becoming a research hot topic, due to its high cooling flux and microchip level size. To fulfill a thin-film TEC, interfacial problems are unavoidable, as they may largely reduce the properties of a thin-film TEC. Moreover, the architecture of a thin-film TEC should also be properly designed. In this review, we introduced the enhancement of thermoelectric properties of (Bi,Sb)2(Te,Se)3 solid solution materials by chemical vapor deposition, physical vapor deposition and electrodeposition. Then, the interfacial problems, including contact resistance, interfacial diffusion and thermal contact resistance, were discussed. Furthermore, the design, fabrication, as well as the performance of thin-film TECs were summarized.

Strikingly enhanced cooling performance for a micro-cooler using unique Cu nanowire array with high electrical conductivity and fast heat transfer behavior

It was found that phonons/electrons are less scattered along (111)-preferred Cu nanowires than in ordinary structure films and that the interface of Cu nanowires electrode and thermoelectric materials are more compatible. Here highly ordered, high-crystal-quality, high-density Cu nanowire array was successfully fabricated by a magnetron sputtering method. The Cu nanowire array was successfully incorporated using mask-assisted deposition technology as electrodes for thin-film thermoelectric coolers, which would greatly improve electrical/thermal transport and enhance performance of micro-coolers. The cooling performance of the micro-cooler with Cu nanowire array electrode is over 200% higher than that of the cooler with ordinary film electrode.

Construction of a 3D porous network of copper film via a template-free deposition method with superior mechanical and electrical properties for micro-energy devices

With the ever increasing level of performance of energy conversion micro-devices, such as thin-film solar cells and thermoelectric micro-generators or coolers, their reliability and stability still remain a challenge. The high electrical and mechanical stability of an electrode is two of the critical factors that affect the long-term life of devices. Here we show that these factors can be achieved by constructing a 3D porous network of nanostructures in copper film using facile magnetron sputtering technology without any templates. The constructed 3D porous network of nanostructures in Cu film provides not only the advantages of light weight, prominently high conductivity, and large elastic deformation, but also the ability to absorb stress, preventing crack propagation, which is crucial for electrodes to maintain stable electrical and mechanical properties under working conditions. The nanopores inside the 3D network are capable of unrestrained deformation under applied stress resulting in strong elastic recovery. This work puts forward a feasible solution for manufacturing electrodes with excellent electrical and mechanical properties for micro-energy devices.

Preparation of thermoelectric thin film material and numerical simulation of cooler

Low dimensional thermoelectric materials and the trend of miniaturization of devices as well as the application in the field of aerospace were discussed. Then the thermoelectric thin film material was fabricated on the polymide( PI) flexible substrate using magnetron sputtering method. The microstructure and property of thin film materials were characterized. The results show that the P-type Bi-Sb-Te and N-type Bi-Te-Se all have a preferential growth of( 015) plane. The numerical simulation was also conducted on the in-plane thin film thermoelectric cooler by ANSYS finite element simulation software. The effect of working current and material physical property parameter on the cooling performance was discussed. It reveals that increasing the thermal resistance of substrate in plane by the decrease of thermal conductivity and thickness benefits the directional thermal flow along the thermoelectric legs. Besides,the hollowed design of substrate and the introduction of high thermal conductive layer in cooling area facilitate the establishment of cooling temperature difference and the uniform cooling in the cooling area. These results provide guidance for the preparation of thin film devices.

Non-contact method for characterization of small size thermoelectric modules.

Conventional techniques for characterization of thermoelectric performance require bringing measurement equipment into direct contact with the thermoelectric device, which is increasingly error prone as device size decreases. Therefore, the novel work presented here describes a non-contact technique, capable of accurately measuring the maximum ΔT and maximum heat pumping of mini to micro sized thin film thermoelectric coolers. The non-contact characterization method eliminates the measurement errors associated with using thermocouples and traditional heat flux sensors to test small samples and large heat fluxes. Using the non-contact approach, an infrared camera, rather than thermocouples, measures the temperature of the hot and cold sides of the device to determine the device ΔT and a laser is used to heat to the cold side of the thermoelectric module to characterize its heat pumping capacity. As a demonstration of the general applicability of the non-contact characterization technique, testing of a thin film thermoelectric module is presented and the results agree well with those published in the literature.

Control Principles and On-Chip Circuits for Active Cooling Using Integrated Superlattice-Based Thin-Film Thermoelectric Devices

Superlattice thin-film thermoelectric coolers (TECs) are emerging as a promising technology for hot spot mitigation in microprocessors. This paper studies the prospect of on-demand cooling with advanced TECs integrated at the back of the heat spreader inside a package (integrated TEC). Using thermal compact models of the chip and package with integrated TECs, the control principles for TEC-assisted transient cooling are presented. The control principles are implemented in a 130-nm CMOS process and cosimulated with the thermal system to show their feasibility and energy overheads. The simulation results show potential for extending the time for which a chip and package can sustain a high power load.

Sensitivity analysis and optimization of thin-film thermoelectric coolers

The cooling performance of a thermoelectric (TE) material is dependent on the figure-of-merit (ZT = S2σT/κ), where S is the Seebeck coefficient, σ and κ are the electrical and thermal conductivities, respectively. The standard definition of ZT assigns equal importance to power factor (S2σ) and thermal conductivity. In this paper, we analyze the relative importance of each thermoelectric parameter on the cooling performance using the mathematical framework of sensitivity analysis. In addition, the impact of the electrical/thermal contact parasitics on bulk and superlattice Bi2Te3 is also investigated. In the presence of significant contact parasitics, we find that the carrier concentration that results in best cooling is lower than that of the highest ZT. We also establish the level of contact parasitics that are needed such that their impact on TE cooling is negligible.

Thermoreflectance imaging of sub 100 ns pulsed cooling in high-speed thermoelectric microcoolers

Miniaturized thin film thermoelectric coolers have received considerable attention as potential means to locally address hot spots in microprocessors. Given the highly dynamic workload in complex integrated circuits, the need arises for a thorough understanding of the high-speed thermal behavior of microcoolers. Although some prior work on transient Peltier cooling in pulsed operation is available, these studies mostly focus on theoretical modeling and typically deal with relatively large modules with time constants well into the millisecond range. In this paper, we present an extensive experimental characterization of 30×30 μm2 high-speed coplanar SiGe superlattice microcoolers subjected to 300 ns wide current pulses at ≈ 300 kHz repetition rate. Using thermoreflectance imaging microscopy, we obtain 2D maps of the transient surface temperature and constituent Peltier and Joule components over the 50–750 ns time range with submicron spatial and 50 ns temporal resolutions. Net cooling of 1 K–1.5 K is achieved within 100–300 ns, well over an order of magnitude faster compared to previous reports on microcoolers in high-speed operation. We also point out ambiguities in separating Peltier and Joule signals during the device turn-off. Overall, our measurements provide substantial insight into ultrafast turn-on and turn-off dynamics in thin film thermoelectrics.

A Design of Thin Film Thermoelectric Cooler for Chip-on-Board(COB) Assembly

A thin film thermoelectric cooler for COB direct assembly was proposed and the COB cooler structure was modeled by electrical equivalent circuit by using SPICE model of thermoelectric devices. The embedded cooler attached between the die chip and metal plate can offer the possibility of thin film active cooling for the COB direct assembly. We proposed a driving method of TEC by using pulse width modulation technique. The optimum power to the TEC is simulated by using a SPICE model of thermoelectric device and passive components representing thermal resistance and capacitance. The measured and simulated results offer the possibility of thin film active cooling for the COB direct assembly.

A thin film thermoelectric cooler for Chip-on-Board assembly

We have proposed and demonstrated an embedded thin film thermoelectric cooler attached between die chip and metal plate for Chip-on-Board (COB) direct assembly. The proposed structure of COB cooler was modeled by electrical equivalent circuit for SPICE simulation including operational heat generation of chip and PWM control of input power supply. The optimum input power of the TEC to achieve maximum temperature difference between chip and heat sink was simulated by using the proposed equivalent circuit. The measured and simulated results offer the possibility of thin film active cooling for COB direct assembly.