Si Film Thickness Research Articles

Interfacial phonon scattering and transmission loss in >1 µm thick silicon-on-insulator thin films

Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter $p$ formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. To better understand the interfacial scattering of phonons and to test the validity of Ziman's theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1--10 \ensuremath{\mu}m and a temperature range of 100--300 K. The $\mathrm{Si}/{\mathrm{SiO}}_{2}$ interface roughness was determined to be $0.11\ifmmode\pm\else\textpm\fi{}0.04\phantom{\rule{0.16em}{0ex}}\mathrm{nm}$ using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. We derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.

Effect of the thickness of Si film on Si/Se film doped silicon prepared by femtosecond laser

The high infrared absorption of silicon could be achieved by doping silicon with chalcogens via femtosecond laser. In the paper, the samples of Se-doped silicon with different thickness of Si film were prepared with the aid of femtosecond laser. The effect of the thickness of silicon film on optical and the electrical properties of se-doped silicon is investigated. All the samples were thermally annealed at 500 °C for 1 h, and the absorptance of all the samples was found with a certain degree of reduction. With the increase of thickness of silicon film, the results of visible-near infrared spectrum showed that the infrared absorptance increased first and then decreased. In particular, the optical absorption, sheet carrier density and responsivity for samples prepared with the silicon film that was 300 nm thick were greater than that of the samples prepared with the Si films of other thickness. The experiment demonstrated that it is significant to select the silicon film of appropriate thickness in the fabrication of Se doped silicon.

Enhanced spin Hall effect of reflected light with guided-wave surface plasmon resonance

The photonic spin Hall effect (SHE) has been intensively studied and widely applied, especially in spin photonics. However, the SHE is weak and is difficult to detect directly. In this paper, we propose a method to enhance SHE with the guided-wave surface-plasmon resonance (SPR). By covering a dielectric with high refractive index on the surface of silver film, the photonic SHE can be greatly enhanced, and a giant transverse shift of horizontal polarization state is observed due to the evanescent field enhancement near the interface at the top dielectric layer and air. The maximum transverse shift of the horizontal polarization state with 11.5 μm is obtained when the thickness of Si film is optimum. There is at least an order of magnitude enhancement in contrast with the transverse shift in the conventional SPR configuration. Our research is important for providing an effective way to improve the photonic SHE and may offer the opportunity to characterize the parameters of the dielectric layer with the help of weak measurements and development of sensors based on the photonic SHE.

Degradation induced by TID radiation and hot-carrier stress in 130-nm short channel PDSOI NMOSFETs

Hot-carrier reliability for devices operating in radiation environment must be considered. In this paper, we investigate how total ionizing dose impacts the hot-carrier reliability of partially-depleted SOI I/O NMOSFETs, highlighting the effect of buried oxide. Firstly, radiation-induced damage on short channel SOI devices with 100nm thick Si film was investigated. After low total dose irradiation, incomplete fully-depleted state has been formed due to the non-uniformly distributed positive charges in the buried oxide. Furthermore, as the dominated factor of hot-carrier injection, the body current reduces after irradiation. Subsequently, the irradiated SOI devices were subjected to hot-carrier stress for 9000-s long time. Compared with unirradiated devices, the irradiated samples display enhanced hot-carrier degradation. We attribute this phenomenon to that radiation lowers the barrier for hot-carrier injection. Therefore, in order to ensure the reliability of SOI devices operating in harsh radiation environments, SOI devices with higher quality or corresponding hardness design should be taken.

Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

Two-dimensional (2D) analytical models for the subthreshold current and␣subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable␣boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

Deterministic composite nanophotonic lattices in large area for broadband applications.

Exotic manipulation of the flow of photons in nanoengineered materials with an aperiodic distribution of nanostructures plays a key role in efficiency-enhanced broadband photonic and plasmonic technologies for spectrally tailorable integrated biosensing, nanostructured thin film solarcells, white light emitting diodes, novel plasmonic ensembles etc. Through a generic deterministic nanotechnological route here we show subwavelength-scale silicon (Si) nanostructures on nanoimprinted glass substrate in large area (4 cm2) with advanced functional features of aperiodic composite nanophotonic lattices. These nanophotonic aperiodic lattices have easily tailorable supercell tiles with well-defined and discrete lattice basis elements and they show rich Fourier spectra. The presented nanophotonic lattices are designed functionally akin to two-dimensional aperiodic composite lattices with unconventional flexibility- comprising periodic photonic crystals and/or in-plane photonic quasicrystals as pattern design subsystems. The fabricated composite lattice-structured Si nanostructures are comparatively analyzed with a range of nanophotonic structures with conventional lattice geometries of periodic, disordered random as well as in-plane quasicrystalline photonic lattices with comparable lattice parameters. As a proof of concept of compatibility with advanced bottom-up liquid phase crystallized (LPC) Si thin film fabrication, the experimental structural analysis is further extended to double-side-textured deterministic aperiodic lattice-structured 10 μm thick large area LPC Si film on nanoimprinted substrates.

(Keynote) FD-SOI: The History from Early Transistors to Today

SOI technology was initiated in the mid 60’s by the quest for radiation-hard devices. Silicon on Sapphire (SOS) was the founder of the SOI family which later attracted many other members: epitaxial overgrowth (ELO), lamp or laser-induced melting and recrystallization (ZMR), wafer bonding and etch-back (BESOI), oxygen implantation (SIMOX), porous Si (FIPOS), etc. The coexistence of numerous options meant that none was really convincing as an industrial solution. The discovery of the Smart-Cut technology in early 90’s brought the necessary industrial momentum in terms of material quality, device performance and product adaptability to a variety of IC applications. The further development of Smart Cut Technology for ultra thin Si SOI in the mid 2000’s opened the door to a manufacturing-compatible planar fully-depleted CMOS IC platform, known today as FD-SOI. The basic mechanisms in fully depleted FD-SOI MOSFETs (interface coupling, back-biasing for threshold voltage adjustment, volume inversion, residual floating-body effects, etc.) have been understood early, when the thickness of Si film and buried dielectric was still in the micrometer range. Since then, these layers become two orders of magnitude thinner, revealing additional phenomena, for example reduced short-channel effects and size quantization. The concept of full depletion spread from FD-SOI to FinFETs and nanowire FETs simply because it is the unique solution for continuing the CMOS down-scaling. This paper reviews the milestones in FD-SOI history with the key technical steps, the strategic industrial decisions, the path to becoming a mass production qualified 22/28nm platform, the formation of the corresponding ecosystem, the early adopters and the markets driving its future growth. We will give a brief story of FD-SOI with insider experience and discuss its future prospects as the ultra low-power mixed signal & CMOS platform of the Internet of Things (IoT) era.SOI technology was initiated in the mid 60’s by the quest for radiation-hard devices. Silicon on Sapphire (SOS) was the founder of the SOI family which later attracted many other members: epitaxial overgrowth (ELO), lamp or laser-induced melting and recrystallization (ZMR), wafer bonding and etch-back (BESOI), oxygen implantation (SIMOX), porous Si (FIPOS), etc. The coexistence of numerous options meant that none was really convincing as an industrial solution. The discovery of the Smart-Cut technology in early 90’s brought the necessary industrial momentum in terms of material quality, device performance and product adaptability to a variety of IC applications. The further development of Smart Cut Technology for ultra thin Si SOI in the mid 2000’s opened the door to a manufacturing-compatible planar fully-depleted CMOS IC platform, known today as FD-SOI. The basic mechanisms in fully depleted FD-SOI MOSFETs (interface coupling, back-biasing for threshold voltage adjustment, volume inversion, residual floating-body effects, etc.) have been understood early, when the thickness of Si film and buried dielectric was still in the micrometer range. Since then, these layers become two orders of magnitude thinner, revealing additional phenomena, for example reduced short-channel effects and size quantization. The concept of full depletion spread from FD-SOI to FinFETs and nanowire FETs simply because it is the unique solution for continuing the CMOS down-scaling. This paper reviews the milestones in FD-SOI history with the key technical steps, the strategic industrial decisions, the path to becoming a mass production qualified 22/28nm platform, the formation of the corresponding ecosystem, the early adopters and the markets driving its future growth. We will give a brief story of FD-SOI with insider experience and discuss its future prospects as the ultra low-power mixed signal & CMOS platform of the Internet of Things (IoT) era.

Bonding of SiO2 and SiO2 at Room Temperature Using Si Ultrathin Film

In three-dimensional integration technology, the bonding of metal electrode and insulator hybrid interface is very important technique. The hybrid interface serves as both an electrical connection and mechanical bond. However, the bonding of these hybrid interfaces is a challenging issue. Since the conventional bonding process requires high-temperature annealing, there exist various problems such as thermal damage, low throughput, and low alignment accuracy. As the surface activated bonding (SAB) is a bonding method carried out at room or low temperatures [1], the bonding method is expected to solve these problems. By the SAB method, direct bonding metal materials such as Cu or Al is easy. However, it is very difficult to directly bond insulator materials such as SiO2 or SiN [2], because these surfaces are rendered inactive immediately after being activated. We have reported on the bonding technique at room temperature using only Si ultrathin films for insulator materials, and we have shown that high bonding strength is achieved [3]. The surface of electrode is also covered with Si film by this bonding method. Thus, it is very important to reveal the influence of this Si film thickness on the SiO2/SiO2 bonding. In this report, we have investigated the relationship between the SiO2/SiO2bonding strength and the thickness of Si ultrathin film. Figure 1 shows a schematic illustration of the bonding apparatus (Mitsubishi Heavy Industries, Ltd., MWB-08AX) used in this experiment. Surface activation is carried out by an Ar fast atom beam (FAB). In the normal SAB process, the upper and lower wafers are irradiated with the Ar-FAB at the same time. The bonding procedure which we propose for hybrid bonding is as follows. The one of bonding wafers is held by the electric static chuck (ESC), and Si blanket wafer is placed on the lower side as the sputtering target. First, only the lower wafer is irradiated with FAB1 (first irradiation) after activating electrode surface of the upper wafer. The blanket Si wafer is then exchanged with the other bonding wafer. Only the upper wafer is irradiated with FAB2 (second irradiation) after activating electrode surface of the lower wafer, and the Si film surface on the upper wafer is also etched by FAB2. A Si thin film is then deposited on the lower wafer surface. The upper wafer and the lower wafer are optically aligned and then bonded with high load.Figure 2 shows the relationship between the surface energy and the Si ultrathin film thickness for the bonding of Si blanket wafers (8 in) with a thermal oxide. Applied voltage and current of Ar beam source operated in these experiments were about 1.8 kV and 100 mA, respectively. The background vacuum pressure is about 2×10-6Pa. The surface energy of wafers was about 1 J/m2 for thicker than about 3 nm. A cross-sectional TEM image of SiO2/SiO2bonding is shown in Fig. 3. The bonded wafers were treated with a FAB1 irradiation time of 5 min and a FAB2 irradiation time of 1 min. No micro voids were observed, and Si intermediate layer, of which the thickness is about 3nm, was seen at the bonding interface.In conclusion, we showed that high bonding strength was achieved in SiO2/SiO2 bonding with the Si film thickness of about 3 nm by this bonding method. Reference:[1] H. Takagi, K. Kikuchi, R. Maeda, T. R. Chung, and T. Suga, Appl. Phys. Lett. 68, 2222 (1996).[2] H. Takagi, R. Maeda, T. R. Chung, and T. Suga, Sensors and Actuators, A 70, 164 (1998).[3] J. Utsumi, K. Ide, and Y. Ichiyanagi, Jpn. J. Appl. Phys., 55, 026503 (2016). Figure 1

Dual-material double-gate tunnel FET: gate threshold voltage modeling and extraction

A new analytical model for the gate threshold voltage ($$V_\mathrm{TG}$$VTG) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson's equation in the lightly doped Si film and employing the physical definition of $$V_\mathrm{TG}$$VTG. A numerical simulation study of the transfer characteristics and $$V_\mathrm{TG}$$VTG of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of $$V_\mathrm{TG}$$VTG is performed based on the transconductance change method as already used for conventional metal---oxide---semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on $$V_\mathrm{TG}$$VTG are reported. The dependence of $$V_\mathrm{TG}$$VTG on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.

Time-resolved, nonequilibrium carrier dynamics in Si-on-glass thin films for photovoltaic cells

A femtosecond pump–probe spectroscopy method was used to characterize the growth process and transport properties of amorphous silicon-on-glass, thin films, intended as absorbers for photovoltaic cells. We collected normalized transmissivity change (ΔT/T) waveforms and interpreted them using a comprehensive three-rate equation electron trapping and recombination model. Optically excited ∼300–500 nm thick Si films exhibited a bi-exponential carrier relaxation with the characteristic times varying from picoseconds to nanoseconds depending on the film growth process. From our comprehensive trapping model, we could determine that for doped and intrinsic films with very low hydrogen dilution the dominant relaxation mode was carrier trapping; while for intrinsic films with large hydrogen content and some texture, it was the standard electron–phonon cooling. In both cases, the initial nonequilibrium relaxation was followed by Shockley–Read–Hall recombination. An excellent fit between the model and the ΔT/T experimental transients was obtained and a correlation between the Si film growth process, its hydrogen content, and the associated trap concentration was demonstrated.

Capping of rare earth silicide nanowires on Si(001)

The capping of Tb and Dy silicide nanowires grown on Si(001) was studied using scanning tunneling microscopy and cross-sectional high-resolution transmission electron microscopy. Several nanometers thick amorphous Si films deposited at room temperature allow an even capping, while the nanowires maintain their original structural properties. Subsequent recrystallization by thermal annealing leads to more compact nanowire structures and to troughs in the Si layer above the nanowires, which may even reach down to the nanowires in the case of thin Si films, as well as to V-shaped stacking faults forming along {111} lattice planes. This behavior is related to strain due to the lattice mismatch between the Si overlayer and the nanowires.

Supercoupling effect in short-channel ultrathin fully depleted silicon-on-insulator transistors

Supercoupling effect prevents the simultaneous formation of inversion and accumulation channels at the two interfaces of ultrathin silicon-on-insulator metal-oxide-semiconductor field-effect transistor. Our work highlights that short-channel effects enhance supercoupling and turn it into a two-dimensional mechanism. The lateral influence of source and drain terminals is evidenced with experimental data and examined by 2D numerical simulations which reveal the roles of gate length and drain bias. The critical Si-film thickness, below which supercoupling arises, is significantly increased in short-channel transistors. The impact of back-gate and drain bias, BOX thickness, and quantum effects is documented and practical applications are discussed.

SiC@Si core–shell nanowires on carbon paper as a hybrid anode for lithium-ion batteries

Silicon has been considered as one of the most promising anode materials for the next generation lithium-ion battery due to its high theoretical capacity, but large volume changes during the electrochemical cycling limit its commercial application. In this study, we report the synthesis of silicon carbide @ silicon core–shell nanowires on carbon paper and their application in lithium-ion batteries. The hybrid nano-structures are fabricated via a two-step chemical vapor deposition method and directly used as the working electrode without any additional binder, exhibiting high specific capacity, high coulombic efficiency and good cycling stability. After 50 cycles, the discharge capacities still remain 2837 and 1809 mAh g−1 at the rates of 0.1C and 0.5C, respectively. Furthermore, we also study the influence of the growth time of SiC NWs and the thickness of Si film on the lithium-ion batteries' performance, and propose the possible method to further improve the battery performance.

Unusual gate coupling effect in extremely thin and short FDSOI MOSFETs

We investigated the characteristics of state-of-the-art FDSOI MOSFETs in a wide range of temperature by focusing on the effects of the back-gate bias, Si film thickness and channel length. High device performance and remarkably reduced short-channel effect with decreasing Si film thickness are achieved in ultra-thin film SOI devices. Systematic measurements reveal an unusual coupling effect resulting from the competition between front-gate, back-gate and temperature-dependent short-channel effect. Counter-intuitively, the impact of the back-gate bias can be smaller in 5nm than in 10nm thick MOSFETs, in particular in very short devices operated at 300K.

Impact of processing and back-gate biasing conditions on the low-frequency noise of ultra-thin buried oxide silicon-on-insulator nMOSFETs

The analysis of the low-frequency noise of fully-depleted Silicon-On-Insulator (SOI) ultra-thin body and Ultra-Thin Buried Oxide (UTBOX) MOSFETs with different gate stacks, Si film thicknesses and extension architecture is performed. It was revealed that the extension architecture is the main factor affecting the drain current and low frequency noise behavior of the devices studied. It is revealed that the 1/f noise of extensionless MOSFETs appears to be higher than for standard ones, especially when the back interface is biased towards accumulation. The latter is accompanied by the lower drain current of extensionless devices in comparison to standard ones. Moreover, the Lorentzians accompanying the Linear Kink Effect that were revealed for standard MOSFETs, were not observed for extensionless devices. The latter is ascribed to the different architecture of the source/drain regions, which affect source/drain-body junctions characteristics and free charge carrier concentration.

Residual stress modeling of density modulated silicon thin films using finite element analysis

Density modulated thin films offer a compliant property that can reduce residual stress, which typically originate during the growth of thin films. Lower residual stress improves adhesion properties of the film with reduced buckling or delamination, and therefore leads to more durable coatings. In this study, finite element analysis (FEA) was employed to simulate the residual stresses developed in density modulated silicon (Si) thin films, which incorporate alternating low and high density layers. The main focus of this investigation is not developing new FEA algorithms but to verify the impact of density modulated layers quantitatively using computational methods. Hence, verification of a predicted stress reduction enhances the current understanding of the mechanics of density modulated layered thin films. FEA simulation results reveal that low density layers act compliant and result in significant reduction in film stress especially at the interface with the substrate. For example, maximum stress at the film/substrate interface, which is in the substrate, was reduced from 2897 MPa down to 2432 MPa by simply adding a 100 nm thick density-modulated low-density Si layer in between a 300 μm thick Si wafer substrate and 1 μm thick conventional high density Si film, which makes the reduction percentage of the maximum stress about 16%.

Fabrication of a high-performance poly-Si thin-film transistor using a poly-Si film prepared by silicide-enhanced rapid thermal annealing process

A 50-nm thick polycrystalline Si film was fabricated by the crystallization of anamorphous Si film using silicide-enhanced rapid thermal annealing (SERTA). The amorphous Si film was deposited on a 5-nm thick polycrystalline Si seed layer containing nickel silicide precipitates in grain boundary areas. With the help of the silicide precipitates, the RTA temperature decreased from 730 to 680°C and the grain size of the crystallized polycrystalline Si film increased to 1.4 — 2.2 μm. Few defects were found within the grains and the Ni concentration in the polycrystalline film decreased to 1 × 1018 cm−3 due to the very-thin seed layer that contained nickel silicide precipitates. As a result, the field-effect hole mobility in the p-channel poly-Si thin film transistors (TFTs), fabricated employing the polycrystalline Si film, was as high as 169 cm2/V∙s at a drain voltage of V D = −0.1 V; the subthreshold swing was as small as 0.24 V/decade. The minimum leakage current at V D = 5V was 1.5 × 10−10 A with very good diode characteristics.

High areal capacity, micrometer-scale amorphous Si film anode based on nanostructured Cu foil for Li-ion batteries

We report a feasible design to fabricate micrometer-scale Si films deposited on nanostructured Cu foil as high areal capacity anodes for Li-ion batteries with excellent cycling performance. Nanostructured copper oxides are prepared by anodic oxidation of Cu foil in alkaline solution. The resultant copper oxide nanofibers function as matrix for thick Si films (1–2 μm) loading. Metallic Cu nanofibers are obtained by in-situ electrochemical reduction at low potentials, which work as electrical highways for fast electron transport and a reliable mechanical matrix to accommodate volume changes during lithium–silicon alloy/dealloy processes. The engineered thick Si film anode exhibit both high areal capacity (0.48 mAh cm−2 for 1 μm Si film and 0.6 mAh cm−2 for 2 μm Si film after 200 cycles at 0.225 mA cm−2) and excellent rate capability (0.52 mAh cm−2 at 1.05 mA cm−2 for 2 μm Si film). The 2 μm silicon film electrode is able to recover to the initial value of 1 mAh cm−2 when the current rate is set back to 0.15 mA cm−2 even after cycling at high current rates. The reported concept can be a general method for high-loading-film electrodes, which is industrial scalable and compatible with current battery manufacturing processes.

Metal-induced crystallization of highly corrugated silicon thick films as potential anodes for Li-ion batteries.

Silicon has turned into one of the most promising anodes for high energy rechargeable Li-ion batteries. However, a huge volume expansion during alloying with Li always induces serious pulverization/delamination for microsized electrodes as well as undesired accumulation of solid electrolyte interphase (SEI). Many efforts have focused on various nanoengineering and binding strategies to construct integrated, robust ionic/electronic wiring networks but with a trade-off between active/inactive material ratio and performance retention. Here, we first apply a metal-induced crystallization (AIC) principle for immiscible metal/semiconductor systems (Si/Al bilayers in this work) to prepare microthick Si films consisting of a high density of isolated nanocolumns. This method furthermore brings about low temperature crystallization of initial amorphous Si and conformal coating of ion-conductive oxide to enhance the Li transport kinetics of bulk and interface. Both highly satisfactory capacity retention (1650 mAh/g after 500 cycles) and rate performance (∼1000 mAh/g at 8C) are achieved for such thick Si film anodes. This methodology can be used to prepare thick film samples with well-defined nanostructures but free of extra binder and conductive additives. It enables much higher area specific capacity than for inactive-component contained slurry samples and thin film samples. This postdeposition pore-creating can be extended to more alloying or conversion electrodes of thick films for high capacity Li/Na ion batteries.

Flash Ignition of Freestanding Porous Silicon Films: Effects of Film Thickness and Porosity

We report the first successful xenon flash ignition of freestanding porous Si films in air. The minimum flash ignition energy (Emin) first decreases and then increases with increasing the porous Si film thickness due to the competition between light absorption and heat loss. The Emin is lower for higher porosity film because high porosity reduces both the heat capacity and the thermal conductivity, facilitating the temperature rise. These results are important for initiating controlled porous Si combustion and preventing their unwanted combustion for safety reasons.