Thick Porous Si Layer Research Articles

Metal assisted anodic etching of silicon.

Metal assisted anodic etching (MAAE) of Si in HF, without H2O2, is demonstrated. Si wafers were coated with Au films, and the Au films were patterned with an array of holes. A Pt mesh was used as the cathode while the anodic contact was made through either the patterned Au film or the back side of the Si wafer. Experiments were carried out on P-type, N-type, P(+)-type and N(+)-type Si wafers and a wide range of nanostructure morphologies were observed, including solid Si nanowires, porous Si nanowires, a porous Si layer without Si nanowires, and porous Si nanowires on a thick porous Si layer. Formation of wires was the result of selective etching at the Au-Si interface. It was found that when the anodic contact was made through P-type or P(+)-type Si, regular anodic etching due to electronic hole injection leads to formation of porous silicon simultaneously with metal assisted anodic etching. When the anodic contact was made through N-type or N(+)-type Si, generation of electronic holes through processes such as impact ionization and tunnelling-assisted surface generation were required for etching. In addition, it was found that metal assisted anodic etching of Si with the anodic contact made through the patterned Au film essentially reproduces the phenomenology of metal assisted chemical etching (MACE), in which holes are generated through metal assisted reduction of H2O2 rather than current flow. These results clarify the linked roles of electrical and chemical processes that occur during electrochemical etching of Si.

A Thermoelectric Generator Using Porous Si Thermal Isolation

In this paper we report on a thermoelectric generator (TEG) using thermal isolation provided by a thick porous Si layer locally formed on the Si wafer and thermocouples composed of p-doped polycrystalline Si/Al. The “hot” contacts of the thermocouples lie on the porous Si layer, while the “cold” contacts lie on bulk crystalline Si. A housing was also designed and fabricated in order to transfer any external temperature change on the “hot” contacts of the thermocouples, the “cold” contacts being isolated from the “hot” contacts by a thick resist layer. The fabrication of the sensing element (Si die) is fully compatible with batch Si processing. The output power of the thermoelectric generator depends on the porous Si isolation layer thickness, porosity, structure and morphology. For a mesoporous Si layer of 60% porosity and a macroscopic temperature differential of 10 K, an output power of 0.39 μW/cm2 was measured for a 50 μm thick porous Si layer.

Low thermal conductivity porous Si at cryogenic temperatures for cooling applications

Porous Si thermal conductivity was determined in a wide temperature range from 20 to 350 K using the steady-state direct current method and a subsequent finite element method. The method was applied to a 40 µm thick porous Si layer of ∼60% porosity, formed on p-type Si of resistivity 1–10 Ω cm. It was found that in the temperature range 20–80 K the thermal conductivity of the studied porous Si layer was more than four orders of magnitude lower than that of bulk crystalline Si, due to phonon confinement in the nanostructured skeleton composing porous Si. The temperature distribution as a function of distance from a heater on the porous Si layer and as a function of depth from the porous Si/metal interface was also calculated for different values of the applied electric power and for two different temperatures, 20 and 290 K, using a combination of experimental results and simulations. The effectiveness of local thermal isolation from the Si substrate by a thick highly porous Si layer in a wide temperature range was demonstrated, showing that this material is challenging for use in Si micro-cooling devices.

Integrated inductors on porous silicon

AbstractWe examine porous Si as a thick RF‐isolation layer for on‐chip inductors and separate the loss sources that downgrade the Q factors into their material components, namely Si substrate loss and metal types common to standard CMOS technologies. First we validate theoretical designs with measurements in standard 0.18 μm CMOS technology. Then we examine the effect of a porous Si substrate on a fixed metal layout of a 2‐metal optimized inductor design compatible either with 0.18 μm CMOS technology using Aluminum or with 0.13 μm CMOS technology using Copper metallization. For typical on‐chip inductor layouts of (200–300 μm)2, we show that a 50 μm thick porous Si layer produces negligible current distributions inside the underlying lossy Si substrate, compared to the ones without it, which maintain high values throughout a large lateral extent of the die. In Al technology, a fixed inductor layout produces Q ‐factor enhancements of the order of 50%, compared to the case where no porous Si layer is used. In a 0.13 μm‐compatible CMOS technology using Cu on porous Si, the resulting Q ‐factors increase by a factor of 2 and reach values of 30 or more in the 3 GHz frequency range. For porous‐Si‐isolated inductors we compare the effect of metal losses and show that the resulting Q ‐factors scale with the metal conductivity. (© 2007 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Integrated inductors on porous silicon

AbstractThe cover picture illustrates the effective use of a thick porous silicon layer as an integrated micro‐plate for RF isolation on a silicon substrate, proposed by Harry Contopanagos and Androula Nassiopoulou in their Original Paper [1] in the current issue. What is plotted is the magnitude of the current distribution (colour coded from blue (low) to high (red) values) on the metallization and on a screen 50 µm underneath the bottom oxide layer of a 2‐metal integrated CMOS‐compatible inductor on bulk silicon (lower right) and on a 50 µm thick porous silicon layer (upper left) for a frequency of 2.5 GHz.Inductors were designed in a standard 0.13 µm CMOS technology. Efficient RF isolation is produced by the porous Si layer, as evidenced by the virtual elimination of surface currents relative to the case of standard CMOS, indicating virtually complete substrate shielding by a 50 µm thick porous Si layer for the relevant size scale. The quality factor of the inductor with the use of the porous Si layer is increased by 100%, reaching a maximum value of 33 for the design shown.The first author of the article is a visiting senior researcher at the Institute of Microelectronics (IMEL), National Center for Scientific Research “Demokritos” (Athens, Greece). His research focuses on electromagnetics and microwave engineering, artificial materials and photonic crystals, wireless front ends, antennas and high‐frequency analog integrated circuits.

Metastability of Luminescent Porous Silicon

ABSTRACTPhotoluminescence from l–3μm thick porous Si layers prepared by anodization of p-type c-Si wafers and subsequent chemical etching exhibits an anomalous temperature dependence and light-induced degradation. The luminescence intensity is almost quenched at temperatures below 30K and recovered by laser irradiation at 48K. This quenching phenomenon is not observed for PS thicker than 10μm. The luminescence fatigue is partially recovered by annealing at 150°C for 5min during which no further oxidation takes place. These observations are interpreted in terms of the structural metastability of hydrogen-terminated porous Si.