Thermal Resistance Of Heat Sink Research Articles

From Chip to Cooling Tower Data Center Modeling: Influence of Chip Temperature Control Philosophy

The chiller cooled data center environment consists of many interlinked elements that are usually treated as individual components. This chain of components and their influences on each other must be considered in determining the benefits of any data center design and operational strategies seeking to improve efficiency, such as temperature controlled fan algorithms. Using the models previously developed by the authors, this paper extends the analysis to include the electronics within the rack through considering the processor heat sink temperature. This has allowed determination of the influence of various cooling strategies on the data center coefficient of performance. The strategy of increasing inlet aisle temperature is examined in some detail and found not to be a robust methodology for improving the overall energy performance of the data center, while tight temperature controls at the chip level consistently provide better performance, yielding more computing per watt of cooling power. These findings are of strong practical relevance for the design of fan control algorithms at the rack level and general operational strategies in data centers. Finally, the impact of heat sink thermal resistance is considered, and the potential data center efficiency gains from improved heat sink designs are discussed.

Stationary and Adaptive Color-Shift Reduction Methods Based on the Bilevel Driving Technique for Phosphor-Converted White LEDs

The bilevel driving technique has realized a 2-D control of the luminosity and emitted color of white LEDs with duty cycle and forward current levels. Unfortunately, various combinations of these dimming control parameters can lead to significant changes in junction temperature, which further modify the luminosity and emitted color of LEDs. In this paper, the theoretical aspects of these complex interactions and the impact of bilevel drive on the color-shift properties of white LEDs are discussed in detail by using a mathematical color-shift model. Two color-shift reduction methods are proposed based on the insights obtained from this model. This study shows that a heat sink's thermal resistance that minimizes the overall color shift over dimming can be uniquely determined from the knowledge of some measurable LED parameters, and gives rise to a global minimum color shift. If such a thermal resistance cannot be realized due to practical limitations, the second method that utilizes an adaptive change of forward current levels over dimming can be adopted. Based on their nature, these methods are classified as stationary and adaptive methods, respectively. Their validity is supported by experimental measurements on a commercial white LED.

Performance analysis of multi-stage thermoelectric coolers

Multi-stage thermoelectric coolers offer larger temperature differences between heat source and heat sink than single-stage thermoelectric coolers. In this paper, a pyramid-type multi-stage cooler is analyzed, focusing on the importance of maximum attainable target heat flux and overall coefficient of performance, COP. Having considered the COP and the thermal resistance of a heat sink as key parameters in the design of a multi-stage thermoelectric cooler, analytical formulas for COP and heat sink thermal resistance versus working electrical current are derived. For a fixed cooling target heat flux, the ratio of the heat sink thermal resistance to the respective single-stage value and the attainable COP in a cascaded cooler are determined as a function of the number of stages. Numerical simulations clearly indicate that the thermal resistance of the hot side heat sink is the controlling factor in determining the overall performance of a multi-stage thermoelectric cooler.

Experimental Investigation of Porous Micro Heat Sink for Electronics Cooling Application

A novel porous micro heat sink system was presented for dissipating high heat fluxes of electronic device. The flow and heat transfer of porous micro heat sink was investigated by experiment at the condition of high heat fluxes, and the results showed that the heat load of up to 280W was removed by the heat sink, and the heater junction temperature was 63.8°C at the coolant flow rate of 5.1cm3/s. The whole heat transfer coefficient of heat sink increased with the increases of coolant flow rate and heat load, and the maximal heat transfer coefficient was 33kW(m2.°C)-1 in the experiment. The minimum value of 0.19°C/W for whole thermal resistance of heat sink was achieved at flow rate of 5.1cm3/s, and increasing of coolant flow rate and heat fluxes could decrease the thermal resistance.

Energy-Optimal Dynamic Thermal Management: Computation and Cooling Power Co-Optimization

Conventional dynamic thermal management (DTM) assumes that the thermal resistance of a heat-sink is a given constant determined at design time. However, the thermal resistance of a common forced-convection heat sink is inversely proportional to the flow rate of the air or coolant at the expense of the cooling power consumption. The die temperature of the silicon devices strongly affects its leakage power consumption and reliability, and it can be changed by adjusting the thermal resistance of the cooling devices. Different from conventional DTM which aims to avoid the thermal emergency, our proposed DTM regards the thermal resistance of a forced-convection heat sink as a control variable, and minimize the total power consumption both for computation and cooling. We control the cooling power consumption together with the microprocessor clock frequency and supply voltage, and track the energy-optimal die temperature. Consequently, we reduce a significant amount of the temperature-dependent leakage power consumption of the microprocessor while spending a bit higher cooling power than conventional DTM, and eventually consume less total power. Experimental results show the proposed DTM saves up to 8.2% of the total energy compared with a baseline DTM approach. Our proposed DTM also enhances the Failures in Time (FIT) up to 80% in terms of the electromigration lifetime reliability.

Effects of Nonuniform Base Heating on Single Stack and Multi-Stack Microchannel Heat Sinks Used for Electronics Cooling

Numerical investigations with regard to the thermal characteristics of water cooled single stack and multistack microchannel heat sinks subjected to nonuniform base heating are conducted. Nonuniformities in base heating are accomplished by applying gradually increasing and gradually decreasing base heat fluxes with respect to coolant flow direction in the heat sink. The effects of heat concentration upstream, downstream, and in the center half of the microchannel heat sinks (similar to a hotspot) are also studied. Both parallel flow and counter coolant flow conditions in the heat sink are considered and the results are compared. The results are presented in the form of base temperature distribution and heat sink thermal resistance. The finite element method is used for the analysis.

Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits

Three-dimensional (3D) interconnection technology offers several electrical advantages, including reduced signal delay, reduced interconnect power, and design flexibility. 3D integration relies on through-silicon vias (TSVs) and the bonding of multiple active layers to stack several die or wafers containing integrated circuits (ICs) and provide direct electrical interconnection between the stacked strata. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in stacked 3D ICs are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multidie stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of a single-valued junction-to-air thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package and heat sink thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the multidie stack. The improvement required in package and heat sink thermal resistances for a 3D logic-on-memory implementation to be thermally feasible is quantified. An increase in maximum temperature in a 3D IC compared to an equivalent system-in-package (SiP) is predicted. This increase is found to be mainly due to the reduced chip footprint. The increased memory die temperature in case of memory-on-logic integration compared to a SiP implementation is identified to be a significant thermal management challenge in the future. The results presented in this paper may be useful in the development of thermal design guidelines for 3D ICs, which are expected to help maximize the electrical benefits of 3D technology without exacerbating thermal management issues when implemented in early-stage electrical design and layout tools.

Design and Optimization of Single-Phase Liquid Cooled Microchannel Heat Sink

Semiconductor devices for demanding automotive applications generate a large amount of heat (>100 Wcm2). These high power devices can be cooled off very effectively by liquid coolant flowing through the microchannel heat sink. Microchannel heat sinks are very attractive because of their compactness, light weight, and large surface-to-volume ratio. Higher surface-to-volume ratio results in enhanced cooling performance. In this paper, a systematic robust analytical method is presented for design and optimization of single-phase liquid cooled microchannel heat sink. Effects of various design parameters such as eccentricity and footprint of heat source or device, thickness of the heat sink base, channel aspect ratio, number of microchannels or fins, coolant flow rate, and thermal conductivity of heat sink material on heat sink thermal resistances and pressure drop are delineated. Finally, analytical results are compared with experimental data and good agreement is obtained. The analytical method helps to reduce the design cycle time and time-to-market significantly.

Low-Temperature Two-Phase Microchannel Cooling for High-Heat-Flux Thermal Management of Defense Electronics

For a given heat sink thermal resistance and ambient temperature, the temperature of an electronic device rises fairly linearly with increasing device heat flux. This relationship is especially problematic for defense electronics, where heat dissipation is projected to exceed 1000 W/cm2 in the near future. Direct and indirect low-temperature refrigeration cooling facilitate appreciable reduction in the temperature of both coolant and device. This paper explores the benefits of cooling the device using direct and indirect refrigeration cooling systems. In the direct cooling system, a microchannel heat sink serves as an evaporator in a conventional vapor compression cycle using R134a as working fluid. In the indirect cooling system, HFE 7100 is used to cool the heat sink in a primary pumped liquid loop that rejects heat to a secondary refrigeration loop. Two drastically different flow behaviors are observed in these systems. Because of compressor performance constraints, mostly high void fraction two-phase patterns are encountered in the R134a system, dominated by saturated boiling. On the other hand, the indirect refrigeration cooling system facilitates highly subcooled boiling inside the heat sink. Both systems are shown to provide important cooling benefits, but the indirect cooling system is far more effective at dissipating high heat fluxes. Tests with this system yielded cooling heat fluxes as high as 840 W/cm2 without incurring critical heat flux (CHF). Results from both systems are combined to construct an overall map of performance trends relative to mass velocity, subcooling, pressure, and surface tension. Extreme conditions of near-saturated flow, low mass velocity, and low pressure produce ldquomicrordquo behavior, where macrochannel flow pattern maps simply fail to apply, instabilities are prominent, and CHF is quite low. One the other hand, systems with high mass velocity, high subcooling, and high pressure are far more stable and yield very high CHF values; two-phase flow in these systems follows the fluid flow and heat transfer behavior as well as the flow pattern maps of macrochannels.

Towards a Thermal Moore's Law

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Thermal design power trends and power densities for present and future single-core microprocessors are investigated. These trends are derived based on Moore's law and scaling theory. Both active and stand-by power are discussed and accounted for in the calculations. A brief discussion of various leakage power components and their impact on the power density trends is provided. Two different lower limits of heat dissipation for irreversible logic computers that have previously appeared in the literature are discussed. These are based on the irreversibility of logic to represent one bit of information, and on the distribution of electrons to represent a bit. These limits are found to be two or more orders of magnitude lower than present-day microprocessor thermal design power trends. Further, these thermal demand trends are compared to the projected trends for the desktop product sector from the International Technology Roadmap for Semiconductors (ITRS). To evaluate the thermal impact of projected power densities, heat sink thermal resistances are calculated for a given technology target. Based on the heat sink thermal resistance trends, the evolution of a consistent air-cooling limit is predicted. One viable alternative to air-cooling, i.e., the use of high-efficiency solid-state thermoelectric coolers (TECs), is explored in detail. The impact of different parasitics on the thermoelectric figure of merit (ZT) is quantified. </para>

Fluid flow and heat transfer in liquid cooled foam heat sinks for electronic packages

In this paper, the fluid flow and heat transfer of liquid cooled foam heat sinks (FHSs) were experimentally investigated. Eight Open-celled copper foam materials with two pore densities of 60 and 100 PPI (pores per inch) and four porosities varying from 0.6 to 0.9 were bonded onto copper base plates to form the FHSs, which were then assembled on flip chip BGA packages (FBGAs) with a common thermal grease as the thermal interface material. A liquid cooling test loop was established to obtain the pressure drops and overall thermal resistances. For the four 60 PPI FHSs, the one with the lowest porosity of 0.6 is found to possess the lowest thermal resistance level with the largest pressure drop. Generally the FHSs with 100 PPI had slightly lower thermal resistances at the same flowrates but much larger pressure drops than those with 60 PPI. In the overall performance assessment, the thermal resistances of the FHSs are plotted against the pressure drop and the pump power, together with a microchannel heat sink of similar unit cell scale and structural dimensions. The thermal resistances of the FHS with a porosity of 0.8 and pore density of 60 PPI were identified to be the lowest among all the FHSs, which outperformed the microchannel heat sink at large pressure drop and pump power. The reduced heat sink thermal resistance and Nusselt numbers for the present FHSs and microchannel heat sink are also presented and compared with the FHS reported in the literature.

Performances of thermoelectric cooler integrated with microchannel heat sinks

In this study, experimental and theoretical studies on thermoelectric cooler (TEC) performance for cooling a refrigerated object (water in a tank) were performed. Microchannel heat sinks fabricated with etched silicon wafers were employed on the TEC hot side to dissipate heat. The measurements show that the temperature of the refrigerated object decreased with time. A theoretical model based on a lumped system was established to predict the transient behavior of the variation in temperature for the refrigerated object with time. The theoretical predicted temperature variation was in good agreement with the measured data. The relationship among the heat sink thermal resistances, TEC electric current input and minimum refrigerated objected temperature was examined based on the theoretical model. The calculated minimum temperatures were showed for the several cases of heat sink thermal resistance on the TEC hot side and electric current input. The minimum temperature can be obtained by increasing the electrical current input and decreasing the heat sink thermal resistance.

Trade-off Design of Extruded Heat Sinks Using Mathematical Optimization

Heat sink designers have to balance a number of conflicting parameters to maximize the performance of heat sinks. This multi-parameter problem lends itself naturally to mathematical optimization techniques. The paper illustrates how mathematical optimization techniques combined with a semi-empirical thermal simulation program can be used to construct a trade-off curve (Pareto-optimal set) between the heat sink mass and thermal resistance for a given heat sink configuration. This trade-off curve can be used by the engineer to decide on the optimal heat sink design that is the best compromise between heat sink mass and thermal resistance for the specific application under consideration.

Thermoelectric cooler application in electronic cooling

This study addresses thermoelectric cooler (TEC) applications in the electronic cooling. The cold side temperature ( T c) and temperature difference between TEC cold and hot sides (Δ T= T h− T c, T h=temperature of hot side of TEC) were used as the parameters. The cooling capacity, junction temperature, coefficient of performance (COP) of TEC and the required heat sink thermal resistance at the TEC hot side were computed. The results indicated that the cooling capacity could be increased as T c increased and Δ T was reduced. The maximum cooling capacity and chip junction temperature obtained were 207 W and 88 °C, respectively. The required heat sink thermal resistance on TEC hot side was 0.054 °C/W. Larger cooling capacity and higher COP could be obtained when the TEC was operated in the enforced regimes (Δ T<0). However, TEC performance was restricted by the T c values and heat sink thermal resistance at the TEC hot side. A microchannel heat sink using water or air as the coolant was demonstrated to meet the low thermal heat sink resistance requirement for TEC operated at maximum cooling capacity conditions.

Heat transfer from square pin-fin heat sinks using air impingement cooling

Experimental and numerical results are presented for heat transfer from a C4 mounted organic land grid array (OLGA) thermal test chip cooled by air impingement. Five heat sink geometries were investigated for Reynolds numbers ranging from 9,000 to 26,000. The dimensionless nozzle-to-heat sink vertical spacing z/D was varied between 2 and 12. In this study, we investigate the interactions between heat sink geometry, flow conditions and nozzle setting and how they affect the convective heat transfer and overall cooling of the test chip as measured by total thermal resistance /spl theta//sub ja/. Optimizing fin arrays by minimizing the overall heat sink thermal resistance instead of focusing solely on maximizing the heat transfer from the fins is shown to be a better design criterion. We also provide results that show cooling performance gains can be obtained by inserting a deflector plate above the heat sink.

A design method of thermoelectric cooler

A system design method of thermoelectric cooler is developed in the present study. The design calculation utilizes the performance curve of the thermoelectric module that is determined experimentally. An automatic test apparatus was designed and built to illustrate the testing. The performance test results of the module are used to determine the physical properties and derive an empirical relation for the performance of thermoelectric module. These results are then used in the system analysis of a thermoelectric cooler using a thermal network model. The thermal resistance of heat sink is chosen as one of the key parameters in the design of a thermoelectric cooler. The system simulation shows that there exists a cheapest heat sink for the design of a thermoelectric cooler. It is also shown that the system simulation coincides with experimental data of a thermoelectric cooler using an air-cooled heat sink with thermal resistance 0.2515°C/W. An optimal design of thermoelectric cooler at the conditions of optimal COP is also studied. The optimal design can be made either on the basis of the maximum value of the optimal cooling capacity, or on the basis of the best heat sink technology available.

Design considerations and analytical approximations for high continuous-wave power, broad-waveguide diode lasers

Accurate analytical approximations are derived for the equivalent transverse spot size, d/Γ (&amp;lt;5% error), and the transverse beamwidth θ1/2 (&amp;lt;2% error), of broad-waveguide-type diode lasers, over a wide range in waveguide width: from the first-order-mode cutoff to the third-order-mode cutoff. The analytical formulas are found to be in good agreement with experimental values. For low-series-resistance and thermal-resistance devices, it is found that the junction-temperature rise ΔTj in continuous wave (CW) operation is a strong function of both the characteristic temperature T1 for the external differential quantum efficiency ηD as well as of the heatsink thermal resistance. If the device has relatively temperature-insensitive ηD (i.e., T1≳1000 K) the maximum CW power as well as the power density at catastrophic optical mirror damage, P̄COMD, are limited, for a given active-region material, only by the heatsink heat-removal ability. For large d/Γ, 0.97 μm emitting, 100 μm stripe InGaAs/InGaAs(P)/GaAs devices with T1=1800 K, record-high CW and quasi-CW (100 μs wide pulses) output powers are obtained. The ratio of quasi-CW to CW P̄COMD values is only 1.3, in contrast to devices of poor carrier confinement and subsequent low-T1 values (∼140 K), for which the ratio is 1.9, and whose maximum CW powers are ∼40% less than those obtainable from high-T1 devices.

Thermal Performance of Pin-Fin Fan-Sink Assemblies

Abstract Experiments are reported on the thermal performance of model fan-sink assemblies consisting of a small axial flow fan which impinges air on a square array of pin-fins. Cylindrical, square, and diamond shape cross section pin-fins are considered. The pin-fin heat transfer coefficient is found to be maximum immediately under the fan blades and minimum below the fan hub and near the corners of the array. The overall heat sink thermal resistance, R, decreases with an increase in either applied pressure rise or fan power and fin height. At fixed applied pressure rise, R is minimized when the fin pitch-to-diameter ratiois maximum. At fixed fan power, R is minimized when the pitch-to-diameter ratio is reduced toward unity. Finally, cylindrical pin-fins give the best overall fan-sink performance.

Effect of Pin Fin Density of the Thermal Performance of Unshrouded Pin Fin Heat Sinks

An experimental investigation was conducted to examine the effect of pin fin density on thermal resistance of unshrouded pin fin heat sinks. Six heat sinks with different number of round pin fins were constructed. Heat sink thermal resistance was calculated by maintaining its base temperature constant. For these experiments, air flow varied from natural to high velocity forced convection. The results showed that thermal resistance did not decrease with increase of number of pin fins. An optimum number of pin fins existed beyond which thermal resistance actually increased. The study also showed that thermal resistance was a function of air velocity and governing flow pattern. Comparison of the heat transfer coefficient (h) and pin fin surface area showed that h decreased dramatically as surface area increased. The results showed that pin fin heat sinks with small number of pins had the best performance at low and moderate forced convection cooling.

Thermal interaction of semiconductor devices on copper clad ceramic substrates

The temperature rise due to the spacing between two heat dissipating devices mounted on metallized or copper-clad ceramic substrates is presented. The thickness of the copper layer, the thermal conductivity of the substrate material, and the thermal resistance of the heat sink system are considered. Results for parameters typically found in power hybrid applications are presented in nondimensional form. The results indicate that increasing the thickness of the copper metallization requires that the devices be placed farther apart to prevent thermal interaction. An increase in the copper layer thickness can significantly decrease the device temperatures on alumina, but may increase temperatures on high thermal conductivity ceramic substrates such as beryllia (BeO). The results also demonstrate that the external heat sink thermal resistance can cause significant heat flow spreading and increased temperatures in the substrate. As the external resistance increases, the spacing required to prevent thermal interaction also increases.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>