Thermal Expansion Coefficient Of Substrate Research Articles

Substrate thermal expansion coefficient effect on cracks induced by the high-heat treatment of electroplated Ni-P films for power devices

Automotive power semiconductors are required not to fail at high-temperature mounting (∼400 °C), and a structural design that prevents defects as well as cracks is essential. In this study, we focused on the thermal expansion coefficient of medium-phosphorus Ni films (P content: 8–9 wt%), which are commonly used for soldering or wire-bonding, with the substrates on which they are electroplated to investigate the effects of high-temperature heating on cracks induced in the Ni films. The Ni-P films were deposited on Al, Cu, Ni, and Fe substrates via electroplating technique using a Watts bath containing phosphorous acid. By heating to approximately 360 °C, the Ni-P film shrank because of the phase transition to a phosphorus compound mainly composed of Ni3P. As a result of the Ni film indentation test after heating to 400 °C, cracks were induced in the Ni film on the Cu substrate but not on the Ni substrate. The thermal expansion coefficients of the Cu and Ni substrates at approximately 360 °C were 17.4 and 14.8 µm m−1 °C−1, respectively; suggesting that the residual stress at the interface between the Ni film and the substrate affects cracking.

Optimized Tunability of Barium Strontium Titanate Thin Films onto Different Plates with Proper Buffer Layers

Misfit strain, polarization, permittivity, and tunability of Ba x Sr1−x TiO3 (BST) thin films on various substrates with varied buffer layers are calculated by a modified thermodynamic model. The lattice parameters of the LaAlO3 (LAO), CaTiO3 (CT), BaZr0.25Ti0.75O3 (BZT), and MgO buffer layers grow consecutively as does the thermal expansion coefficient (TEC) of the Si, Ti, Ni, and stainless steel (SS) substrates. When the TEC of substrates is bigger (such as Ni, SS) than that of the films, introducing buffer layers with larger lattice parameters (such as BZT, MgO) can improve the permittivity and tunability. Conversely, inserting buffer layers with smaller lattice parameters (such as LAO, CT) can enhance the dielectric response when the TEC of substrates is smaller (such as Si, Ti) than that of the films. The relationship between the TEC of substrate and the lattice parameter of buffer layer is primarily linear for achieving high tunability. According to several references, introducing LaNiO3 buffer layers can significantly increase the tunability of BST solid solutions prepared on Si‐based substrates, which is in line with the estimated rule. This law offers a guide for choosing the best substrate and buffer layer when producing BST films with strong dielectric response.

Challenges toward applying UHTC-based composite coating on graphite substrate by spark plasma sintering

In this study, the UHTC-based composite layers where applied on the graphite substrates using SPS method to protect them against ablation. The protective layers had some defects and problems such as crack, fracture, separation, melting, and weak adhesion to the substrate. Several factors such as the thickness of composite layer, the number of protective layers, the SPS conditions (temperature, applied pressure, soaking time and mold), the chemical composition of the layers, the type of the substrate and the mismatch between the thermal expansion coefficients of the substrate and the applied layer(s) affected the quality and connection of the protective layer to the graphite substrate. The amount of additive materials influenced the melting phenomenon in the composite layer; for example, further MoSi2 in the layer led to more melting. The mismatch between the thermal expansion coefficients of the graphite substrate and the composite layer caused stresses during the cooling step, which resulted in cracks in the applied layer. Hence, proximity in the thermal expansion coefficients seems to be necessary for the formation of an acceptable adhesion between the layer and the substrate.

Development of epitaxial PbS layers obtaining method for photoelectric transducers

Photoelectric transducers are a semiconductor device that converts photonic energy into electrical energy. This paper describes obtained by the hotwall epitaxy method epitaxial PbS layers technology. Materials, methods, technological parameters of synthesis were selected and substantiated. A theoretical model of the p-n transition has been developed. The calculation of the main parameters has been done. The hotwall epitaxy method was chosen for the synthesis, because it allows to obtain layers with required properties in a single technological cycle with an economical consumption of material. BaF2 was chosen as the substrate, because in this case a smaller difference in the identity periods and the layer and the substrate thermal expansion coefficients is achieved.

Effect of substrate thermal expansion coefficients on the properties of (Bi,Na)TiO3–BaTiO3 thick films around the morphotropic phase boundary

Lead-free (1–x)(Bi0.5Na0.5)TiO3–xBaTiO3 (abbreviated as BNT–100xBT) thick films around the morphotropic phase boundary composition (0.03 ≤ x ≤ 0.09) were prepared on Pt-coated substrates with different thermal expansion coefficients, and the properties of the films were analyzed. While BNT–100xBT (x ≤ 0.05) exhibit a rhombohedral structure, BNT–100xBT (0.07 ≤ x) exhibit a tetragonal structure. The BNT–100xBT (0.03 ≤ x ≤ 0.09) thick films prepared on the MgO substrate preferentially formed c-domains. The Pr of the BNT–100xBT (0.03 ≤ x ≤ 0.09) thick films has the maximum value at the composition of x = 0.07 at room temperature. The depolarization temperature of the BNT–100xBT thick films prepared on MgO substrates with Pt bottom electrodes (0.05 ≤ x) was larger than that of the BNT–100xBT thick films prepared on 3 mol% Y2O3-stabilized ZrO2, Al2O3 substrates with Pt bottom electrodes, or bulk ceramics. An increase in the depolarization temperature became larger with an increase in composition of x because the thermal expansion difference between BNT–100xBT and MgO became large with an increase in the composition of x.

Influence of substrate and sintering temperature on the thickness and number of layers of 3YSZ multilayer sol-gel coatings

A study was made of the influence of the substrate (fused quartz, sapphire, soda-lime glass, and stainless steel AISI-310) and sintering temperature (300 °C, 500 °C, and 800 °C) on the thickness and number of layers of 3YSZ multilayer sol-gel coatings that can be deposited by dip-coating without the coating cracking. It was found that the thickness and the number of layers increase with the higher sintering temperature and the greater substrate's thermal expansion coefficient. These trends were explained as resulting from the residual in-plane stresses generated in the sol-gel coating when cooled from the sintering temperature down to room temperature due to its thermal expansion coefficient differing from that of the substrate. Thus, the smaller the residual in-plane tensile stress or the greater the residual in-plane compressive stress, the greater can be the thickness and number of layers of the sol-gel coating. The same is the case for higher sintering temperatures because the densification of the layers either predominates over the increased in-plane tensile stresses or combines synergistically with the greater in-plane compressive stresses.

P‐66: Low Coefficient of Thermal Expansion (CTE) Display Glass Minimizes Chip on Glass (COG) Light Leakage (LL) from Chip Warp

Based on application of heated bi‐metal strip bending theory to measured chip warp on 0.5 mm thick bare Corning® EAGLEXG® Glass and Corning Lotus™ NXT Glass, low substrate CTE minimizes chip warp. Different substrates have different effective process temperatures. Chip warp is relatively insensitive to substrate Young’s modulus vs. substrate CTE.

Thermal expansion of magnetron sputtered TiCxN1-x coatings studied by high-temperature X-ray diffraction

The coefficient of thermal expansion (CTE) of TiCxN1-x can be adjusted by changing the value x between 0 (i.e. pure TiN) and 1 (pure TiC), which makes this material exceptionally useful as base layer to adapt the mismatch between the CTEs of substrate and coating. However, no comprehensive data on the CTE of sputtered TiCxN1-x has been reported up to now. Thus, in this work eleven coatings with compositions ranging from pure TiN to pure TiC were deposited using non-reactive magnetron sputtering. The elemental and phase composition were obtained by elastic recoil detection analysis and Raman spectroscopy, respectively. Powders of the coating material were analyzed using high-temperature X-ray diffraction between room temperature and up to 1000 °C to determine the temperature dependent lattice parameters. Subsequently, these lattice parameters were fitted using second order polynomials with coefficients linearly depending on the carbon content. Thus, a formula for the CTE of TiCxN1-x valid between 25 and 1000 °C was deduced which showed that at room temperature TiN has the highest CTE of 8.12 × 10−6 K−1. The CTE gradually decreases with increasing carbon content to 7.55 × 10−6 K−1 for pure TiC. While the value for TiC only shows a small increase with temperature, the CTE of TiN increases strongly up to 11.1 × 10−6 K−1 at 1000 °C. The presented formula for the temperature dependent CTE of sputtered TiCxN1-x coatings allows to calculate the required composition for TiCxN1-x base layers, in order to tune their thermal expansion for the use in complex multilayered coatings.

Influence of substrate characteristics on residual stress of SLMed Inconel 718

Purpose Selective laser melting (SLM) is a promising additive manufacturing technology in the field of complex parts’ fabrication. High temperature gradient and residual stress are vital problems for the development of SLM technology. The purpose of this paper is to investigate the influence of substrate characteristics on the residual stress of SLMed Inconel 718 (IN718). Design/methodology/approach The SLMed IN718 samples were fabricated on the substrates with different characteristics, including pre-compression stress, materials and pre-heating. The residual stress at the center of the top surface was measured and compared through Vickers micro-indentation. Findings The results indicate that the residual stress reduces when the substrate contains pre-compression stress before the SLM process starts. Both substrate thermal expansion coefficient and thermal conductivity affect the residual stress. In addition to reducing the difference of thermal expansion coefficient between the substrate and the deposited material, the substrate with low thermal conductivity can also decrease the residual stress. Substrate pre-heating at 150°C reduces nearly 42.6 per cent residual stress because of the reduction of the temperature gradient. Originality/value The influence of substrate characteristics on the residual stress has been studied. The investigation results can help to control the residual stress generated in SLM processing.

Stress analysis of shielding electrode in chip with pressure sensor embedded in accelerometer

PurposeAnalysis of the thermal effects during the packaging process or in the actual operating environment is necessary to develop small monolithic integrated sensing chips with heterogeneous integration. The use of multiple layers and various materials in monolithic integrated sensing chips addresses the coefficient of thermal expansion (CTE) mismatch issue. The purpose of this study is to focus on the residual stress analysis of the shielding electrode, which is a metal film that prevents pull-in of proof-mass during anodic bonding in microelectromechanical system (MEMS) chips with pressure sensors embedded in an accelerometer.Design/methodology/approachThe finite element model of the chip was built by the commercial software ANSYS, and the residual stress was evaluated during the die attachment process for the shielding electrode. Various shielding electrode materials and a proposed design with a keep-out zone to reduce the residual stress are discussed, with a focus on the relationship between the geometric parameters of the chip and the residual stress for copper shielding electrodes of different thicknesses.FindingsThe results of the finite element analysis showed that the use of polysilicon as a shielding electrode in the proposed design generated the lowest residual stress because of its low CTE. The maximum stresses in both of in-plane and out-of-plane directions in the finite element model were reduced by keep-out zone design for the proposed design of the copper shielding electrode, and had 11 times reduction in out-of-plane direction especially, according to the nonlinear analysis as the stress concentration point in the shielding electrode moved. Moreover, the design with a thinner shielding electrode, thinner glass substrate and higher CTE of the glass substrate also lowered the maximum von Mises stress. On the other hand, the stress level during the operating temperature, without considering residual stress, overestimated up to five times in the proposed design.Originality/valueIn this study, valuable suggestions are proposed for the design of chips with pressure sensors embedded in accelerometers.

Response of molten silicate infiltrated Gd2Zr2O7 thermal barrier coatings to temperature gradients

The delamination tendency for bilayer gadolinium zirconate/yttria-stabilized zirconia (GZO/YSZ) thermal barrier coatings (TBCs) was investigated using a continuous laser-based thermal gradient test and a computational model for the analysis of multilayer structures. TBCs with different architectures were exposed to molten silicate compositions, representative of aero-engine deposits, and subjected to thermal cycles prescribed to impart specified levels of strain energy in the coating. The exposed surface of the intercolumnar gaps in the outer part of the GZO layer was found to rapidly dissolve into the intruding molten silicate and precipitate reaction products that seal the flow paths, limiting the penetration depth and the ensuing stiffening of the TBC. Nevertheless, the stiffened layer magnifies the thermal stresses in the coating upon thermal cycling. The influence of the thermal history and multilayer structure on the driving force for delamination was modeled and compared with the experimental results. The effects that the substrate coefficient of thermal expansion, the temperature gradient, and the TBC thickness have on the driving force for delamination were analyzed and the critical amount of stored elastic strain energy for failure under different scenarios was assessed.

Prediction of deformation during manufacturing processes of silicon interposer package with TSVs

The purpose of this paper is to analyze and predict the thermal deformation of the through silicon via (TSV) interposer package during the manufacturing process and to perform a parametric study to minimize the warpage and thermal stress. Samples were selected during different stages of the assembly to observe the thermal behavior change. The Digital Image Correlation (DIC) technique was employed to measure the real-time deformation of the samples under thermal loading. To make a finite element analysis (FEA) model, material properties were characterized by DIC and Dynamic Mechanical Analysis (DMA). Based on the material properties and deformation data determined by experiments, a validated FEA model was established. To reduce the modeling complexity and the computing time in the simulation, the C4/underfill layer, micro bump/underfill layer, and TSV interposer were assumed to be isotropic. The most effective material properties for the isotropic layers were calculated by the composite theory. Also, the simulation followed the sequential manufacturing processes to investigate the thermal deformation change of each step and to obtain a more accurate prediction result. The thermal behavior from simulation showed a good agreement with the experimental result and this verified simulation model was implemented for the parametric study. A series of simulations were carried out to minimize the package warpage. To avoid any delamination failures, the stresses at the interface between the interposer and underfill were also evaluated. The effect of the interposer underfill material property, substrate material property, substrate thickness, and TSV density (Cu volume fraction) in the interposer were studied. It has been shown that low modulus, low coefficient of thermal expansion (CTE), and high glass transition temperature (Tg) underfill, as well as a low modulus and low CTE substrate can mitigate the package warpage and stress development at the interface between interposer and underfill. Also, a larger Cu volume TSV interposer and thick substrate can lessen the warpage of the package and stress at the interface.

Solder Joint Reliability Assessment for a High Performance RF Ceramic Package

The prediction of long term solder joint reliability, (SJR), of microelectronic devices and packaging solutions continues to challenge the microelectronic packaging industry, particularly with the introduction of lead-free materials, the push for higher performance (frequency/speed/thermal) and lower unit cost. High performance packages are generally custom designed and therefore have minimal industry data on configuration specific reliability performance. In this application, the package substrate coefficient of thermal expansion, (CTE), was closely matched to the die resulting in a relatively large CTE mismatch between the package and organic PCB. In addition, the package RF and thermal performance requirements required this particular solution to be configured as a “cavity down” perimeter ball array with a large central ground pad to electrically couple the package to the PCB. Given the package's unique design requirements and CTE mismatch, even modest daily temperature swings of 20°C usually found in a controlled or “Central Office” environment could have an adverse impact on the interconnect reliability. This study provides an overview of the solder joint reliability assessment methodologies performed for a custom design lead-free, high performance RF package as part of the requirements to demonstrate compliance to product specifications. SJR life predictions were made for varying package BGA configurations using a multi-tiered approach using constitutive material models, thermo-mechanical finite element simulations, and material specific fatigue models. Empirical accelerated life testing was performed and a life prediction obtained through modeling was validated. Finally, statistical failure distributions were fit to empirical data and discussed in the context of absolute solder life predictions of small fractions unit failures, (100ppm).

Wet adhesion of epoxy–amine coatings on 2024-T3 aluminum alloy

To explore the influence of the molar epoxide-to-amine ratio E/NH on the coating adhesion strength, samples with E/NH ratios ranging from 0.6 to 1.4 were prepared and fully cured. Coatings with an E/NH value of 1.0 appeared to have the highest Tg and cross-link density, and the lowest water absorption ability, which was proved to be independent from solubility or free volume effects. Being verified by the classic “cross-hatch” and the more quantitative pull-off tests, the wet adhesion of coatings was found to be significantly influenced by the epoxide content. Excess epoxide groups highly likely to favor the formation of stronger adhesive bonding at coating–metal interface. No clear correlation could be established between the coating adhesion strength and their cross-link density and water-uptake. In addition, the measurements of the thermal expansion coefficients of substrate and coatings revealed the presence of a tensile internal stress, which is more pronounced for stoichiometric samples. The existence of compressive internal stress induced by water uptake was also confirmed by the adhesion tests on samples which were immersed in water for two days. In these samples, a partial recovery of adhesion strength was found, after the samples were dried for two days, indicating that the compressive internal stress deteriorated the load-bearing properties of adhesive bonds and contributed to debonding. This influence becomes larger as the coating thickness increases as well as the E/NH off-stoichiometry increases. Interestingly, for the samples possessing excess epoxide functional groups, a higher degree of recovery was obtained. This was not the case for coatings with excess amine, confirming that specifically the epoxide groups facilitate the formation of strong bonds against water at the polymer–metal interface.

Direct Coating Adherent Diamond Films on Fe-Based Alloy Substrate: The Roles of Al, Cr in Enhancing Interfacial Adhesion and Promoting Diamond Growth

Direct CVD deposition of dense, continuous, and adherent diamond films on conventional Fe-based alloys has long been considered impossible. The current study demonstrates that such a deposition can be realized on Al, Cr-modified Fe-based alloy substrate (FeAl or FeCrAl). To clarify the fundamental mechanism of Al, Cr in promoting diamond growth and enhancing interfacial adhesion, fine structure and chemical analysis around the diamond film-substrate interface have been comprehensively characterized by transmission electron microscopy. An intermediate graphite layer forms on those Al-free substrates such as pure Fe and FeCr, which significantly deteriorates the interfacial adhesion of diamond. In contrast, such a graphite layer is absent on the FeAl and FeCrAl substrates, whereas a very thin Al-rich amorphous oxide sublayer is always identified between the diamond film and substrate interface. These comparative results indicate that the Al-rich interfacial oxide layer acts as an effective barrier to prevent the formation of graphite phase and consequently enhance diamond growth and adhesion. The adhesion of diamond film formed on FeCrAl is especially superior to that formed on FeAl substrate. This can be further attributed to a synergetic effect including the reduced fraction of Al and the decreased substrate thermal-expansion coefficient on FeCrAl in comparison with FeAl, and a mechanical interlocking effect due to the formation of interfacial chromium carbides. Accordingly, a mechanism model is proposed to account for the different interfacial adhesion of diamond grown on the various Fe-based substrates.

Determination of heteroepitaxial layer relaxation at growth temperature from room temperature X-ray reciprocal space maps

Lattice-mismatched heteroepitaxial growth in compound semiconductor layer structures, e.g. metamorphic buffers, is frequently used to combine materials with favorable properties. A detailed understanding of the strain relaxation during growth is important to optimize the buffer layers and to achieve high material quality. We present a method to determine the epilayer relaxation at growth temperature from room temperature X-ray diffraction measurements. For this the lattice parameters are measured with (004) and (224) reciprocal space maps along two orthogonal <110> directions to account for anisotropic misfit strain relaxation. Dissimilar thermal expansion coefficients of substrate and epilayer are taken into consideration when calculating the lattice parameters and epilayer relaxation parameters at growth temperature. The application of this method is discussed for GaAsxP1−x metamorphic buffer structure on Si with eight lattice-mismatched layers showing a relaxation parameter of over 130% at room temperature. All layers were found to be nearly 100% relaxed at growth temperature. The use of this method for other compound semiconductors is discussed.

Out-of-Plane CTE Measurement Method for Freestanding Thin Films

An out-of-plane linear coefficient of thermal expansion (CTE) measurement method was developed to overcome the difficulty in measuring the in-plane deformation of freestanding thin films with a thickness of less than 1 μm. The out-of-plane profile measurement was relatively easy with the added advantage of simplicity, easy specimen preparation, and a simple test setup. White light interferometry was used for determining the out-of-plane thermal deformation as a function of temperature. Two types of supporting substrates, silicon and ZERODUR®, were used to account for the substrate effect on the CTE measurement. Attempts were made to fit the measured profiles using several peak functions and then find the optimal one. The test procedures were demonstrated using a freestanding 530-nm-thick aluminum film that was used in a previous in-plane measurement method. The calculated CTE value of this aluminum film was 23.7 ppm/°C, which was in good agreement with the in-plane measurement result. The out-of-plane CTE measurement method incorporating a zero CTE substrate was shown to be the most convenient and straightforward method.

Influence of the substrate thermal expansion coefficient on the morphology and elastic stress of CoSb3 thin films

AbstractDuring the post‐annealing and cooling process of CoSb3 thin films deposited on thermally oxidized Si(100) substrates, cracks occur at the surface of the films, which can be caused by the difference in thermal expansion coefficient of the substrate and the film. To investigate the crack formation, 40‐nm‐thick CoSb3 films were deposited at room temperature under ultra‐high vacuum (UHV) conditions onto various substrates, exhibiting different thermal expansion coefficients (2 × 10−6 to 12 × 10−6 K−1). All samples were post‐annealed in UHV at 500 °C for 1 h. The composition of the films was verified by Rutherford backscattering spectrometry. The phase formation and elastic stress of the films were analyzed by X‐ray diffraction, confirming the formation of the desired skutterudite phase, while the individual grains were studied by electron backscatter diffraction. In addition, the surface morphology and the roughness of the films were investigated by atomic force microscopy. For substrates with a thermal expansion coefficient between 9 × 10−6 and 11 × 10−6 K−1, crack formation can be prevented and a minimum in roughness was found, resulting also in a minimal value of the electrical resistivity.

Influence of Substrate Condictions on Thermal-Shocking Property of Sm&lt;sub&gt;2&lt;/sub&gt;Zr&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;7&lt;/sub&gt;/NiCoCrAlY Graded Thermal Barrier Coatings

The effect of substrate conditions, including material type, thickness and radius on thermal shocking properties of plasma sprayed Sm2Zr2O7/NiCoCrAlY functional graded thermal barrier coatings were analyzed by ANSYS—a finite element method software. Results show that thermal stresse in coatings increase with increasing of thermal expansion coefficients of substrates. The effect of substrate thickness can be ignored when it is greater than 20mm. Thermal stresses increase with radius increasing, however, they are almost not effected when substrate radius is over 18mm.

Investigation about Thermal Shock Property of Plasma-Spraying Sm&lt;sub&gt;2&lt;/sub&gt;Zr&lt;sub&gt;2&lt;/sub&gt;O&lt;sub&gt;7&lt;/sub&gt; Thermal Barrier Coatings with Different Substrate Condictions

Effect of substrate conditions, including material type, thickness and radius of substrate, on thermal-shocking stresses of plasma spraying Sm2Zr2O7/ NiCrCoAlY TBCs was analyzed through finite element method. Results show that radial stresses decrease with time increasing, and they decrease with the increasing of distance from center to edge along radius. However, axial residual stresses increse abruptly at the edge of specimen. All residual stresses increse with incresing of thermal expansion coefficient of substrate. Radial stresses increase with substrate thickness increasing, however, they are not effectd by substrate thickness if it is great than 20mm.and axial residual stresses and shear stresses are not effected by the substrate thickness. The maximum values of axial stresses and shear stresses were not effected by sustrate radius. and values of radial stresses remian invariable when substrate radius is over 18mm.