Thermal Compression Bonding Process Research Articles

Investigation of bonding mechanism for low-temperature Cu[sbnd]Cu bonding with passivation layer

The bonding mechanism of low-temperature CuCu thermal compression bonding (TCB) with passivation layer has been investigated in this research. After the structures of Cu with Au passivation and Cu with Pd passivation were bonded at 180 °C, the analyses of transmission electron microscope (TEM) were performed for the bonded structures to explore the bonding behavior of passivated-Cu during different stages of the TCB process. The results indicate that grain boundary diffusion of Cu leads to formation of amorphous Cu at the bonding interface in the passivated-Cu structure. Furthermore, diffusion of Cu atoms and recrystallization of amorphous Cu into polycrystalline Cu can eliminate voids at the bonding interface during the TCB process. Comparing to conventional Cu direct bonding with high crystallinity Cu at the bonding interface, passivated-Cu bonding can be achieved by much lower energy, leading to high quality bonding results with low thermal budget.

Thermomechanical reliability of a Cu/Sn-3.5Ag solder joint with a Ni insertion layer in flip chip bonding for 3D interconnection

Thermal compression bonding (TCB) has been widely used in flip chip bonding processes for three-dimensional integrated packaging. Therefore, studying the TCB process and solder joint structure is significant for improving reliability. In this study, a Ni layer was deposited between the Cu/Sn-3.5Ag solder bumps of upper and lower chips, and TCB process tests were carried out at different bonding temperatures, forces and times. The solder height at the top and bottom of the copper pillar were recorded. Through the establishment of a mathematical analysis model, the relationship between the solder joint height and maximum stress was analyzed theoretically, and the trend of the shear stress and solder joint height was obtained from die shear tests. Then, the solder joint morphology, strength and microstructure composition of the microbumps were observed after aging. Our results showed that the growth rate of intermetallic compounds (IMCs) for Cu/Sn-3.5Ag microbumps with a 25 μm diameter was 2.5 times those with a 100 μm diameter and that the Ni barrier layer prevented the diffusion of Cu in Sn-3.5Ag solder. In addition, the Ni layer improved the strength of the Cu/Sn-3.5Ag joints after aging. Finally, with extended aging time, the fracture site was found to move from the solder region to the Cu6Sn5 layer for the Cu/Sn-3.5Ag samples, while it remained at the Sn-3.5Ag/IMC interface for the Cu/Ni/Sn-3.5Ag samples.

Study of Electrodeposited High Entropy Single Element (HESE) Cu for Cu-Cu Direct Bonding

Electronic industry had required the smaller size and the higher performance of the device. According to Moore’s law, Technology node which also represents minimum feature size have shrank as rate of 0.7 and density of semiconductor have doubled about every two years. However, decreasing of technology node have been confronted with limit to more dense packaging by two-dimensional large-scale integrated circuits (ICs). Therefore, it is essential that developing of packaging techniques from two-dimensional ICs to three-dimensional ICs. The critical essentials of three-dimensional die stacking technology are TSV (through silicon via) and micro-bump. These technologies have contributed to the appearance of HBM (high bandwidth memory). HBM was packet of the memory, which composed of several stacked layers of the memory chips. Each memory chips were vertically connected by TSV and micro-bump. Thus, HBM have lower RC delay and higher performance of data processing than two-dimensional packaged memory. Even though advance of memory packaging have progressed, the lower pitch size and the higher density of memory chips have been requested ceaselessly in electronics packaging industry. Because the requiring of HPC (high performance computing) in the IT industry field such as AI (artificial intelligence), IOT (internet of things) and VR (virtual reality) have maintained. Especially, in order to accomplish vertical fine height between memory chips in the fine pitch packaging of HBM, micro-bump which consists of copper pillar, deposition of nickel diffusion barrier, and tin-silver or tin-silver-copper based cap have been used. TCB (thermal compression bonding) and reflow process (thermal aging) are typical fabrication process of micro-bump in HBM to combine between tin-silver or tin-silver-copper caps in the temperature range of 200 to 300 degree Celsius. However, there would be issues of reliability of micro-bump in fine-pitch bonding since intermetallic compound (IMC) formed through the reaction between under bump metallurgy and bump cap at smaller area due to lower pitch. For example, during reaction, if atomic flux difference between top and bottom occurred, kirkendall void which provides track of brittle fracture at IMC layer after reflow process could be formed. Moreover, during reflow, if side wetting of tin atoms from solder occurred, solder depletion can be appeared. Solder depletion also cause a serious issue of reliability of micro-bump. In order to remove these problems and make smaller interconnect, bump cap-less interconnect has been considered. Among many ideas related to bump cap-less interconnect, copper-to-copper direct bonding between copper pillar have been considered due to stability for electromigration, low resistivity and not utilizing IMC. However, more heat energy needs to trigger diffusion. [1] In this study, to decrease the challenges of bump bonding process, copper-to-copper direct bonding was conducted below 300℃. For triggering diffusion between copper below 300℃, high entropy single element (HESE) Cu film have been used. HESE Cu film is electrodeposited film which is reinforced self-annealing property. And HESE Cu films have been fabricated by electrochemical process at condition of low temperature and high current density. The self-annealing property of HESE Cu film arose from high defect density and non-equilibrium grain boundaries at the triple junction. The copper-copper bonding experiments were performed using thermal pressing machine. Thermal parameters and pressure parameters were varied to obtain proper bonded samples. The HESE Cu films were characterized by SEM (scanning electron microscope) and EBSD (Electron backscattering diffraction). The microstructure of HESE Cu films were examined by TEM (transmission electron microscopy). Chen, Chih, Doug Yu, and Kuan-Neng Chen. "Vertical interconnects of microbumps in 3D integration." MRS Bulletin40.3 (2015): 257-263.

Rotational solder self-alignment mechanics modeling for a flip chip in the presence of a viscous fluid

Advent of 2.5/3Dimensional (2.5/3D) integration using through-silicon vias (TSVs) enables the formation of high signal bandwidth, fine pitch, and short-distance interconnections in stacked dies but the new package configuration poses technical challenges in package assembly process. To pace industry demands, a new alternative, Thermal Compression Bonding (TCB), to the conventional Flip Chip on Board (FCOB) process has been being developed for the 3D stacking. Among process materials, epoxy flux (or no-flow underfill) draws high attention again due to its technical advantages in both TCB and mass reflow process. The conventional mass reflow with epoxy flux could provide outstanding benefits to 2.5D package assembly process. The new Low Cost High Throughput Flip Chip Assembly process is one such process requiring fewer processing steps, lower cycle times, and lower cost. In this new process, underfill is dispensed prior to chip placement, and solder reflow and underfill cure occur simultaneously. This reduces the cycle time required for manufacture; however, the presence of a viscous underfill affects the chips' capacity for self-alignment. In a companion study, self-alignment for a flip chip undergoing rectilinear translation was analyzed. This paper applies an equivalent analysis process to a flip chip undergoing rotation in the presence of a viscous underfill. Details of the modeling process are presented along with parametric studies and contrasted against pure translation case. Conditions and process parameters which are more conducive to realignment and those hampering realignment are presented.

Optimizing Diamond Heat Spreaders for Thermal Management of Hotspots for GaN Devices

As devices become smaller while still requiring high reliability in the presence of extreme power densities, new thermal management solutions are needed. Nowhere is this more evident than with the use of Gallium Nitride (GaN) transistors, where engineers struggle with the thermal barriers limiting the ability to achieve the intrinsic performance potential of GaN semiconductor devices. Emerging as a common solution to this GaN thermal management challenge are metallized diamond heat spreaders. In this paper, a diamond heat spreader has been applied with a hybrid Si micro-cooler for to cool GaN devices. Several different grades and thicknesses of microwave CVD diamond heat spreaders, as well as various bonding layers, are characterized for their thermal effects. The heat spreader is bonded through a TCB (thermal compression bonding) process to a Si thermal test chip designed to mimic the hotspots of 8 GaN units. The heat dissipation capabilities were compared through experimental tests and fluid-solid coupling simulations, both showing consistent results. In one configuration, using a diamond heat spreader 400μm thick with a thermal conductivity > 2000W/mK, to dissipate 70W heating power, the maximum chip temperature can be reduced by 40.4%, for test chips 100μm thick. And 10kW/cm2 hotspot heat flux can be dissipated while maintaining the maximum hotspot temperature under 160°C. The concentrated heat flux has been effectively reduced by the diamond heat spreader, and much better cooling capability of the Si micro-cooler has been achieved for high power GaN devices.