Testing Of VLSI Circuits Research Articles

On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams

Nowadays On-Line Testing (OLT) has became one the essential technique to detect faults in digital VLSI circuits which occur during their normal operation. However, most of the works on OLT reported in the literature are at the gate level and these techniques take reasonable computational time. The major reason being these schemes work at bit level, leading to state explosion problem. This issue can be addressed by developing OLT schemes at higher description levels of the circuits. In this paper, we present an OLT scheme at Register Transfer Level (RTL) description using High Level Decision Diagrams (HLDDs) and design corresponding on-line tester circuits. Experiments on different HLSynth92 benchmark circuits show that the test generation time is greatly improved using HLDDs, thus, large circuits can be easily handled. Further, it achieves lower area overhead at similar fault coverage compared to OLT schemes at gate level.

Dynamic Shift to Reduce Test Data Volume in Sequential Circuit Testing

Testing of VLSI circuits are normally a tedious process due to the test data volume. It leads to extra power dissipation along with minimum fault coverage.This project presents a test data volume (TDV) reduction method for designs utilizing extremely high compression configurations, and it enables reducing the pin count interfacing with the Automatic Test Equipment. Based on the encoding requirements for every test cube, the proposed test compression method changes the number of shift cycles used to load the test stimuli dynamically. No additional pins or modification of the existing scan chains is needed, making the proposed method work with standard benchmark sequential circuits. A modification is proposed to reduce the test access time ,that is single cycle access with hold mode and single cycle access without hold mode. Instead of a long scan chain ,if each of the scan cells are tested separately in a single clock will reduce the access time and hence the effective testing time of sequential circuits.

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults

Classical manufacturing test verifies that a circuit is fault free during fabrication, however, cannot detect any fault that occurs after deployment or during operation. As complexity of integration rises, frequency of such failures is increasing for which on-line testing (OLT) is becoming an essential part in design for testability. In majority of the works on OLT, single stuck at fault model is considered. However in modern integration technology, single stuck at fault model can capture only a small fraction of real defects and as a remedy, advanced fault models such as bridging faults, transition faults, delay faults, etc. are now being considered. In this paper we concentrate on bridging faults for OLT. The reported works on OLT using bridging fault model have considered non-feedback faults only. The basic idea is, as feedback bridging faults may cause oscillations, detecting them on-line using logic testing is difficult. However, not all feedback bridging faults create oscillations and even if some does, there are test patterns for which the fault effect is manifested logically. In this paper it is shown that the number of such cases is not insignificant and discarding them impacts OLT in terms of fault coverage and detection latency. The present work aims at developing an OLT scheme for bridging faults including the feedback bridging faults also, that can be detected using logic test patterns. The proposed scheme is based on Binary Decision Diagrams, which enables it to handle fairly large circuits. Results on ISCAS 89 benchmarks illustrate that consideration of feedback bridging faults along with non-feedback ones improves fault coverage, however, increase in area overhead is marginal, compared to schemes only involving non-feedback faults.

Implementation of Low Power TPG using LFSR and single input changing generator (SICG) for BIST Application: A Review

3, 4 Abstract: A novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits. The objective of the BIST is to reduce power dissipation without affecting the fault coverage. A new low power test pattern generator using linear feedback shift register (LFSR), called LP-TPG, and is presented to reduce the average power and peak power of the circuit by reducing the switching activities during test. In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the low power linear feedback shift register (LP-LFSR). The proposed scheme is evaluated by using, a synchronous pipelined 4x4 and 8x8 Braun array multipliers. The system-on chip (SoC) approach is adopted for implementation on Xilinx Field Programmable Gate Arrays (FPGAs). From the implementation results, it is verified that the testing power for the proposed method is reduced by a significant percentage.

Analysis of Power Reduction Techniques used in Testing of VLSI Circuits

One of the most important parameter over the past decade in VLSI design is the Power dissipation during manufacturing test, as the circuit consume much more power during test than functional mode of operation. This paper presents analysis of low power testing techniques by which Power optimized test patterns are obtained. The compaction technique has been validated using benchmark examples, and it has been shown that average 33% of test patterns have been reduced by which power is minimized. Evaluation of various techniques under consideration in this paper is carried out by open source tool ATALANTA for test pattern generation and MATLAB for optimization.

MULTI-DEGREE SMOOTHER FOR LOW POWER TESTABLE DIGITAL SYSTEM DESIGN USING BS-LFSR AND SCAN-CHAIN ORDERING TECHNIQUES

Testing of digital VLSI circuits entails many challenges as a consequence of rapid growth of semiconductor manufacturing technology and the unprecedented levels of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the average and peak power dissipation and test application time within acceptable limits. This dissertation proposes techniques to addresses these challenges during test. The first proposed technique, called bit-swapping LFSR (BS-LFSR), uses new observations concerning the output sequence of an LFSR to design a low-transition test-pattern-generator (TPG) for test-per-clock built-in self-test (BIST) to achieve reduction in the overall switching activity in the circuit-under-test (CUT). The obtained results show up to 28% power reduction for the proposed design, and up-to 63% when it is combined with another established technique. The proposed BS-LFSR is then extended for use in test-per-scantest vectors show up to 60%reduction in average power consumption. The BS-LFSR is then extended further to act as a multi-degree smoother for test patterns generated by conventional LFSRs before applying them to the CUT. Experimental results show up to 55% reduction in average power. Another technique that aims to reduce peak power in scan-based BIST is presented. The new technique uses a two-phase scan-chain ordering algorithm to reduce average and peak power in scan and capture cycles. Experimental results show up to 65% and 55% reduction in average and peak power, respectively. Finally, a technique that aims to significantly increase the fault coverage in test-Per scan BIST, while keeping the test-application time short, is proposed. The results obtained show a significant improvement in fault coverage and test application time compared with other techniques.

Fuzzy Linear Fractional Set Covering Problem with Imprecise Costs

Set covering problems are in great use these days, these problems are applied in many disciplines such as crew scheduling problems, location problems, testing of VLSI circuits, artificial intelligence etc . In this paper α -acceptable optimal solution is given for the fuzzy linear fractional set covering problem where fuzziness involved in the objective function. At first the fuzzy linear fractional problem is being converted in to crisp parametric linear fractional set covering problem then a linearization technique is used to obtain an optimal solution to this parametric problem. This optimal solution will also be the fuzzy optimal solution for the original problem. An example is also provided to illustrate the algorithm.

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing

At-speed or even faster-than-at-speed testing of VLSI circuits aims for high-quality screening of the circuits by targeting performance-related faults. On one hand, a compact test set with highly effective patterns, each detecting multiple delay faults, is desirable for lower test costs. On the other hand, such patterns increase switching activity during launch and capture operations. Patterns optimized for quality and cost may thus end up violating peak-power constraints, resulting in yield loss, while pattern generation under low switching activity constraints may lead to loss in test quality and/or pattern count inflation. In this paper, we propose design for testability (DfT) support for enabling the use of a set of patterns optimized for cost and quality as is, yet in a low power manner; we develop three different DfT mechanisms, one for launch-off shift, one for launch-off capture, and one for mixed at-speed testing. The proposed DfT support enables a design partitioning approach, where any given set of patterns, generated in a power-unaware manner, can be utilized to test the design regions one at a time, reducing both launch and capture power in a design-flow-compatible manner. This way, the test pattern count and quality of the optimized test set can be preserved, while lowering the launch/capture power.

Test Versus Security: Past and Present

Cryptographic circuits need to be protected against side-channel attacks, which target their physical attributes while the cryptographic algorithm is in execution. There can be various side-channels, such as power, timing, electromagnetic radiation, fault response, and so on. One such important side-channel is the design-for-testability (DfT) infrastructure present for effective and timely testing of VLSI circuits. The attacker can extract secret information stored on the chip by scanning out test responses against some chosen plaintext inputs. The purpose of this paper is to first present a detailed survey on the state-of-the-art in scan-based side-channel attacks on symmetric and public-key cryptographic hardware implementations, both in the absence and presence of advanced DfT structures, such as test compression and X-masking, which may make the attack difficult. Then, the existing scan attack countermeasures are evaluated for determining their security against known scan attacks. In addition, JTAG vulnerability and security countermeasures are also analyzed as part of the external test interface. A comparative area-timing-security analysis of existing countermeasures at various abstraction levels is presented in order to help an embedded security designer make an informed choice for his intended application.

ENUMERATION TECHNIQUE FOR SOLVING LINEAR FUZZY SET COVERING PROBLEM

In this paper a method for solving linear fuzzy set covering problem is defined. Set covering problems belong to the class of 0-1 integer program- ming problems that are NP-complete. Many applications arises having the set covering problems, switching theory, testing of VLSI circuits and line balancing often take on a set covering structure. Linear set covering problems involving coefficients in the objective function with some lack of precision are usual. To solve them several approaches have been proposed. In this paper a solution al- gorithm to fuzzy linear set covering problem is suggested. In order to defuzzify the problem the concept of vector ranking function is given and for obtaining efficient solution to the problem, an algorithm is constructed with a weighted sum approach.An example is illustrated to demonstrate the correctness of the proposed solution algorithm.

ENUMERATION TECHNIQUE FOR SOLVING LINEAR FRACTIONAL FUZZY SET COVERING PROBLEM

In this paper an enumeration technique for solving linear frac- tional fuzzy set covering problem is defined. Set covering problems belong to the class of 0-1 integer programming problems that are NP-complete. Many applications arises having the set covering problems, switching theory, testing of VLSI circuits and line balancing often take on a set covering structure. Linear fractional set covering problems involving coefficients in t objective function with some lack of precision are usual. To solve them several approaches have been proposed. In this paper a solution algorithm to fuzzy linear fractional set covering problem is suggested, in order to defuzzify the problem the concept of vector ranking function is presented further for obtaining efficient solution to the problem, a lexicographic approach is used. A linearization technique is used to obtain the optimal solution for crisp linear fractional set covering problem. An illustrative example is included to demonstrate the correctness of the proposed solution algorithm.

Survey of Low Power Testing of VLSI Circuits

The System-On-Chip (SoC) revolution challenges both design and test engineers, especially in the area of power dissipation. Generally, a circuit or system consumes more power in test mode than in normal mode. This extra power consumption can give rise to severe hazards in circuit reliability or, in some cases, can provoke instant circuit damage. Moreover, it can create problems such as increased product cost, difficulty in performance verification, reduced autonomy of portable systems, and decrease of overall yield. This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques

Particle Swarm Optimization Framework for Low Power Testing of VLSI Circuits

Power dissipation in sequential circuits is due to increased toggling count of Circuit under Test, which depends upon test vectors applied. If successive test vectors sequences have more toggling nature then it is sure that toggling rate of flip flops is higher. Higher toggling for flip flops results more power dissipation. To overcome this problem, one method is to use GA to have test vectors of high fault coverage in short interval, followed by Hamming distance management on test patterns. This approach is time consuming and needs more efforts. Another method which is purposed in this paper is a PSO based Frame Work to optimize power dissipation. Here target is to set the entire test vector in a frame for time period 'T', so that the frame consists of all those vectors strings which not only provide high fault coverage but also arrange vectors in frame to produce minimum toggling.

Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid

Double-tree-scan (DTS) is a new scan-path architecture that is deemed to be suitable for low-power testing of VLSI circuits. A full DTS resembles two complete k-level (k > 0) binary trees whose leaf nodes are merged pair-wise, and thus consists of exactly N$_{k}$ = 3 × 2$^{k}$ − 2 nodes. In this paper, the problem of planar straight-line embedding of a graph on a rectangular grid is investigated and an O(N$_{k}$) time algorithm for drawing it, is described. The embedding requires at most 2N$_{k}$ grid points, with an aspect ratio lying between 1 and f. Next, techniques of embedding a partial DTS is considered when the number of nodes n ≠ 3 × 2$^{k}$ − 2, for some k. Layouts of double-tree scan-paths for some benchmark circuits are also presented to demonstrate the results.

Static Test Compaction for VLSI Tests An Evolutionary Approach

The test compaction is one of most important requirement regarding the large scale integration (LSI) testing. The overall cost of a VLSI circuit's testing depends on the length of its ...

Hybrid System Approach to On-Line Testing of Mixed Signal VLSI Circuits: A Case Study of DC-DC Buck Converters

This work is concerned with the development of a method for the design of Mixed Signal VLSI circuits with on line testing capability. A novel theory of Fault Detection and Diagnosis of Hybrid Systems has been applied for the on-line detection of catastrophic stuck-at faults in mixed VLSI circuits. Based on this an FPGA based system has been developed to design a DC-DC buck converter with on-line testing capability. To the best of our knowledge the proposed methodology is one of the first attempts to provide a solution for On-Line Testing of mixed signal VLSI circuits using a formal theory, which is applicable to a very large class of low frequency analog circuits.

A Low-Cost Concurrent BIST Scheme for Increased Dependability

Built-in self-test (BIST) techniques constitute an attractive and practical solution to the difficult problem of testing VLSI circuits and systems. Input vector monitoring concurrent BIST schemes can circumvent problems appearing separately in online and in offline BIST schemes. An important measure of the quality of an input vector monitoring concurrent BIST scheme is the time required to complete the concurrent test, termed concurrent test latency. In this paper, a new input vector monitoring concurrent BIST technique for combinational circuits is presented which is shown to be significantly more efficient than the input vector monitoring techniques proposed to date with respect to concurrent test latency and hardware overhead trade-off, for low values of the hardware overhead.

DNA and quantum based algorithms for VLSI circuits testing

Testing of VLSI circuits is still a NP hard problem. Existing conventional methods are unable to achieve the required breakthrough in terms of complexity, time and cost. This paper deals with testing the VLSI circuits using natural computing methods. Two prototypical algorithms named as DATPG and QATPG are developed utilizing the properties of DNA computing and Quantum computing, respectively. The effectiveness of these algorithms in terms of result quality, CPU requirements, fault detection and number of iterations is experimentally compared with some of existing classical approaches like exhaustive search and Genetic algorithms, etc. The algorithms developed are so efficient that they require only ? N (where N is the total number of vectors) iterations to find the desired test vector whereas in classical computing, it takes N/2 iterations. The extendibility of new approach enables users to easily find out the test vector from VLSI circuits and can be adept for testing the VLSI chips.

Special issue on testing VLSI circuits

Special issue on testing VLSI circuits

Ultrafast superconducting single-photon optical detectors and their applications

We present a new class of ultrafast single-photon detectors for counting both visible and infrared photons. The detection mechanism is based on photon-induced hotspot formation, which forces the supercurrent redistribution and leads to the appearance of a transient resistive barrier across an ultrathin, submicrometer-width, superconducting stripe. The devices were fabricated from 3.5-nm- and 10-nm-thick NbN films, patterned into 10% for 405-nm radiation to 3.5% for 1550-nm photons. The detector response time and jitter were /spl sim/100 ps and 35 ps, respectively, and were acquisition system limited. The dark counts were below 0.01 per second at optimal biasing. In terms of the counting rate, jitter, and dark counts, the NbN single-photon detectors significantly outperform their semiconductor counterparts. Already-identified applications for our devices range from noncontact testing of semiconductor CMOS VLSI circuits to free-space quantum cryptography and communications.