SRAM Test Research Articles

Crack identification and evaluation in BEoL stacks of two different samples utilizing acoustic emission testing and nano X-ray computed tomography

A novel approach is presented to evaluate the mechanical stability of back end of line (BEoL) stacks. A SRAM test vehicle manufactured in 28 nm technology with copper pillar bumps is used. In a second step, the validity of the approach is also shown for a second sample manufactured in 22 nm technology and the experimental results are compared. To inflict damage to the BEoL stack of the respective semiconductor device, external forces are applied to the copper pillars (Cu-pillars) by shear loading using a tribo-indenter system. An acoustic emission (AE) detection sensor is attached to the sample to measure acoustic waves during the shear experiment as an indication for damage. The damage progression in the BEoL stack is extremely fast, hence details can't be resolved anymore with the piezo sensors of the tribo-indenter. However, due to the much higher temporal resolution, AE measurements give a more precise insight into the damage process. The resulting damages are imaged using nano X-ray computed tomography (nXCT) as well as scanning electron microscopy (SEM). The results provide a better understanding of the origin and the propagation of damages in the BEoL stack.

Radiation Tolerant SRAM Cell Design in 65nm Technology

In this paper, eight different SRAM cells are studied and evaluated with a 65nm CMOS technology. The cells were designed with radiation-hardening-by-design approaches including schematic and layout techniques. The eight types of cells were placed into eight pages of an SRAM test chip. The alpha and proton irradiation demonstrated that the Dual Interlocked Cell (DICE) has the best radiation-tolerant performance, but requires the largest area. The 6T and 11T cells designed with charge cancellation techniques can reduce soft errors up to 2-3 times with less area overhead. Several DICE variants were developed with reduced area overhead and showed SEU resilience performance equivalent to DICE. Simulation results are also presented in this paper to validate the findings.

SRAM Radiation Hardening Through Self-Refresh Operation and Error Correction

In Space applications, the scaling of transistors has made integrated circuits (ICs) more susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a memory device, this event is referred to as a Single Event Upset (SEU). Since SEU errors degrade system performance and eventually lead to system failure, the design of radiation-resilient memory is substantial. This paper presents a radiation resilient SRAM with a self-refresh scheme for lowering the number of errors in each row below a threshold number. The proposed self-refresh operation reads out the stored data and performs single error correction using a simple algorithm during its hold/idle mode. A 4KB SRAM test chip in 65nm CMOS technology demonstrates a significant reduction in errors with the self-refresh operation. When the SRAM test chip was exposed to accelerated proton radiation with an energy level of 39.38 MeV, the self-refresh scheme reduces the number of uncorrectable errors by $25\times $ and $8\times $ lesser for the fluence of $9.82\times 10^{11}$ particles/cm2 and $49.1\times 10^{11}$ particles/cm2, respectively.

An Efficient Wavelet Based Transient Current Test towards Detection of Data Retention Faults in SRAM

Advancements in integrated circuit technologies, increasing manufacturing complexity and incessant device scaling inflict new challenges in memory testing and demand for new, sophisticated test methods. Much research has been devoted to reducing the test time of Data Retention Fault (DRF) using March tests. Recent advancements in research rely on using transient current based tests for fault detection. As the test length of a transient current test is comparatively small when compared to other test methods, the probability of detection of this kind of fault during a test period is very low especially in the case of small memory arrays. Large variations in peak amplitude of voltage and charge may occur due to process variations which limits the detection capability of such tests. The main contribution of this paper is enhancing the detection of DRFs in SRAM using transient current test amidst process variations. In this paper, we implement an innovative approach to SRAM test - wavelet based transient supply current test with modified March sequence exploiting Read Equivalent Stress (RES) for DRF detection. The proposed technique can be merged with transient current test using Built-in-Current Sensors (BICS) resulting in full coverage of DRF. In comparison with other techniques that solely rely on software implementation for fault detection, the proposed technique significantly reduces hardware and performance penalties. Simulation results confirm that compared to other methods the proposed technique can provide high standards of reliability and efficiency in DRF detection.

Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics

This paper introduces a framework for designing data-dependent SRAMs taking advantage of statistical dependencies present in the binary values processed and stored in the intermediary stages of various algorithms. To demonstrate the framework, a reconfigurable conditional precharge (CP) SRAM is designed in a 28-nm fully-depleted silicon-on-insulator CMOS process. To reduce read power consumption, the SRAM reconfigures its prediction scheme for each column as the data statistics evolve. A 10T bit cell, a prediction-based CP circuit, and a compact column circuit implemented in a 16-kbit SRAM test chip demonstrate the power savings of 63%, 50%, and up to 69% for the applications sparse fast Fourier transform, object detection, and motion estimation, respectively, as compared with similar memories with naive prediction. Analysis tools for optimal prediction selection for the presented class of low-power memories are also provided.

The total ionizing dose response of a DSOI 4Kb SRAM

A 4K-bit SRAM with 0.2um Double Fully-Depleted Silicon-On-Insulator (DSOI) CMOS process is designed to examine circuit total ionizing dose (TID) and the back gate bias effect. Preview researches show that MOSFET electrical parameter shift due to TID damage can be compensated by back gate bias of the FDSOI technology. We can control the NMOS/PMOS back gate separately and discretionarily with DSOI structure which could improve circuit radiation tolerance. TID experiment results show that the total ionizing dose capability of the 4Kb SRAM test chip is above 1M rad (Si).

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization

Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040 $\mu \text{m}^{2}$ 6T SRAM bitcell is designed for high density (HD), and 0.049 $\mu \text{m}^{2}$ for high performance (HP). The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage ( $V_{\mathrm{ MIN}}$ ) and assist overheads. The dual-transient wordline scheme is proposed to improve the $V_{\mathrm{ MIN}}$ by 47.5 mV for the 128 Mb 6T-HP SRAM. The suppressed bitline scheme with negative bitline improves the $V_{\mathrm{ MIN}}$ by 135 mV for the 128 Mb 6T-HD SRAM. The FOM of PPA gain evaluates the optimum SRAM assist for the different bitcells based on the applications.

Investigation on MCU Clustering Methodologies for Cross-Section Estimation of RAMs

Various failure scenarios may occur during irradiation testing of SRAMs, which may generate different characteristic Multiple Cell Upset (MCU) error patterns. This work proposes a method based on spatial and temporal criteria to identify them.

Supply Voltage Dependence of Heavy Ion Induced SEEs on 65 nm CMOS Bulk SRAMs

Soft Error Rates (SER) of hardened and unhardened SRAM cells need to be experimentally characterized to determine their appropriate applications in radiation environments. This characterization is especially important when low supply voltage is preferred. In this paper, we developed an SRAM test chip with four cell arrays including two types of unhardened cells (standard 6T and subthreshold 10T) and two types of hardened cells (Quatro and DICE). This test chip was fabricated in a 65 nm bulk technology and irradiated by heavy ions at different supply voltages. Experimental results show that the SERs of 6T and 10T cells present significant sensitivities to supply voltages when the particle linear energy transfers (LETs) are relatively low. For Quatro and DICE cells, one does not consistently show superior hardening performance over the other. It is also noted that Quatro cells show significant advantage in single event resilience over 10T cells although they consume similar areas. TCAD simulations were carried out to validate the experimental data. In addition, the error amount distributions follow a Poisson distribution very well for each type of cell array.

Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

This paper presents a 9T multi-threshold (MTCMOS) SRAM macro with equalized bitline leakage and a content-addressable-memory-assisted (CAM-assisted) write performance boosting technique for energy efficiency improvement. A 3T-based read port is proposed to equalize read bitline (RBL) leakage and to improve RBL sensing margin by eliminating data-dependence on bitline leakage current. A miniature CAM-assisted circuit is integrated to conceal the slow data development with HVT devices after data flipping in write operation and therefore enhance the write performance for energy efficiency. A 16 kb SRAM test chip is fabricated in 65 nm CMOS technology. The operating voltage of the test chip is scalable from 1.2 V down to 0.26 V with the read access time from 6 ns to 0.85 $\mu {\rm s}$ . Minimum energy of 2.07 pJ is achieved at 0.4 V with 40.3% improvement compared to the SRAM without the aid of the CAM. Energy efficiency is enhanced by 29.4% between 0.38 V $\sim$ 0.6 V by the proposed CAM-assisted circuit.

Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs

Voltage scalable decoupled SRAMs operating at a subthreshold region have various challenges, such as deteriorated read bitline (RBL) swing resulting in read sensing failure and degraded cell stability due to the half-select write. This paper proposes an equalized bitline scheme to eliminate the leakage dependence on data pattern and thus improves RBL sensing and its resilience against process, voltage, and temperature variations. In addition, we propose a fast local write-back (WB) technique to implement a half-select-free write operation. With hierarchical bitline architecture, it facilitates a local read and a subsequent fast WB action to secure the original data without performance degradation. A 16-kb SRAM test chip has been fabricated in a 65-nm CMOS technology and achieved the minimum operating voltage of 0.24 V with a read access time of 4.88 μs.

Dynamic Test Methods for COTS SRAMs

In previous works, we have demonstrated the importance of dynamic mode testing of SRAM components under ionizing radiation. Several types of failures are difficult to expose when the device is tested under static (retention) mode. With the purpose of exploring and defining the most complete testing procedures and reveal the potential hazardous behaviors of SRAM devices, we present novel methods for the dynamic mode radiation testing of SRAMs. The proposed methods are based on different word address accessing schemes and data background: Fast Row, Fast Column, Pseudorandom, Adjacent (Gray) and Inverse Adjacent (Gray). These methods are evaluated by heavy ion and atmospheric-like neutron irradiation of two COTS SRAMs of 90 nm and 65 nm technology.

Adaptive static and dynamic noise margin improvement in minimum-sized 6T-SRAM cells

We present a novel SRAM technique for simultaneously enhancing the static and dynamic noise margins in six transistor cells implemented with minimum size devices using a design for manufacturability constrained layout. During each access, the word-line voltage (VWL) is internally reduced with respect to the cell and bit-line voltages that are maintained at nominal VDD. A specific VWL can be determined for each memory region, thus allowing for an adaptive approach. The benefits and drawbacks of the technique on the overall memory performance are thoroughly investigated through both simulations and experimental data. Simulations results show that this technique expands the read margin without an appreciable increase of memory area. Specifically, an improvement of 52.6% in static noise margin and a 24.5% in critical charge (parameter used to account for the dynamic stability) has been achieved with a VWL reduction of 20%. The impact of variability on SNM is reduced, while both read and write delay increase by a specific amount that should be considered as a tradeoff when setting the word-line voltage value. A 16Kbit SRAM test chip including the proposed technique has been fabricated in a 65nm CMOS technology. Silicon measurements confirm that the proposed technique improves cell stability during READ, which allows operating at relatively low values of VWL with a small impact on read time.

An Analysis of Industrial SRAM Test Results—A Comprehensive Study on Effectiveness and Classification of March Test Algorithms

This paper deals with efficient test algorithm identification of embedded SRAMs. The approach is based on silicon test results of automotive microcontroller devices, which tries to identify efficient tests by removing unnecessary test patterns that cover the same subset of faults. Results of an industrial case under 29 test algorithms and a large amount of chips are obtained; among them, efficient ones are identified.

A new IDDT test approach and its efficiency in covering resistive opens in SRAM arrays

In this article, an alternative approach to SRAM testing – the dynamic supply current test is presented, which is used to cover resistive opens considered as “hard detectable” type of physical defects. The investigation of the efficiency in unveiling open defects is based on the evaluation analysis carried out on a six transistor (6T) SRAM cell designed in a 90nm CMOS technology, where parasitic components of word lines, bit lines, and power supply lines are derived from a 4096-bit SRAM array. Three possible approaches to the dynamic supply current test are proposed and compared. Finally, achieved results are analyzed and discussed.

Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors

This brief proposes one-write-one-read (1W1R) and two-write-two-read (2W2R) multiport (MP) SRAMs for register file applications in nanoscale CMOS technology. The cell features a cross-point Write word-line structure to mitigate Write Half-Select disturb and improve the static noise margin (SNM). The Write bit-lines (WBLs) and Write row-access transistors are shared with adjacent bit-cells to reduce the cell transistor count and area. The scheme halves the number of WBL, thus reducing WBL leakage and power consumption. In addition, column-based virtual VSS control is employed for the Read stack to reduce the Read power consumption. Post-sim results show that the proposed scheme reduces both Write/Read current consumption by over 30% compared with the previous MP structure. The proposed scheme is demonstrated and validated by an 8-Kb 2W2R SRAM test chip fabricated in TSMC 40-nm CMOS technology.

SRAM standby leakage decoupling analysis for different leakage reduction techniques

SRAM standby leakage reduction plays a pivotal role in minimizing the power consumption of application processors. Generally, four kinds of techniques are often utilized for SRAM standby leakage reduction: Vdd lowering (VDDL), Vss rising (VSSR), BL floating (BLF) and reversing body bias (RBB). In this paper, we comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage. It is disclosed that the performance of these techniques depends on the leakage composition of the SRAM cell and temperature. This has been verified on a 65 nm SRAM test macro.

Fault Models and Test Methods for Subthreshold SRAMs

Due to the increasing demand of an extra-low-power system, a great amount of research effort has been spent in the past to develop an effective and economic subthreshold SRAM design. However, the test methods regarding those newly developed subthreshold SRAM designs have not yet been fully discussed. In this paper, we first categorize the subthreshold SRAM designs into three types, study the faulty behavior of open defects and address decoders faults on each type of designs, and then identify the faults which may not be covered by a traditional SRAM test method. We will also discuss the impact of open defects and threshold-voltage mismatch on sense amplifiers under subthreshold operations. A discussion about the temperature at test is also provided.

Testing Methodology of Embedded DRAMs

The embedded-DRAM (eDRAM) testing mixes up the techniques used for DRAM testing and SRAM testing since an eDRAM core combines DRAM cells with an SRAM interface (the so-called 1T-SRAM architecture). In this paper, we first present our test algorithm for eDRAM testing. A theoretical analysis to the leakage mechanisms of a switch transistor is also provided, based on that we can test the eDRAM at a higher temperature to reduce the total test time and maintain the same retention-fault coverage. Finally, we propose a mathematical model to estimate the defect level caused by wear-out defects under the use of error-correction-code circuitry, which is a special function used in eDRAMs compared to commodity DRAMs. The experimental results are collected based on 1-lot wafers with an 16 Mb eDRAM core.

Geant4 Analysis of n-Si Nuclear Reactions From Different Sources of Neutrons and Its Implication on Soft-Error Rate

This work examines nuclear events resulting from the interaction of atmospheric neutrons at ground level and different atmospheric-like sources with a silicon layer. Using extensive Geant4 simulations and in-depth data analysis, this study provides a detailed comparison between several facilities and natural environment in terms of nuclear processes, secondary ion production and fragment energy distribution. The different computed databases have been used in a second part of this work to estimate the Soft-Error Rate (SER) of a widely characterized 65 nm SRAM test circuit with the Tool suIte for rAdiation Reliability Assessment (TIARA Monte-Carlo simulation code). A detailed analysis is conducted to clarify the mechanisms leading to single and multiple cell upsets and to estimate the SER of a broad spectrum source from values obtained with monoenergetic simulations.