Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics

Abstract

This paper introduces a framework for designing data-dependent SRAMs taking advantage of statistical dependencies present in the binary values processed and stored in the intermediary stages of various algorithms. To demonstrate the framework, a reconfigurable conditional precharge (CP) SRAM is designed in a 28-nm fully-depleted silicon-on-insulator CMOS process. To reduce read power consumption, the SRAM reconfigures its prediction scheme for each column as the data statistics evolve. A 10T bit cell, a prediction-based CP circuit, and a compact column circuit implemented in a 16-kbit SRAM test chip demonstrate the power savings of 63%, 50%, and up to 69% for the applications sparse fast Fourier transform, object detection, and motion estimation, respectively, as compared with similar memories with naive prediction. Analysis tools for optimal prediction selection for the presented class of low-power memories are also provided.