Testing For Small-delay Defects Research Articles

Evaluation of the Impact of Technology Scaling on Delay Testing for Low-Cost AVS

With the continued down-scaling of IC technology and increase in manufacturing process variations, it is becoming ever more difficult to accurately estimate circuit performance of manufactured devices. This poses significant challenges on the effective application of adaptive voltage scaling (AVS) which is widely used as the most important power optimization method in modern devices. Process variations specifically limit the capabilities of Process Monitoring Boxes (PMBs), which represent the current industrial state-of-the-art AVS approach. To overcome this limitation, in this paper we propose an alternative solution using delay testing, which is able to eliminate the need for PMBs, while improving the accuracy of voltage estimation. The paper shows, using simulation of ISCAS’99 benchmarks with 28nm FD-SOI library, that using delay test patterns result in an error of 5.33% for transition fault testing (TF), error of 3.96% for small delay defect testing (SDD), and an error as low as 1.85% using path delay testing (PDLY). In addition, the paper also shows the impact of technology scaling on the accuracy of delay testing for performance estimation during production. The results show that the 65nm technology node exhibits the same trends identified for the 28nm technology node, namely that PDLY is the most accurate, while, TF is the least accurate performance estimator.

Generation of Effective 1-Detect TDF Patterns for Detecting Small-Delay Defects

Testing for small-delay defects (SDDs) has become necessary for high-quality products (e.g., automotive applications) as technology scales further and functional frequency increases. Traditional timing-unaware transition-delay fault (TDF) ATPG is not adequate for detecting SDDs. Commercial timing-aware ATPGs suffer from large CPU runtime and huge pattern count. However, a small pattern set with high SDD coverage is desired by industry. In this paper, a comprehensive procedure named parametric pattern generation (PPG) is proposed in order to meet these requirements. In the evaluation phase of PPG, a new metric is proposed to represent pattern characteristics when detecting SDDs and gross TDFs. In the selection phase of PPG, pattern quality is considered by excluding detection redundancy. PPG is mathematically modeled and solved using the gradient descent concept. By learning from the previous pattern selection efficiency, a new selection is performed in a more effective way until the pattern set is finally generated. While utilizing PPG, the final pattern set can be framed in 1-detect volume with high SDD detection efficiency while meeting the target TDF coverage. Experimental results on both IWLS and ISCAS'89 benchmarks demonstrate the efficiency of the proposed method.

Test compaction for small-delay defects using an effective path selection scheme

Testing for small-delay defects (SDDs) requires fault-effect propagation along the longest testable paths. However, identification of the longest testable paths requires high CPU time, and the sensitization of all such paths leads to large pattern counts. Dynamic test compaction for small-delay defects is therefore necessary to reduce test-data volume. We present a new technique for identifying the longest testable paths through each gate in order to accelerate test generation for SDDs. The resulting test patterns sensitize the longest testable paths that pass through each SDD site. An efficient dynamic test compaction method based on structural analysis is presented to reduce the pattern count substantially, while ensuring that all the longest paths for each SDD are sensitized. Simulation results for a set of ISCAS 89 and IWLS 05 benchmark circuits demonstrate the effectiveness of this method.

Crosstalk- and Process Variations-Aware High-Quality Tests for Small-Delay Defects

The population of small-delay defects (SDDs) in integrated circuits increases significantly as technology scales to 65 nm and below. Therefore, testing for SDDs is necessary to ensure the quality and reliability of high-performance integrated circuits fabricated with the latest technologies. Commercial timing-aware automatic test pattern generation (ATPG) tools have been developed for SDD detection. However, they only use static timing analysis reports in the form of standard delay format for path-length calculation and neglect important underlying causes, such as process variations, crosstalk, and power-supply noise, which can also induce small delays into the circuit and impact the timing of targeted paths. In this paper, we present an efficient pattern evaluation and selection procedure for screening SDDs that are caused by physical defects and by delays added to paths by process variations and crosstalk. In this procedure, the best patterns for SDDs are selected from a large repository test set. Experimental results demonstrate that our method sensitizes more LPs, detects more SDDs with a much smaller pattern count, and needs less CPU runtime compared with a commercial timing-aware ATPG tool.

Efficient Pattern Generation for Small-Delay Defects Using Selection of Critical Faults

Testing for small-delay defects (SDDs) has become necessary as technology further scales. Existing tools and methodologies for generating SDD patterns suffer from: limited long-paths sensitization capability, overwhelming pattern volume, time-consuming pattern generation process, and vague evaluations of pattern quality. Such situation places patterns in a dilemma where the generation and application effort are huge yet the results cannot reflect the physical phenomena clearly enough for correct binning and diagnosis. In this paper, we focus on establishing a pattern generation flow that produces patterns of high application value. Firstly, critical faults are identified in order to generate high-quality original pattern repository with n-detect ATPG.A novelpattern evaluation and selection method that further minimizes pattern count while maintaining the SDD detection ability is then presented. Top-off ATPG is then performed to ensure meeting the target fault coverage. Along with the flow, multiple evaluation metrics are also proposed to measure the pattern's efficiency on SDD coverage, unique SDD detection, detectable SDD size, long path distribution, etc. Experimental results demonstrate that the proposed critical fault-based method improves long path sensitization efficiency by 2.5× without impairing its average delay and saves approximately 80 % CPU runtime compared with total fault-based method. Comparing with timing-aware ATPG, the generated pattern set detects equivalent or even more SDDs with significantly reduced pattern count.

Testable Path Selection and Grouping for Faster Than At-Speed Testing

Faster than at-speed testing provides an efficient way for testing of small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is managed to be applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing based on path delay fault (PDF) model and single path sensitization criterion. An effective testable path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.