Test Wafers Research Articles

Fabrication, electrical characterization and sub-ng mass resolution of sub-μm air-gap bulk mode MEMS mass sensors for the detection of airborne particles

In this study, we propose to realize high-performance inertial Micro-Electro-Mechanical Systems (MEMS) mass sensors by the thick oxide as a mask layer fabrication technique. This method enables to reduce the air-gap to sub-μm in capacitively transduced MEMS with optical lithography and has been used to fabricate high aspect ratio sub-μm air-gap bulk mode MEMS mass sensors. MEMS devices have been designed and fabricated with the gap size as small as ~400 nm for ~38 μm thick SOI-based resonators (~95:1). Due to the conical characteristic of the gap, the mean air-gap has also been estimated as ~868 nm with 46 μm depth, which results in ~ 53:1 aspect ratio for the silicon test wafers that have been treated under the same conditions with the SOI-based devices. COMSOL simulation results and fabricated MEMS resonators coherently show that MEMS devices exhibit Lamé mode at 4.099 MHz resonance frequency with the estimated quality factor around 20,000, and extensional mode at 4.467 MHz with the estimated quality factors around 18,000 in the air. The motional resistance has been estimated as small as 27.28 Ω for the Lamé mode operating at 40 V. In this study, two different bulk modes have been considered as sensitive and uniform mass sensors for the detection of airborne particles. Then, minimum mass measurement capability of both modes has been experimentally estimated as 0.51 ng and 0.47 ng for Lamé and extensional modes, respectively. The latter, a proof-of-concept mass measurement has been conducted to deduce the resonance frequency shifts of both modes upon an added mass. This work demonstrates optimization of the thick oxide mask layer fabrication technique and realization of high aspect ratio bulk-mode MEMS mass sensors.

Incorporating Virtual Metrology Into Failure Prediction

In the semiconductor manufacturing process, wafer fabrication is followed by a wafer test, which filters out defective dies by performing several physical inspections. Only dies that pass the wafer test are used in an assembly and final test. However, a few of them eventually fail the final test as well. We address this issue by formulating a die-level failure prediction problem, focusing on utilizing the sampling inspections in the wafer test, which are performed only for a few sampled dies. Here, we propose a joint prediction model that simultaneously performs both virtual metrology and failure prediction tasks based on a multi-task learning scheme. The proposed model incorporates the virtual metrology task as missing value imputation for non-sampled dies to improve the failure prediction task. We demonstrate the effectiveness of the proposed model by evaluating it on real-world data from a semiconductor manufacturer.

A Wafer Map Yield Prediction Based on Machine Learning for Productivity Enhancement

Manufacturing productivity in the semiconductor industry is a key factor in determining the competitiveness of manufacturers. In order to enhance productivity, evaluating the productivity of wafer maps prior to production and optimizing the productivity of wafer maps is one of the most effective solutions. The productivity of a wafer map is evaluated in advance by considering various factors affecting wafer productivity such as: gross dies, shot counts, lithography throughputs, mask field occupancy (MFO), prices, etc. Manufacturing process information is not determined at the initial wafer map design stage. Predicting the yield of new wafer maps before fabrication is a difficult challenge due to lack of process information. However, a yield prediction model is required to precisely evaluate the productivity of new wafer maps, because the yield is directly related to the productivity and the design of wafer map affects the yield. In this paper, we propose a novel yield prediction model based on deep learning algorithms. Our approach exploits spatial relationships among positions of dies on a wafer and die-level yield variations collected from a wafer test without process parameters. By modeling these spatial features, the accuracy of yield prediction significantly increased. Furthermore, experimental results showed that the proposed yield model and approach helps to design wafer maps with up to 8.59% higher productivity.

Measurement of the stress-strain behavior of freestanding ultra-thin films

The stress-strain behavior of freestanding ultra-thin films (<100 nm) is characterized using residual-stress-driven structures. The proposed technique does not require an external sample loading setup and uses standard fabrication and metrology techniques that are available in the clean-room. A uniaxial load is applied to the freestanding test films using the residual stress of a well-characterized reference material. Highly cross-linked SU-8, a negative photoresist, is proposed as the reference loading material. The test wafer includes structures for in-situ calibration of the properties of the loading material. The geometry of the structures is varied to measure strains as high as 3.7%. The displacements of the freestanding test films are measured using digital image processing and used to measure the stress-strain response. Measurements on 63 nm thick passivated copper film stack show a slightly lower elastic modulus and a much higher yield strength than observed in bulk materials, and are in-line with the expectations from a nanocrystalline film with passivation. The properties of SU-8 and copper measured here are in good agreement with those measured using an alternate technique by the authors. As such, the proposed technique of residual-stress-driven structures is easy-to-replicate and serves as a useful in-line metrology tool that can be seamlessly implemented on coatings used in a semiconductor device production line.

Performance Evaluation of RF Generators with In-Situ Plasma Process Monitoring Sensors.

Plasma-processing equipment consists of numerous components, and RF power delivery system is one of the most critical for maintaining the requisite wafer quality. In this research, we investigate the use of In-Situ plasma process monitoring sensors to evaluate the performance of the RF generator used in plasma enhanced chemical vapor deposition (PECVD) equipment. We employ three kinds of In-Situ plasma process monitoring sensors, optical emission spectroscopy (OES), an optical plasma-monitoring sensor (OPMS), and a voltage-current (VI) probe, to monitor the plasma conditions produced by three different RF generators (RFGs). We found no significant differences among the test wafers. Thus, we conclude that the three RFGs each perform similarly in the PECVD system. We also found the OES is useful for analyzing the plasma chemistry and the degree of dissociation and ionization, the OPMS to be useful for monitoring the long-term stability in plasma processing, and the VI probe to be helpful for detecting instantaneous faults in semiconductor manufacturing.

A New Approach to Tackle Wafer Contact Mark Contamination Issues in Marangoni Drying

Introduction Wafer drying is the last and critical step in wet wafer surface preparation processes for a product finished with clean and dry surfaces (1). Among various wafer drying technologies, Marangoni drying has been the most commonly used application nowadays due to its advantages in many aspects (1-3). However, surface tension gradients generated by Marangoni effect might not be able to fully overcome the capillary force existing at the tight geometry of the contact area between wafers and a wafer holder, resulting in contact mark contamination issues, especially under an inspection condition with reduced wafer edge exclusion (Figure 1). In this paper, we demonstrate the application of a technological approach to enhance a complete drainage of water droplets at the wafer/holder contact points to significantly mitigate the contact mark contamination issue. Experimental Experiments were conducted on a GAMATM wafer cleaning station in NAURA-Akrion’s Applications Lab, in which a LuCIDTM dryer is used for the wafer drying process. The dryer was set to run a typical Marangoni process at fixed parameters, with the in-tank wafer holder as the only variable. Various numbers of 200mm bare Si test wafers, sandwiched with clean dummy wafers to serve a full loading condition, were placed to various slots of a full pitch process carrier for a test batch. To ensure a consistent degree of hydrophilic state of Si surfaces during the drying process, each wafer batch was processed with an SC1/QDR/Dry instead of a Dry Only recipe. Before and after a process run, test wafers were inspected with a KLA-Tencor SP1 at ≥100nm particle threshold with 2mm edge exclusion. Results Wafer contact mark incidence was evaluated by overlapping the “pre” and “post” wafer map of each test wafer to identify the specific contact mark signature. Figure 2 highlights the incidence with respect to frequency and severity of contact mark occurrence. The former indicates how many test wafers in a testing batch show contact mark contamination, while the latter presents the extent of particle clustering in a contact mark. It can be seen from Fig.2 that both the frequency and severity of contact mark contamination were significantly reduced with appropriate liquid drainage at the contact area between the test wafers and a modified in-tank holder. Conclusion Experiments were conducted to tackle the wafer contact mark issue in a Marangoni drying process. The capillary effect holding liquid droplets at wafer/holder contact points can be overcome by a drainage technology to significantly reduce the contact mark incidence. With the technological solution, the Marangoni process window can be broadened and, in turn, the robustness and performance of the drying process are enhanced. References D.C. Burkman, et. al., in Handbook of Semiconductor Wafer Cleaning Technology (ed.. W. Kern), Noyes Publications, Westwood, NJ, 1993, pp. 131-134.A.F.M. Leenaars, et. al., Marangoni Drying: A New Extremely Clean Drying Process, Langmuir, 1990, 6 (11), pp. 1701-1703.T. Vukosav, Substrate Drying Using Surface Tension Gradient Technology, R&D Magazine, 7/16/2013. https://www.rdmag.com/article/2013/07/substrate-drying-using-surface-tension-gradient-technology Figure 1

Study on La2O3 Wet Clean by pH Controlled Functional Water

Introduction For the dimensional scaling and performance enhancement of upcoming semiconductor devices, some novel materials have been implemented. In the high-k metal gate (HKMG) of logic and memory periphery transistors, some lanthanides and alkaline earth metal or their oxides, e.g. lanthanum oxide (La2O3) and magnesium oxide (MgO), have been proposed as a zero-thickness work function shifter [1-7]. These dielectric films are typically patterned by wet processing to enable a multiple threshold voltage [6,7]. However, the wet processes on the new materials are challenging because they dissolve easily in de-ionized wafer (DIW). In this paper, the impact of functional water rinsing on the dissolution and passivation of La2O3 films have been investigated. Experimental detail Coupon testFirst, the effect of etching due to pH was tested. The pH of the solution was adjusted by ammonia or hydrochloric acid. Moreover, O3, H2, H2O2 was added to the ammonia water which dissolution suppression has confirmed, and the effects of their solutions were tested.(2) Wafer test We tested using 10 mm × 10 mm coupon which was cut from 300 mm La2O3 wafers. And the La2O3 coupon was immersed in various dilute solutions under open air conditions. After immersion, the La concentration in the solution was analyzed by ICP-MS. And we calculated the La dissolution amount from these results. The DIW and some functional waters, e.g. CO2 dissolved water (CO2Water), ultra-diluted NH4OH (NH4OH water) , ultra-diluted NH4OH and ultra-diluted H2O2 (NH4OH/H2O2 water), were prepared by using a Kurita functional water unit (HS-13, Kurita Water Industries), which has the capability of injection and mixing CO2 (1 – 40 ppm) and NH4OH (1 – 100 ppm). The 300 mm blanket La2O­3 wafers were processed on a single wafer wet cleaning tool (SU-3200, SCREEN Semiconductor Solutions) connected with the functional water unit. First, We had cleaning tests using CO2 water, DIW, NH4OH water, NH4OH/H2O2 water. Moreover, in order to clarify the dissolution suppression mechanism, the wafer surfaces after cleaning with each solution were analyzed by XRR. Results and discussion Coupon test La2O3 + 6H+ → 2La3 + +3H2O (1).La2O3 + 3H2O → 2La(OH)3 (2).In addition, when H2, O3 and H2O2 were added to ammonia water of pH 10.4, Suppression effects were confirmed by H2O2 added, but we did not have the effect by H2 and O3 gases added(2) Wafer test Several functional waters have been evaluated for the introduction of novel materials and applications for leading edge semiconductor device manufacturing. In case HKMG patterning is required to remove La2O3, CO2W rinsing is preferred. Meantime, NH4OH water and NH4OH/H2O2 water rinsing could preserve the La2O3 layer. Conclusions Cleaning test was performed on a 300 mm La2O3 wafer and the dissolution rate was calculated by performing wafer weight change. Figure 3 shows the etching behavior of La2O3 films treated by DIW, CO2water and NH4OH water and NH4OH/H2O2 water. The results show that the La2O3 film dissolves in CO2water and DIW, of which the pH is acidic or neutral. And XRR measurement ressults are Figure 4, It was suggested that the La2O3 surface after various rinse reatments was formed of La (OH)3. The La (OH) 3 film is thicker by the NH4OH water and NH4OH/H2O2 water cleaning than in the DIW only cleaning. Therefore, it is considered that passivation with a hydroxide film is generated and dissolution is suppressed by setting it as an alkaline region. Regarding the RMG La2O3 patterning for the PMOS devices, it would be required to remove La2O3. Meantime, the La2O3 layer should be preserved for the NMOS devices [6]. Relevant wet etching and rinsing solutions should be used for each patterning step.On the other hand, the dissolution of La2O3 is drastically suppressed in NH4OH water, which is an alkaline solution. Therefore, the La2O3 surface would be passivated by its hydroxide:The results show that La2O3 have following reaction in acidic or neutral solution:Figure 1 is shown that the influence pH on the etching rate of La2O3. By the coupon test, we clarified that the dissolution of La2O3 can be suppressed by raising pH. From this test, it was found that the etching amount was sharply reduced from about pH 1.2 to about 8, and was hardly dissolved over pH 10. Figure 1

An RF-to-DC Rectifier Based on Tunable Threshold Diodes

This paper proposed a Dickson RF-to-DC rectifier based on floating-gate MOS diodes with tunable threshold voltages to improve RF input sensitivity and to counter process variation in logic CMOS foundry technology. When compensation by active circuits is excluded for system reasons, prior works relied on the availability of diodes with nearly zero threshold voltage in a mixed-signal process, but was unavoidably susceptible to process variation and leakage currents at low thresholds. Our proposed rectifier can have each constituent diode tuned to its optimal threshold at the wafer testing stage to maximize the operational output voltage at various loads and to compensate device-level variations. An optimization algorithm was implemented to automatically take the output voltage as feedback for system calibration in a short duration. The measurements of the tunable-threshold rectifier show > 4dB improvement in input sensitivity compared to the rectifier built by foundry-provided zero-threshold transistors. The proposed circuits can be combined with other techniques including high- ${Q}$ impedance matching for input voltage boosting and hierarchical tandem stages for further improvement on operating conditions. With a ${Q}\,\,{=}$ 10 matching network, −26 dBm sensitivity and 22% efficiency can be achieved for about 0.5 V dc output to a $500~{k} {\Omega }$ load at 570 MHz.

Learning Quality Rating of As-Cut mc-Si Wafers via Convolutional Regression Networks

This paper investigates deep convolutional neural networks (CNNs) for the assessment of defects in multicrystalline silicon (mc-Si) and high-performance mc-Si wafers for solar cell production based on photoluminescence (PL) images. We identify and train a CNN regression model to forecast the I-V parameters of passivated emitter and rear cells from given PL images of the as-cut wafers. The presented end-to-end model directly processes the PL image and does not rely on the human-designed image feature. Domain knowledge is replaced by a model based on a huge variety of empirical data. The comprehensive dataset allows for the evaluation of the generalizability of the model with test wafers from bricks and manufacturers not presented in the training set. We achieve mean absolute prediction errors as low as 0.11%abs in efficiency for test wafers from “unknown” bricks, which improves handcrafted feature-based methods by 35%rel at simultaneously lower computational costs for prediction. Samples with high prediction errors are investigated in detail showing an increased iron point defect concentration.

A modular application specific active test environment for high-temperature wafer test up to 300 °C

Abstract Applications in harsh environment such as high temperatures require electronic devices for signal amplification, calculations and digital interfaces. These devices often contain ASICs (application specific integrated circuits) which are suitable for high temperatures above 125 °C. For functionality verification of these high-temperature ASICs a high-temperature wafer test environment is necessary. This article describes a high-temperature wafer test setup which can be used up to 300 °C. It is based on a modular concept for a maximum of 48 test channels. The combination of three modular components (contact needle system, thermal insulation chamber and active probe card) allows adapting the setup to different ASICs and pad layouts. The active probe card operates at temperatures below 65 °C during 300 °C wafer test temperature. It is mounted on the thermal insulation chamber for signal amplification, defined loads or generation of precise input signals. This modular concept significantly shortens the development time for the high-temperature wafer test and thus saves time and reduce the costs of ASIC development.

Compact and Low Loss Microwave Idlers for Low Frequency Integrated Circuits

Two design methodologies for realization of low frequency (less than 20 GHz) compact and low loss microwave idlers have been proposed in this paper. Such idlers can be used for realizing low frequency higher order (6X or more) harmonic mixers or multipliers on monolithic integrated technology. Low frequency higher order harmonic mixers or multipliers are generally avoided due to higher losses and board space consumed by multiple idlers. The present proposed methods of idler design are based on realization of idlers by combining distributed microstrip transmission line and lumped components. The approach helps in transmitting the desired frequency with lower insertion loss and providing more rejection to the undesired frequencies. The design proposal has been demonstrated by designing an idler for 3 GHz LO side of a 6X harmonic MMIC mixer. This mixer utilizes 6th harmonic of the 3 GHz LO for generating 18 GHz output RF signal by frequency mixing. The idler for 3 GHz LO rejects dc, IF and selective even harmonics of LO; 6 GHz, 12 GHz and 18 GHz. On wafer test results of the developed 6X harmonic MMIC mixer has substantiated the idler design.

Feature Extraction From Analog Wafermaps: A Comparison of Classical Image Processing and a Deep Generative Model

Semiconductor manufacturing is a highly innovative branch of industry, where a high degree of automation has already been achieved. For example, devices tested to be outside of their specifications in electrical wafer test are automatically scrapped. In this paper, we go one step further and analyze test data of devices still within the limits of the specification, by exploiting the information contained in the analog wafermaps. To that end, we propose two feature extraction approaches with the aim to detect patterns in the wafer test dataset. Such patterns might indicate the onset of critical deviations in the production process. The studied approaches are: 1) classical image processing and restoration techniques in combination with sophisticated feature engineering and 2) a data-driven deep generative model. The two approaches are evaluated on both a synthetic and a real-world dataset. The synthetic dataset has been modeled based on real-world patterns and characteristics. We found both approaches to provide similar overall evaluation metrics. Our in-depth analysis helps to choose one approach over the other depending on data availability as a major aspect, as well as on available computing power and required interpretability of the results.

변분 오토인코더와 세그넷 기반 웨이퍼 불량패턴 탐지

Wafer bin maps (WBMs) represent the wafer test results in semiconductor processes. In WBMs, identifying the defect patterns are significant because the defect patterns can be used to detect the root causes of a defect. However, WBM researches in a real application suffer from insufficient training data for pattern analysis, so it is hard to apply machine learning techniques. Moreover, it is significant to classify the die, which is the minimum unit in a wafer, for identifying accurate causes, but the previous studies were conducted for the wafers. In this study, we use a variational autoencoder to generate new WBMs samples to build an accurate classifier for defect patterns. We then propose a die-wise defect segmentation system. This system aims to enable classification the cause of defects by using SegNet, a deep convolutional encoder-decoder architecture. To demonstrate the robustness and effectiveness of the proposed methodology, we conducted an experimental evaluation to compare the accuracy of the proposed approach than the ones of two variants of autoencoders. The experimental study confirmed that the proposed approach shows superior performance in the results.

Spatial Correlated Data Monitoring in Semiconductor Manufacturing Using Gaussian Process Model

In semiconductor manufacturing, various wafer tests are conducted in each stage. The analysis and monitoring of collected wafer testing data plays an important role in identifying potential problems and improving process yield. There exists three variation sources: 1) lot-to-lot variation; 2) wafer-to-wafer variation; and 3) site-to-site variation, which means the measurements cannot be considered independently. However, most existing control charts for monitoring wafer quality are based on the assumption that data are independently and identically distributed. To deal with the variations, we propose a mixed-effects model incorporating a Gaussian process to account for the variations. Based on the model, two control charts are implemented to detect anomalies of the measurements which can monitor the changes of the variations and the quality of products, respectively. Simulation studies and results from real applications show that this model and control scheme is effective in estimating and monitoring the variation sources in the manufacturing process.

Fabrication and Charge Deduction Based Sensitivity Analysis of GaN MOS-HEMT Device for Glucose, MIG, C-erbB-2, KIM-1, and PSA Detection

This paper presents the applicability of a high-resolution AlGaN/AlN/GaN metal oxide semiconductor-high electron mobility transistor (MOS-HEMT) for multiple bio detection and analysis of its sensitivity through a charge deduction based approach. The biomarkers of interest chosen in this paper include c-erbB-2, the breast cancer biomarker whose detection from saliva has been modeled. In this approach, the effective gate bias deduced through the model is applied to the fabricated device. High sensitivity of 0.054 mA/μgmL -1 , about nine times higher than the existing/conventional device, is attained here due to the modification of device epi design and use of MOS-gate. Similarly equivalent gate bias/interface charge has been deduced for other biomarkers such as prostate specific antigen, kidney injury molecule, monokine induced by interferon gamma, and glucose oxidase Enzyme, and effective sensitivities of 0.91 mA/μgmL -1 , 0.254 mA/μgmL -1 , 0.48 mA/ngmL -1 , and 2.06 mA/mmolL -1 , respectively, have been attained. The aim of the paper is developing an analytical model to analyze the sensitivity of the fabricated MOS-HEMT device with Al2O3 as gate dielectric (using on wafer testing) before the real packaging or sample introduction to ensure the device usability as a sensor for a dedicated detection. The methodology used here has been validated by comparison of the device sensitivity with real-time pH detection sensitivity. The device showcases high sensitivity of 1.83 mA/pH. The comparison of sensitivity with existing systems proves that the fabricated device overpowers the existing systems with huge marginal increase in sensitivities attained.

Three-point and four-point mechanical bending test modeling and application in solar cells

&lt;sec&gt;Silicon (Si)-wafer-based solar cells have dominated the global market with a share exceeding 90% due to their abundant source material and well-known physical and chemical properties. The brittleness of silicon material limits its further applications. It is necessary to investigate the material strength properties of Si wafer and/or Si solar cells, which can guide the fabrication process of Si solar cells to avoid breaking the Si wafers. The Si material strength properties have been extensively investigated by the methods of three-point bending test and four-point bending test. However, the difference between these two methods has not been studied so far.&lt;/sec&gt;&lt;sec&gt;In this work, the mechanical strength properties of monocrystalline silicon (c-Si) wafer and bifacial c-Si solar cells are measured by three-point bending test and four-point bending test respectively. The average value of the maximum bending displacements has a little discrepancy between the results of the three-point bending test and four-point bending test methods. It is worth noting that the degree of dispersion of the Si wafer test results of the three-point bending test is larger than those of the four-point bending test. And the results of the dispersion of the Si bifacial solar cells, obtained from the two bending test methods, show no difference between them due to the existence of metalized electrodes. Whether the measured sample is Si wafer or Si solar cell, the average value of the maximum load, obtained from the four-point bending test, is higher than that from the three point-bending test method, and the average value of the fracture strength, obtained from the four-point bending test, is lower than that from the three-point bending test method. By establishing the models of different beams, the applied load gets dispersed through two bars of the four-point bending test method, whereas the applied load is directly applied to the sample through one bar of the three-point bending test method, which can explain the relatively large difference between these two test methods.&lt;/sec&gt;

High-aspect ratio mechanical microdrilling process for a microhole array of nitride ceramics

In semiconductor industry, wafer testing requires a microhole array constructed by high-density holes below ϕ 100 μm for stabilizing the microprobe used in conduction testing. This study conducted mechanical microdrilling experiments of a nitride ceramic sheet to investigate the effects of drilling parameters on quality characteristics of the microhole drilled. Fabrications of a high-aspect ratio microhole must be implemented by segmented machining. A center pilot hole was first made and then drilled the microhole by a two-segment process. Drilling factors analyzed in this study included depth of the center pilot hole, depth ratio of the hole segments, and machining parameters of cutting speed (spindle rotation rate), tool feed rate, and step in peck drilling in the microdrilling. Because both diameter and position of the microhole affect the functionality of hole array directly, this is a multi-objective problem. This study proposes a new decision method for deriving the optimal parameter level set in the multi-object problem based on the level effects obtained from Taguchi’s analyses. In addition, this study used a scanning electron microscopy (SEM) to observe the influences of drilling stroke on flank wear of the microdrill. This study implemented two series experiments of ϕ 69 μm and ϕ 55 μm with aspect ratios of 15.36 and 11.64, respectively. Experimental results indicate that applying the optimal parameter level set derived in ϕ 55 μm experiment could obtain excellent performances after the drilling stroke of 384 mm, 600 holes drilled. The microdrills have fulfilled a high use efficiency.

Statistical comparison of field height correction by Z-stage movement versus height-correction hardware in a modern electron-beam lithography tool

Modern electron-beam lithography tools are expected to operate within very tight specifications [S. Babin, S. Borisov, V. Militsin, T. Komagata, and T. Wakatsuki, Proc. Soc. Photo-Opt. Instrum. 9984, 998406 (2016)], in order to meet lithographic requirements for today’s and tomorrow’s cutting-edge electronic and photonic device fabrication. Specifications for linewidth fidelity, field stitching, and absolute feature placement accuracy demand the highest levels of performance. In this work, the performance of the hardware height compensation mechanism in a modern Gaussian-beam, vector-scan lithography tool is statistically compared with the use of the Z stage to correct for height on a field-by-field basis, in order to determine the method most likely to yield the best writing performance on a nonflat substrate. A test sample is prepared by writing an array of square marks on a 4 in. Si wafer. Four marks per field are written, using the four corners of the writing field. After development, the wafer is coated with metal and the resulting marker array is formed via lift-off. The test wafer is then reloaded into the lithography tool. For each writing field, the positions of each of the four marks are found, with respect to the center of the field. The fields are visited in a spiral-out order, beginning near the center of the wafer. Location of the marks can be performed under two different conditions: fixed Z position with normal height compensation active or with Z position adjusted to bring the substrate to reference the height before locating marks in each field. No height compensation is used in the latter case. Subsequent statistical and graphical analysis of the collected data provides insight into the dynamics of the tool’s height correction capabilities and helps to inform the choice of Z-drive motion versus hardware height correction. In addition, should anomalies be observed, the analysis provides useful diagnostic information.

An acoustic emission sensor system for thin layer crack detection

We present a new method for semiconductor layer characterization enabling simultaneous crack generation and detection based on the established acoustic emission testing. In this paper, we explain the test concept and failure mechanism of diamond tip indentation with acoustic wave measurement on oxide layers by analytical modeling and computer-aided simulations. For this purpose, an innovative design of a sensor-indenter system was developed and experimentally verified. In further tests, the new acoustic crack detection method is correlated with proven optical inspection methods and the good reproducibility of the measurement is demonstrated. The high sensitivity and resolution of this method offer new opportunities for thin layer characterization at lower time and cost. The new high-efficient method can be used especially for process qualification for semiconductor wafer test, where oxide cracks can be induced by sharp probes causing electrical failure of the chip.

300 mm Wafer Development for Pattern Collapse Evaluations

Over the past decade, many advanced drying techniques have been developed to reduce and prevent pattern collapse of high aspect ratio (HAR) structures after wet processing. However, different dimensions, profiles and materials of HAR structures used in literature make it difficult to compare the efficiency of different drying processes. In this work, standard 300 mm wafer test structures, characterization and analysis techniques have been developed for quantitative analysis of pattern collapse rate as a function of the intrinsic mechanical property of HAR structures. Such standardized single wafer evaluations are important for benchmarking different drying techniques.