Test Set Size Research Articles

High-level delay test generation for modular circuits

Circuits containing functional blocks (modules) whose implementation details are not available pose major problems for delay fault testing. High-level testing methods are needed, but they often generate excessively large test sets to ensure good realization-independent fault coverage. This paper extends high-level delay fault models to large modular logic circuits by demonstrating that a hierarchical approach to delay test generation for modular circuits is feasible. Module implementation and input pattern pair requirements for robust delay testing are proposed along with a new fault model, the module path delay fault (MPDF) model. A test generation program called Module PATH delay test generator for MPDFs is presented, which exploits binary decision diagrams to increase its efficiency. Experimental results evaluating the proposed technique are presented, which show that it achieves a significant reduction in test set size compared to nonhierarchical approaches.

Reducing the number of specified values per test vector by increasing the test set size

Test sets consisting of incompletely specified test vectors for full-scan circuits have applications in input test data compression and power reduction. Earlier procedures for reducing the percentage of specified values in a given test set maintained the test set size. A procedure is described that starts from a given (compact) test set and reduces the percentage of specified values by replacing a selected test vector with a subset of test vectors that have fewer specified values per test vector and together detect the same subset of faults. By applying this replacement process iteratively, the procedure provides a series of solutions with increasing test set sizes and decreasing numbers of specified values per test vector. The importance of considering a series of solutions is demonstrated in the application of input test data compression.

Test chip experimental results on high-level structural test

Using complex (high-level) gates, such as multiplexers, full adders, etc., for automatic test pattern generation (ATPG) has several advantages. It makes ATPG faster and potentially reduces the size of the test set that needs to be applied. A variety of other techniques are used to reduce the size of test sets for digital chips. They typically rely on preserving the single-stuck-fault coverage of the test set. This article presents data obtained from applying a variety of test sets on the ELF35 test chip and recording the test escapes. The data presented show the test quality effect of using complex gates as fault sites. The article also shows the impact of test compaction and reduced fault coverage on the test quality.

Huffman-Based Test Response Coding

SUMMARY Test compression /decompression is an efficient methodfor reducing the test application cost. In this letter we propose a responsecompression method based on Huffman coding. The proposed methodguarantees zero-aliasing and it is independent of the fault model and thestructure of a circuit-under-test. Experimental results of the compressionratio and the size of the encoder for the proposed method are presented. key words: Hu ff man code, test compression, test response, test applicationtime, ATE 1. Introduction As the size and complexity of VLSI circuits increase, thesize of test sets for the circuits also increases. The increasein test set size requires larger storage and longer time totransport test sets from the storage device of a VLSI tester(ATE) to the circuit-under-test (CUT). To overcome thisproblem, some methods using compression/decompressionof test sets have been proposed. In the proposed scheme,a given test input set T is compressed into T by a datacompression technique and stored in a VLSI tester storage.While a CUT on a chip is tested, the compressed test inputset

Modeling and Predicting Biological Performance of Contact Stabilization Process Using Artificial Neural Networks

In this paper, the microfauna distribution data of a contact stabilization process were used in a neural network system to model and predict the biological activity of the effluent. Five uncorrelated components of the microfauna were used as the artificial neural network model input to predict the dehydrogenase activity of the effluent (DAE) using back-propagation and general regression algorithms. The models’ optimum architectures were determined for the back-propagation neural network (BPNN) model by varying the number of hidden layers, hidden transfer functions, test set size percentages, and initial weights. Comparison of the two model prediction results showed that the genetic general regression neural network model demonstrated the ability to calibrate the multicomponent microfauna, and yielded reliable DAE close to that resulting from direct experimentation, and thus was judged superior to BPNN models.

Refinement in statechart testing

Abstract An existing statechart testing method developed by the authors allows a tester to show the equivalence of the behaviour of an implementation of some software system to its Harel statechart specification, by testing. This requires a rather large test set and satisfaction of certain requirements for both a specification and an implementation. Introduction of additional constraints permits reduction in a test set size, without weakening of the conclusions obtained by testing. This paper describes how a test set can be derived from a relatively big statechart and investigates the role of a few specific constraints in the reduction of test set size, depending on where in the system structure these constraints are used. The main contribution of the paper is a demonstration that enforcing relatively weak constraints in the right place of a system's structure makes it possible to reduce the size of a test set by many orders of magnitude. The practical use of the contribution is to help developers structure a system under construction in such a way that it is completely testable using the described testing method with few additional constraints. Copyright © 2004 John Wiley & Sons, Ltd.

Water Testing Natural Rubber Latex Condoms: A Comparison of Surveillance Test Methods

Abstract Manufacturers, consumers, and regulators use various water test methods to test the integrity of the barrier offered by natural rubber latex condoms. The purpose of this study is to analyze three alternative water test methods and determine which is the best method for detecting holes in condoms. Three types of holes (laser, acupuncture, and 28 gage insulin needles), approximating defects that occur in condoms, were placed in condoms and then into equal size test sets for testing by six laboratories for the purpose of evaluating the three alternative methods: the ASTM method, the ISO/FDA method, and the CSI/FHI method. Each method shares a hang portion for 1 min, and then uses a different form of manipulation; either elevate (ASTM), roll (ISO/FDA), or squeeze (CSI/FHI). The interlaboratory study data indicate the CSI/FHI is the most sensitive method for locating holes in condoms, becoming more sensitive as the defect approaches the closed end.

Forward selection radial basis function networks applied to bacterial classification based on MALDI-TOF-MS

Forward selection improved radial basis function (RBF) network was applied to bacterial classification based on the data obtained by matrix-assisted laser desorption/ionization time-of-flight mass spectrometry (MALDI-TOF-MS). The classification of each bacterium cultured at different time was discussed and the effect of parameters of the RBF network was investigated. The new method involves forward selection to prevent overfitting and generalized cross-validation (GCV) was used as model selection criterion (MSC). The original data was compressed by using wavelet transformation to speed up the network training and reduce the number of variables of the original MS data. The data was normalized prior training and testing a network to define the area the neural network to be trained in, accelerate the training rate, and reduce the range the parameters to be selected in. The one-out-of-n method was used to split the data set of p samples into a training set of size p−1 and a test set of size 1. With the improved method, the classification correctness for the five bacteria discussed in the present paper are 87.5, 69.2, 80, 92.3, and 92.8%, respectively.

Exact computation of maximally dominating faults and its application to n-detection tests for full-scan circuits

The size of an n-detection test set increases approximately linearly with n. This increase in size may be too fast when an upper bound on test set size must be satisfied. A test generation method is proposed for obtaining a more gradual increase in the sizes of n-detection test sets, while still ensuring that every additional test would be useful in improving the test set quality. The method is based on the use of fault-dominance relations to identify a small subset of faults (called maximally dominating faults) whose numbers of detections are likely to have a high impact on the defect coverage of the test set. Structural analysis obtains a superset of the maximally dominating fault set. A method is proposed for determining exact sets of maximally dominating faults. New types of n-detection test sets are based on the approximate and exact sets of maximally dominating faults. The test sets are called (n,n2)-detection test sets and (n,n2,n3)-detection test sets. Experimental results demonstrate the usefulness of these test sets in producing high-quality n-detection test sets for the combinational logic of ISCAS-89 benchmark circuits.

Efficient Transition Fault ATPG Algorithms Based on Stuck-At Test Vectors

This paper proposes novel algorithms for computing test patterns for transition faults in combinational circuits and fully scanned sequential circuits. The algorithms are based on the principle that [email protected] vectors can be effectively used to construct good quality transition test sets. Several algorithms are discussed. Experimental results obtained using the new algorithms show that there is a 20% reduction in test set size, test data volume and test application time compared to a state-of-the-art native transition test ATPG tool, without any reduction in fault coverage. Other benefits of our approach, viz. productivity improvement, constraint handling and design data compression are highlighted.

Boosted leave-many-out cross-validation: the effect of training and test set diversity on PLS statistics.

It is becoming increasingly common in quantitative structure/activity relationship (QSAR) analyses to use external test sets to evaluate the likely stability and predictivity of the models obtained. In some cases, such as those involving variable selection, an internal test set--i.e., a cross-validation set--is also used. Care is sometimes taken to ensure that the subsets used exhibit response and/or property distributions similar to those of the data set as a whole, but more often the individual observations are simply assigned 'at random.' In the special case of MLR without variable selection, it can be analytically demonstrated that this strategy is inferior to others. Most particularly, D-optimal design performs better if the form of the regression equation is known and the variables involved are well behaved. This report introduces an alternative, non-parametric approach termed 'boosted leave-many-out' (boosted LMO) cross-validation. In this method, relatively small training sets are chosen by applying optimizable k-dissimilarity selection (OptiSim) using a small subsample size (k = 4, in this case), with the unselected observations being reserved as a test set for the corresponding reduced model. Predictive errors for the full model are then estimated by aggregating results over several such analyses. The countervailing effects of training and test set size, diversity, and representativeness on PLS model statistics are described for CoMFA analysis of a large data set of COX2 inhibitors.

Linear size test sets for certain commutative languages

We prove that for each positive integer n, the finite commutative language En = c (a 1 a 2 ...an ) possesses a test set of size at most 5n. Moreover, it is shown that each test set for E n has at least n -1 elements. The result is then generalized to commutative languages L containing a word w such that (i) alph(w ) = alph}(L ); and (ii) each symbol a ∈ alph}(L ) occurs at least twice in w if it occurs at least twice in some word of L : each such L possesses a test set of size 11n , where n = Card(alph(L )). The considerations rest on the analysis of some basic types of word equations.

Fault detection in a tristate system environment

Embedded computers commonly rely on multiple-board systems, called tristate system environments. These environments consist of an interconnect and drivers or receivers with tristate features and boundary scan capabilities. The authors present a comprehensive fault model that provides 100 percent fault coverage and minimizes test set size.

Forward-looking fault simulation for improved static compaction

Fault simulation of a test set in an order different from the order of generation (e.g., reverse- or random-order fault simulation) is used as a fast and effective method to drop unnecessary tests from a test set in order to reduce its size. We propose an improvement to this type of fault simulation process that makes it even more effective in reducing the test-set size. The proposed improvement allows us to drop tests without simulating them based on the fact that the faults they detect will be detected by tests that will be simulated later, hence the name of the improved procedure: forward-looking fault simulation. We present experimental results to demonstrate the effectiveness of the proposed improvement.

Test set compaction algorithms for combinational circuits

This paper presents a new algorithm, essential fault reduction, for generating compact test sets for combinational circuits under the single stuck-at fault model, and a new heuristic for estimating the minimum single stuck-at fault test set size. These algorithms together with the dynamic compaction algorithm are incorporated into an advanced automatic test pattern generation system for combinational circuits, called MinTest. MinTest found better lower bounds and generated smaller test sets than the previously published results for the ISCAS85 and full scan versions of the ISCAS89 benchmark circuits.

Novel test pattern generators for pseudoexhaustive testing

Pseudoexhaustive testing of a combinational circuit involves applying all possible input patterns to all its individual output cones. The testing ensures detection of all detectable multiple stuck-at faults in the circuit and all detectable combinational faults within individual cones. Test pattern generators based on coding theory principles are not tailored to a specific circuit as they do not utilize any structural information. They usually generate test sets that are several orders of magnitude larger than the minimum size pseudoexhaustive test set required for a specific circuit. In this paper, we describe hardware efficient test pattern generators that employ knowledge of the circuit output cone structures for generating minimal test sets. Using our techniques, we have designed generators that generate minimum size test sets for the ISCAS benchmark circuits.

Test set size minimization and fault detection effectiveness: A case study in a space application

An important question in software testing is whether it is reasonable to apply coverage-based criteria as a filter to reduce the size of a test set. An empirical study was conducted using a test set minimization technique to explore the effect of reducing the size of a test set, while keeping block coverage constant, on the fault detection strength of the resulting minimized test set. Two types of test sets were examined. For those with respect to a fixed size, no test case screening was conducted during the generation, whereas for those with respect to a fixed coverage, each subsequent test case had to improve the overall coverage in order to be included. The study reveals that regardless of how a test set is generated, with or without any test case screening, block minimized test sets have a size/effectiveness advantage, in terms of a significant reduction in test set size and with almost the same fault detection effectiveness, over the original non-minimized test sets.

Estimating the uncertainty in estimates of root mean square error of prediction: application to determining the size of an adequate test set in multivariate calibration

Root mean square error of prediction (RMSEP) is widely used as a criterion for judging the performance of a multivariate calibration model; often it is even the sole criterion. Two methods are discussed for estimating the uncertainty in estimates of RMSEP. One method follows from the approximate sampling distribution of mean square error of prediction (MSEP) while the other one is based on performing error propagation, which is a distribution-free approach. The results from a small Monte Carlo simulation study suggest that, provided that extreme outliers are removed from the test set, MSEP estimates are approximately proportional to a χ 2 random variable with n degrees of freedom, where n is the number of samples in the test set. It is detailed how this knowledge can be used to determine the size of an adequate test set. The advantages over the guideline issued by the American Society for Testing and Materials (ASTM) are discussed. The expression derived by the method of error propagation is shown to systematically overestimate the true uncertainty. A correction factor is introduced to ensure approximate correct behaviour. A close agreement is found between the uncertainties calculated using the two complementary methods. The consequences of using a too small test set are illustrated on a practical data set.

Efficient techniques for dynamic test sequence compaction

Dynamic test sequence compaction is an effective means of reducing test application time and often results in higher fault coverages and reduced test generation time as well. Three simulation-based techniques for dynamic compaction of test sequences are described. The first technique uses a fault simulator to remove test vectors from the test sequence generated by a test generator if the vectors are not needed to detect the target fault, considering that the circuit state may be known. The second technique uses genetic algorithms to fill the unspecified bits in a partially-specified test sequence in order to increase the number of faults detected by the sequence. The third technique uses test sequences provided by the test generator as seeds in a genetic algorithm, and better sequences are evolved that detect more faults. Significant improvements in test set size, fault coverage, and test generation time have been obtained over previous approaches using combinations of the three techniques.

Low-cost modular totally self-checking checker design for m-out-of-n code

We present a low-cost (hardware-efficient) and fast totally self-checking (TSC) checker for m-out-of-n code, where m/spl ges/3, 2m+1/spl les/n/spl les/4m. The checker is composed of four special adders which sum the 1s in the primary inputs added by appropriate constants, two ripple carry adders which sum the outputs of the biased-adders, and a t-variable two-rail code checker tree which compares the outputs of the two ripple carry adders, where k=[log/sub 2/(n-m)+1]. All the modules are composed of 2-input gates and inverters. Compared with previous nonmodular methods, our TSC checker has a lower hardware and time complexity. Our method reduces the hardware complexity and circuit delay of the checker from O(n/sup 2/) to O(n) and from O(n) to O(log/sub 2/n), respectively. Compared with recent modular methods, our TSC checker has about the same hardware and time complexity, but is applicable to a much broader range of n. In summary, our method is superior to existing methods for the considered range of n. In addition, our TSC checker can easily be tested (the test set size of our TSC checker is relatively small) and implemented in VLSI for its modular structure.