Test Pattern Generation Approach Research Articles

An exquisitely sensitive variant-conscious post-silicon Hardware Trojan detection

Hardware Trojans, malicious modifications or additions to circuit elements, are often introduced during outsourced stages of IC manufacturing. Their presence in hardware security platforms became a concern after incidents like the Syrian RADAR failure and the Kill-switch incident. Existing Trojan detection techniques mostly focus on netlist-level identification and overlook process variation challenges in post-silicon ICs. In this work, we introduce a novel golden free and highly sensitive detection method that addresses process variations and various sources of noise. Our approach achieves enhanced detection sensitivity by (i) utilizing an efficient circuit partitioning method that takes into account post-silicon noises, ensuring post-silicon validation through pre-silicon analysis, (ii) implementing a technique to mitigate the impact of systematic and random variations within and between dies, (iii) developing a variation-aware test pattern generation approach that utilizes a bit-flipping technique, leading to low transition net switching and increasing the likelihood of activating Trojans. We evaluate the sensitivity of our detection approach using a custom tool called relative power difference (RPD). To validate our method, we conduct experiments on the ISCAS’89 benchmark and the AES-128 circuit, testing against various Trojans reported in the literature. Our results demonstrate outstanding detection sensitivity for inserted Trojans across different levels of noise.

A Comprehensive Test Pattern Generation Approach Exploiting the SAT Attack for Logic Locking

The need for reducing manufacturing defect escape in today's safety-critical applications requires increased fault coverage. However, generating a test set using commercial automatic test pattern generation (ATPG) tools that lead to zero-defect escape is still an open problem. It is challenging to detect all stuck-at faults to reach 100% fault coverage. In parallel, the hardware security community has been actively involved in developing solutions for logic locking to prevent IP piracy. In logic locking, locks are inserted in different locations of the netlist to modify the original functionality. Unless the correct key is programmed into the IC, the circuit functions incorrectly. Unfortunately, the Boolean satisfiability (SAT) based attack, introduced in [1], can determine the secret key efficiently, and break different logic locking schemes. In this paper, we propose a novel test pattern generation approach using the powerful SAT attack on logic locking. A stuck-at fault is modeled as a locked gate with a secret key, where it can effectively deduce the satisfiable assignment with reduced backtracks under key initialization of the SAT attack. The input pattern that determines the key is a test for the stuck-at fault. We propose two different approaches for test pattern generation. First, a single stuck-at fault is targeted, and a corresponding locked circuit with one key bit is created. This approach generates one test pattern per fault. Second, we consider a group of faults and convert the circuit to its locked version with multiple key bits. The inputs obtained from the SAT attack tool are the test set for detecting this group of faults. Our approach can find test patterns for all hard-to-detect faults that were previously undetected in commercial ATPG tools. The proposed test pattern generation approach can efficiently detect redundant faults as well. We demonstrate the effectiveness of the approach on ITC'99 benchmarks. The results show that we can detect all the hard-to-detect faults and identify redundant faults and a 100% stuck fault coverage is achieved. In addition, we show that test generation time saving becomes significant for Approach 2 as multiple faults help reduce or remove conflicts.

ATPG for Delay Defects in Current Mode Threshold Logic Circuits

An automatic test pattern generation approach to detect delay defects in a circuit consisting of current mode threshold logic gates is introduced. Each generated pattern should excite the maximum propagation delay at the fault site. Manufactured weights may vary, and maximum delay is ensured by applying an appropriately generated set of patterns per fault. Experimental results show the efficiency of the proposed methods.

Test Pattern Generation with Low Power for Delay Faults in Digital Circuits by Evolution Method with Hybrid Strategies

The high power consumption during circuit test process can produce unwanted failures or take effects on circuit reliability, therefore the reduction of both peak power and average power of circuit test is necessary. A test pattern generation approach is presented in this paper for the delay faults in digital circuits, the approach makes use of the evolution method with the hybrid strategies to produce the test vectors with low power consumption. First of all, a pair of vectors that may detect a delay fault is coded as an individual. A lot of individuals constitute the populations. Secondly, the test vectors with low power are produced by the evolution of these populations. Many new individuals are randomly produced and are added into every evolution step, and the mutation mode of individuals is related to other individuals in the current population. A lot of experimental results show that the test vectors with low power for the delay faults in digital circuits can be produced by the approach proposed in this paper, and the approach can get the large reduction of power consumption when compared with random test generation algorithm.

GENERATING TEST PATTERNS FOR FPGA CIRCUITS: A QUANTUM COMPUTING APPROACH

This paper presents an effective test pattern generation approach for FPGA circuits by applying quantum computing algorithms. A prototypical new algorithm named QFPGA is developed utilizing the properties of quantum theory, such as quantum superposition and quantum parallelism. The effectiveness of this technique in terms of result quality, CPU requirements, fault detection and number of iterations is experimentally compared with some of the existing classical approaches, like exhaustive search, simulated annealing and genetic algorithms. The algorithm developed is so efficient that it requires only √N (N is the total number of vectors) iterations to find the desired test vector, whereas in classical computing it takes N/2 iterations. Simulation results on various benchmark circuits are also covered in this paper. The extendability of the new approach enables users to easily find the test vector from FPGA circuits and can be adapted for testing FPGA chips.

Simulation-Based Functional Test Generation for Embedded Processors

Deterministic functional test pattern generation has been a long-standing open problem, which is an important problem to be solved for both design verification and manufacturing testing. One key in developing a practical functional test pattern generation approach is to avoid the exponential growth of the test generation complexity in terms of the design size. This work proposes a novel functional test generation approach where simulation results are used to guide the generation of additional tests. Our methodology avoids the complexity growth issue by converting some modules in a design into simpler and more efficient models. Then, these models are used to facilitate the actual test generation process. We develop two sets of techniques to achieve these conversions: Boolean learning for random logic and arithmetic learning for datapath modules. We demonstrate the effectiveness and discuss the. limitations of these techniques through experiments on benchmark circuits. Last, we validate the overall test generation methodology based on the OpenRISC 1200 microprocessor