Test Generation Model Research Articles

Dynamic Test Stimulus Adaptation for Analog/RF Circuits Using Booleanized Models Extracted From Hardware

Test stimulus generation algorithms for analog/RF circuits rely on iterative simulation of the circuits concerned and are extremely computation-intensive. Our objective is to speed up test stimulus generation while allowing tests to be optimized dynamically (adapted) across diverse process corners that a device under test (DUT) is experiencing during manufacturing without compromising test quality. To achieve this, we propose to dynamically recognize devices from unknown process corners during manufacturing test and create Booleanized models of these devices from measurements performed on hardware. The cumulative ensemble of Booleanized models across different devices is used to (re-) optimize tests depending on observed performance statistics. The use of Booleanized models for test generation allows orders of magnitude speed up in test computation time while allowing emulation of devices long after they have shipped to the customer. The method is demonstrated using the alternative test methodology developed in prior research and allows the tests concerned to adapt to process shifts in a dynamic manner during device manufacture. The simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques.

Exploiting Model Morphology for Event-Based Testing

Model-based testing employs models for testing. Model-based mutation testing (MBMT) additionally involves fault models, called mutants, by applying mutation operators to the original model. A problem encountered with MBMT is the elimination of equivalent mutants and multiple mutants modeling the same faults. Another problem is the need to compare a mutant to the original model for test generation. This paper proposes an event-based approach to MBMT that is not fixed on single events and a single model but rather operates on sequences of events of length k ≥ 1 and invokes a sequence of models that are derived from the original one by varying its morphology based on k . The approach employs formal grammars, related mutation operators, and algorithms to generate test cases, enabling the following: (1) the exclusion of equivalent mutants and multiple mutants; (2) the generation of a test case in linear time to kill a selected mutant without comparing it to the original model; (3) the analysis of morphologically different models enabling the systematic generation of mutants, thereby extending the set of fault models studied in related literature. Three case studies validate the approach and analyze its characteristics in comparison to random testing and another MBMT approach.

Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip

The verification of system-on-chip is challenging due to its high level of integration. Multiple components in a system can behave concurrently and compete for resources. Hence, for simulation-based verification, we need a methodology that allows one to automatically generate test cases for testing concurrent and resource-competing behaviors. We introduce the use of a transfer-resource graph (TRG) as the model for test generation. From a high abstraction level, TRG is able to model the parallelism between heterogeneous interaction forms in a system. We show how TRG is used in generating test cases of resource competitions and how these test cases are structured in event-driven test programs. For coverage, TRG can be converted to a Petri net, allowing one to measure the completeness of concurrency in simulation.

Analysis of Test Generation Complexity for Stuck-At and Path Delay Faults Based on k-Notation

In this paper, we discuss the relationship between the test generation complexity for path delay faults (PDFs) and that for stuck-at faults (SAFs) in combinational and sequential circuits using the recently introduced τk-notation. On the other hand, we also introduce a class of cyclic sequential circuits that are easily testable, namely two-column distributive state-shiftable finite state machine realizations (2CD-SSFSM). Then, we discuss the relevant conjectures and unsolved problems related to the test generation for sequential circuits with PDFs under different clock schemes and test generation models.

Abstractions for Model-Based Testing

The idea of model-based testing is to compare the I/O behavior of an explicit behavior model with that of a system under test. This requires the model to be valid. If the model is a simplification of the SUT, then it is easier to check the model and use it for subsequent test case generation than to directly check the SUT. In this case, the different levels of abstraction must be bridged. Not surprisingly, experience shows that choosing the right level of abstraction is crucial to the success of model-based testing. We argue that models for specification purposes, models for test generation, and models for full code generation are likely to be different. The paper classifies and discusses different abstractions. It is intended as a step towards guidelines for those who build behavior models to the end of testing.

An exact solution to the minimum size test pattern problem

This article addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized. This problem has different applications in testing, including the identification of "don't care" conditions to be used in the synthesis of Built-In Self-Test (BIST) logic. The proposed solution is based on an integer linear programming (ILP) formulation which builds on an existing Propositional Satisfiability (SAT) model for test pattern generation. The resulting ILP formulation is linear on the size of the original SAT model for test generation, which is linear on the size of the circuit. Nevertheless, the resulting ILP instances represent complex optimization problems, that require dedicated ILP algorithms. Preliminary results on benchmark circuits validate the practical applicability of the test pattern minimization model and associated ILP algorithm.

Testing refinements of state‐based formal specifications

A specification provides a concise description of a system, and can be used as both the benchmark against which any implementation is tested, and also as a means to generate tests. Formal specifications have potential advantages over informal descriptions because they offer the possibility of reducing the costs of testing by automating part of the testing process. This observation has led to considerable interest in developing test generation techniques from formal specifications, and a number of different methods have been derived for state-based formalisms such as Z, B and VDM. However, after tests have been derived from a formal specification, the specification might be refined further before it is implemented, and therefore a mechanism is needed to relate the abstract tests to the refined implementation. The purpose of this paper is to provide such a method by exploring the relationship between testing and refinement. In this paper a model for test generation is used which constructs a finite state machine (FSM) from a Z specification by using a Disjunctive Normal Form (DNF) partition analysis of the state and operations. The finite state machine is then used to derive suitable test suites. The paper decribes a way of calculating an FSM for a refinement from an abstract FSM together with the information about the refinement embodied in the retrieve relation. This means that it is possible to test an implementation by generating a new concrete finite state machine from a set of abstract tests. Copyright © 1999 John Wiley & Sons, Ltd.

Testing refinements of state-based formal specifications

A specification provides a concise description of a system, and can be used as both the benchmark against which any implementation is tested, and also as a means to generate tests. Formal specifications have potential advantages over informal descriptions because they offer the possibility of reducing the costs of testing by automating part of the testing process. This observation has led to considerable interest in developing test generation techniques from formal specifications, and a number of different methods have been derived for state-based formalisms such as Z, B and VDM. However, after tests have been derived from a formal specification, the specification might be refined further before it is implemented, and therefore a mechanism is needed to relate the abstract tests to the refined implementation. The purpose of this paper is to provide such a method by exploring the relationship between testing and refinement. In this paper a model for test generation is used which constructs a finite state machine (FSM) from a Z specification by using a Disjunctive Normal Form (DNF) partition analysis of the state and operations. The finite state machine is then used to derive suitable test suites. The paper decribes a way of calculating an FSM for a refinement from an abstract FSM together with the information about the refinement embodied in the retrieve relation. This means that it is possible to test an implementation by generating a new concrete finite state machine from a set of abstract tests. Copyright © 1999 John Wiley & Sons, Ltd.

Diagnosis of leakage faults with I DDQ

Recently there has been renewed interest in fault detection in static CMOS circuits through I DDQ monitoring. This work shows that, in addition to fault detection, accurate fault diagnosis may be performed using a combination of current and voltage observations. The proposed system combines a simple single fault model for test generation with a more realistic multiple defect model for diagnosis, and as a result requires only minor modifications to existing stuck-at fault ATPG software. The associated hardware is sufficiently simple that on-board implementation is possible. Experimental results demonstrate the effectiveness of the method on a standard-cell ASIC.

Functional Level Primitives in Test Generation

This paper deals with the use and development of high-level (functional) primitive logic elements for use in a system which automatically generates tests for complex sequential circuits. The concept of solution sequences to test problems for primitive elements is introduced and a functional language used to describe solution sequences is presented. Functional test generation models for two basic elements, a shift register and a counter, are derived, including procedures for implication, D-drive and line justification. Primitive algorithms which generate single as well as multivector (sequences) solutions to D-drive and line justification problems are presented.

A Nine-Valued Circuit Model for Test Generation

A nine-valued circuit model for test generation is introduced which takes care of multiple and repeated effects of a fault in sequential circuits. Using this model test sequences can be determined which allow multiple and repeated effects of faults on the internal state of a sequential circuit. Thus valid test sequences are derived where other known procedures, like the D-algorithm, do not find any test although one exists.

Secondary school model automatic test generation

A review of the literature dealing with automatic test generation yields a wide variety of subject matter applications. Most decriptives, however, deal with college level projects. This paper out lines secondary school requirements that may encourage the development of appropriate test generation models. Our discussion will center on a common need for remediation at the secondary level, namely, mathematics skill building (addition, subtraction, multiplication and division). The subject matter selection is only to assure that the suggestions made are as concrete as possible. The paper will concentrate on the structural and procedural aspects of school site test generation and will not deal with the computer programming requirements. The basic model assumes remedial curriculum that will be directed as a student population of 500 students. This supposes that the entire student population is not utilizing a single test generation package. The recommendations allow for adding additional curriculum services and increasing student use. A test generating laboratory should emerge that would operate as a service bureau. This center will be detailed below. The discussion will be organized under the following headings: The discussion will be organized under the following headings: Hardware Requirements Turnaround Personnel Cost

Secondary school model automatic test generation

A review of the literature dealing with automatic test generation yields a wide variety of subject matter applications. Most decriptives, however, deal with college level projects. This paper out lines secondary school requirements that may encourage the development of appropriate test generation models. Our discussion will center on a common need for remediation at the secondary level, namely, mathematics skill building (addition, subtraction, multiplication and division). The subject matter selection is only to assure that the suggestions made are as concrete as possible. The paper will concentrate on the structural and procedural aspects of school site test generation and will not deal with the computer programming requirements. The basic model assumes remedial curriculum that will be directed as a student population of 500 students. This supposes that the entire student population is not utilizing a single test generation package. The recommendations allow for adding additional curriculum services and increasing student use. A test generating laboratory should emerge that would operate as a service bureau. This center will be detailed below. The discussion will be organized under the following headings: The discussion will be organized under the following headings: Hardware Requirements Turnaround Personnel Cost