Test Generation For Delay Faults Research Articles

LFSR-Based Test Generation for Path Delay Faults

Two challenges are combined when compressed tests are computed for path delay faults: 1) path delay faults that are important to detect are associated with long paths, and many of these faults are undetectable and 2) it may not be possible to compress a given test for a path delay fault. This paper addresses these challenges in the context of test data compression methods that are based on a linear-feedback shift-register (LFSR). The basic approach that this paper uses modifies initially random seeds for the LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in this paper also selects detectable path delay faults to address the presence of undetectable path delay faults in the set of target faults. For this purpose it uses a metric that measures the similarity between target and detected path delay faults, and attempts to compute seeds that increase the values of this metric. Experimental results are presented to demonstrate the ability of the procedure to detect path delay faults in benchmark circuits.

Path delay test generation at functional level

The path delay tests, which are used to test the maximum speed of the circuit, usually are generated at the structural level. The authors suggested the path delay fault test generation approach for non-scan sequential circuits at the functional level. The circuit is considered as a black box model having the primary inputs, primary outputs and state bits. The state bits of the model are transformed into pseudo-primary inputs and pseudo-primary outputs. The circuit is represented as the iterative logic array model, consisting of k copies of the combinational logic of the circuit. The value k defines the number of clock cycles, which has to be chosen before test generation. To assess the length of the path at the functional level they suggested a new criterion. The length of the path is assessed by the number of the sensitive paths connected to the particular input and to the particular output. The experimental results are provided for the ITC'99 benchmark circuits. The generated functional test for path delay faults can be used either on its own if there is no structural test or it can be used as a supplement to the structural test.

Fuzzy delay model based fault simulator for crosstalk delay fault test generation in asynchronous sequential circuits

In this paper, a fuzzy delay model based crosstalk delay fault simulator is proposed. As design trends move towards nanometer technologies, more number of new parameters affects the delay of the component. Fuzzy delay models are ideal for modelling the uncertainty found in the design and manufacturing steps. The fault simulator based on fuzzy delay detects unstable states, oscillations and non-confluence of settling states in asynchronous sequential circuits. The fuzzy delay model based fault simulator is used to validate the test patterns produced by Elitist Non-dominated sorting Genetic Algorithm (ENGA) based test generator, for detecting crosstalk delay faults in asynchronous sequential circuits. The multi-objective genetic algorithm, ENGA targets two objectives of maximizing fault coverage and minimizing number of transitions. Experimental results are tabulated for SIS benchmark circuits for three gate delay models, namely unit delay model, rise/fall delay model and fuzzy delay model. Experimental results indicate that test validation using fuzzy delay model is more accurate than unit delay model and rise/fall delay model.

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

Test Generation for Delay Faults on Clock Lines under Launch-on-Capture Test Environment

A Metric for Identifying Detectable Path Delay Faults

Path delay faults are used for modeling small delay defects. Due to the large numbers of paths and the large numbers of undetectable path delay faults, test generation procedures for path delay faults use path selection procedures and procedures for the identification of undetectable faults to facilitate test generation. To complement these procedures, this paper describes a metric for assessing the likelihood that a path delay fault is detectable. Path selection procedures should prefer such faults in order to yield sets of target faults that are detectable even if not all the undetectable faults are identified prior to test generation. The metric is defined such that it allows all the path delay faults with the same value of the metric (the same likelihood of being detectable) to be enumerated together. The metric is computed based on the numbers of detections of transition faults under a test set for such faults, and requires N-detection fault simulation of transition faults for a sufficiently large value of N. The results of test generation for path delay faults confirm that faults with higher values of the metric are more likely to be detectable.

Scan Flip-Flop Grouping to Compress Test Data and Compact Test Responses for Launch-on-Capture Delay Testing

Test data compression is a much more difficult problem for launch-on-capture (LOC) delay testing, because test data for LOC delay testing is much more than that of stuck-at fault testing, and LOC delay fault test generation in the two-frame circuit model can specify many more inputs. A new scan architecture is proposed to compress test stimulus data, compact test responses, and reduce test application time for LOC delay fault testing. The new scan architecture merges a number of scan flip-flops into the same group, where all scan flip-flops in the same group are assigned the same values for all test pairs. Sufficient conditions are presented for including any pair of scan flip-flops into the same group for LOC transition, non-robust path delay, and robust path delay fault testing. Test data for LOC delay testing based on the new scan architecture can be compressed significantly. Test application time can also be reduced greatly. Sufficient conditions are presented to construct a test response compactor for LOC transition, non-robust, and robust path delay fault testing. Folded scan forest and test response compactor are constructed for further test data compression. Sufficient experimental results are presented to show the effectiveness of the method.

Application of Preselection of Test Subsequences in Sequential Test Generation for Functional Delay Faults

Testing of high-performance circuits for timing failures is becoming very important. Testing of non-scan circuits using variable clock speeds requires sophisticated testers and clock control circuitry. Due to these drawbacks, delay fault testing in industry has focussed on at-speed test application in non-scan or partial scan circuits. In the paper, we introduced a new fault model, simplified functional delay fault model, and proposed to use two stages in random test generation process. In the first stage called test subsequences preselection we employed for selection of test subsequences the simplified functional delay fault model. Then in the second stage, we consider only the set of preselected test subsequences and use for fault simulation already the usual functional delay fault model. Experimental results were presented to demonstrate the effectiveness of proposed approach. Ill. 2, bibl. 10, tabl. 3 (in English; abstracts in English and Lithuanian). DOI: http://dx.doi.org/10.5755/j01.eee.118.2.1179

A SAT Based Test Generation Method for Delay Fault Testing of Macro Based Circuits

This letter addresses the problem of delay fault test generation in circuits using macros whose implementation is not known. The proposed approach uses a new signal representation that allows us to evaluate any kind of sensitization conditions (robust, non-robust, and functional) by means of Boolean differential calculus. Such an approach makes use of binary decision diagrams to support the computation of sensitization conditions for each macro along a path and of Boolean satisfiability to justify such conditions at primary inputs. Results are shown for a set of benchmarks.

Factor of Randomness in Functional Delay Fault Test Generation for Full Scan Circuits

We investigated the influence of the random generation methods to the results of the functional delay test generation. There are the three possibilities: random generation of values 0 and 1 when the probability for the appearance of each value is 50% in every bit of test pattern; random generation of large integer values, which then are split into the sequences of 0’s and 1‘s according to the rules of the conversion of the decimal number to the binary number; anti-random generation when the presence of the earlier generated patterns is taken into account. We adopted the anti-random generation for the functional delay faults. The obtained results of the investigation indicate that the random generation has the direct influence to the results of the functional delay test generation. The largest coverage of transition fault is obtained when the anti-random generation is employed.

On the Use of ZBDDs for Implicit and Compact Critical Path Delay Fault Test Generation

A new framework for generating test sets with high test efficiency for path delay faults (PDFs) is presented. The proposed method is based on a data structure that can implicitly represent all sens...

Functional test generation for delay faults in combinational circuits

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called Δ is used to control the number of funtional faults targeted and thus the number of tests generated. If Δ is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of Δ are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

Deriving logic systems for path delay test generation

We present an algorithm to derive logic systems for various classes of path delay test problems. In these logic systems, the value of a signal represents the relevant conditions that occur during a set of consecutively applied vectors. Starting from a set of basic values for valid signals at primary inputs, a state transition graph is constructed to enumerate all possible signal states relevant to path activation that are reachable by Boolean operations. These states include all incompletely specified states, composed as combinations of basic values. A distinguishability analysis then finds all state-pairs that need to be distinguished during test generation. The final step minimizes the number of states. For forward and backward implications of test generation in combinational or sequential circuits, the procedure provides optimal logic systems. We define optimality as the smallest set of logic states that provides the least possible ambiguity in implications. Thus, an optimal set of logic states will minimize the number of backtracks in test generation. A 10-valued logic described in the literature is found to be optimal for generating tests for single path delay faults. Other problems addressed in this paper include compact test generation through activation of many single path delay faults, test generation for rated-clock test application, and test generation for multiple path delay faults. The limitations and capabilities of various logic systems are illustrated by examples.

Hierarchical Delay Test Generation

Delay testing is used to detect timing errors in a digital circuit. In this paper, we report a tool called MODET for automatic test generation for path delay faults in modular combinational circuits. Our technique uses precomputed robust delay tests for individual modules to compute robust delay tests for the module-level circuit. We present a longest path theorem at the module level of abstraction which specifies the requirements for path selection during delay testing. Based on this theorem, we propose a path selection procedure in module-level circuits and report efficient algorithms for delay test generation. MODET has been tested against a number of hierarchical circuits with impressive speedups in relation to gate-level test generation.

On the number of tests to detect all path delay faults in combinational logic circuits

The problems involved in handling large numbers of path delay faults were alleviated in previous works, by developing fault simulation and test generation procedures that do not require paths to be explicitly considered. Thus, the methods developed allow the set of all path delay faults to be targeted during test generation and fault simulation. With the problems related to the number of paths removed, a new limiting factor in test generation for path delay faults is revealed, namely, the number of tests required to detect all path delay faults. In this work, the problems related to the number of tests are investigated. A procedure for computing a lower bound on the number of tests is described, and methods for synthesizing circuits with reduced lower bounds on the numbers of tests are developed. Experimental results are presented to demonstrate various aspects of the problem.

INCREDYBLE: A new search strategy for design automation problems with applications to testing

A new search strategy for design automation problems is proposed, that is directly applicable to circuits having a size parameter (e.g., operand size), and indirectly, to random-logic circuits as well. Under the proposed approach, exhaustive search for an optimal solution is performed for small versions of the target circuit, obtained by scaling-down all the size parameters of the circuit (e.g., by reducing the operand size). The optimal solutions obtained for the small circuits are studied, and analytic rules are derived to capture their common features. Using these rules, the solutions are scaled-up into a high-quality solution for the large target circuit. The method, its feasibility and limitations are described in this work. The method is applied to two problems related to testing of digital circuits, namely, test generation for stuck-at faults and test generation for path delay faults.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Test generation for path delay faults using binary decision diagrams

A new test generation technique for path delay faults in circuits employing scan/hold type flip-flops is presented. Reduced ordered binary decision diagrams (ROBDDs) are used to represent Boolean functions realized by all signals in the circuit, as well as to represent the constraints to be satisfied by the delay fault test. Two faults are considered for each path in the circuit. For each fault, a pair of constraint functions, corresponding to the two time frames that constitute a transition, is evaluated. If the constraint function in the second time frame is non-null, robust-hazard-free-test generation for the delay fault is attempted. A robust test thus generated belongs either to the class of fully transitional path (FTP) tests or to the class of single input transition (SIT) tests. If a robust test cannot be found, the existence of a non-robust test is checked. Boolean algebraic manipulation of the constraint functions guarantees that if neither robust nor non-robust tests exist, the fault is undetectable. In its present form the method is applicable to all circuits that are amenable to analysis using ROBDDs. An implementation of this technique is used to analyze delay fault testability of ISCAS '89 benchmark circuits. These results show that the algebraic technique is one to two orders of magnitude faster than previously reported methods based on branch-and-bound algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Delay-fault test generation and synthesis for testability under a standard scan design methodology

The problems of test generation and synthesis aimed at producing VLSI sequential circuits that are delay-fault testable under a standard scan design methodology are considered. Theoretical results regarding the standard scan-delay testability of finite state machines (FSMs) described at the state transition graph (STG) level are given. It is shown that a one-hot coded and optimized FSM whose STG satisfies a certain property is guaranteed to be fully gate-delay-fault testable under standard scan. This result is extended to arbitrary-length encodings, and a heuristic state assignment algorithm that results in highly gate-delay-fault testable sequential FSMs is developed. The authors also consider the problem of delay test generation for large sequential circuits and modify a PODEM-based combinational test pattern generator. The modifications involve a two-time-frame expansion of the combinational logic of the circuit and the use of backtracking heuristics tailored for the problem. A version of the scan shifting technique is also used in the test pattern generator. Test generation, flip-flop ordering, flip-flop selection and test set compaction results on large benchmark circuits are presented. >

Transitional Delay Fault Test Generation Using AGenetic Algorithm

With the continuous technological advancements in digital electronic circuit technology devices are becoming even more complex, it is essential that a high level of operational reliability is maintained which is why there is always a requirement for new and improved test methodologies. A fault condition in a digital circuit may be the result of a manufacturing problem causing physical imperfection in the device, this imperfection may be open circuit or short circuit connections, or a flaw that changes other characteristics of the device. The propagation of a gate may be affected introducing a delay defect into the circuit, often creating timing problems, which have always proved difficult to detect. This paper presents a new approach to the generation of test patterns that detect gross delay defects in combinational VLSI circuits. In O'Dare and Arslan [1] the authors presented a technique that implemented a genetic algorithm (GA) for the generation of test patterns to detect single stuck-at-faults in combinational VLSI circuits. In order to generate a test for delay faults it is necessary to create a transition in logical state at the fault site within the circuit, the only way to achieve this is by generating pairs of test patterns . The first test pattern initialises the state of all nodes within the circuit, the second test pattern is then used to force the required transition at the designated test node. The problem of test generation for delay faults is considerably more complex than that of test pattern generation for single stuck-at-faults presented in O'Dare and Arslan [1], with an increase in search space size from 2 n to 2 2n for an n input circuit. The problem is further augmented by the necessity of applying the two test patterns in a strict ordered sequence to create the required transition. The authors have therefore developed a new genetic test technique to overcome the problem, using chromosomes-pairs to represent the test patterns. The GAs primary component is a dynamically evolving Global Record Table (GRT), which is used to guide the search towards optimal test pairs in an otherwise complex solution space, producing a compact and efficient set of test pattern-pairs as the GA evolves. The experimental results presented in this paper are compared with other research results for well known combinational benchmark circuits.