Abstract
Testing of high-performance circuits for timing failures is becoming very important. Testing of non-scan circuits using variable clock speeds requires sophisticated testers and clock control circuitry. Due to these drawbacks, delay fault testing in industry has focussed on at-speed test application in non-scan or partial scan circuits. In the paper, we introduced a new fault model, simplified functional delay fault model, and proposed to use two stages in random test generation process. In the first stage called test subsequences preselection we employed for selection of test subsequences the simplified functional delay fault model. Then in the second stage, we consider only the set of preselected test subsequences and use for fault simulation already the usual functional delay fault model. Experimental results were presented to demonstrate the effectiveness of proposed approach. Ill. 2, bibl. 10, tabl. 3 (in English; abstracts in English and Lithuanian). DOI: http://dx.doi.org/10.5755/j01.eee.118.2.1179
Highlights
Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection
In the first stage we suggest to employ for selection of test subsequences the simplified functional delay fault model
We introduced a new fault model, simplified functional delay fault model, and proposed to use two stages in random test generation process
Summary
Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. A lot of work has been done in the area of delay testing for both combinational and sequential circuits. Most of the proposed delay fault test techniques for sequential circuits involve test methods utilizing scan chains or variable clock speed test application. On the other hand, testing non-scan circuits using variable clock speeds requires sophisticated testers and clock control circuitry. Due to these drawbacks, delay fault testing in industry has focussed on at-speed test application in non-scan or partial scan circuits [2]. In this paper we are going to propose an approach that allows to speed-up the test generation process.
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