Test Chip Design Research Articles

Efficient Test Chip Design via Smart Computation

Submitted to the Special Issue on Machine Learning for CAD (ML-CAD). Competitive strength in semiconductor field depends on yield. The challenges associated with designing and manufacturing of leading-edge integrated circuits (ICs) have increased that reduce yield. Test chips, especially full-flow logic test chips, are increasingly employed to investigate the complex interaction between layout features and the process that improves the total process quality before and during initial mass production. However, designing a high-quality full-flow logic test chip can be time-consuming due to the huge design space and complex process to search for optimal result. This work describes a new design flow that significantly accelerates the logic test chip design process. First, we deploy random forest classification technique to predict potential synthesis outcome for test chip design exploration. Next, a new method is described to efficiently solve the integer programming problem involved in the design process. Various experiments with industrial design have demonstrated that the proposed two methods greatly improve the design efficiency.

Variation-Aware Methods and Models for Silicon Photonic Design-for-Manufacturability

Methods for the generation and application of process variation-aware compact models for silicon photonics are presented. Three categories of process variations are considered. First, systematic variations, including die-to-die and spatial variations, are addressed with parameterized variation-aware compact models, and demonstrated for coupled resonator optical waveguide variation impact and yield analysis. Second, methods for random variation are presented, with ensemble and adjoint-based variation modeling methods. Third, particle defects are addressed with an extension to adjoint methods, enabling efficient analysis and identification of photonic component areas that are sensitive to defects. Finally, methods for extraction of variation models using variation test chip design and measurement are presented. Together, these methods are key components toward design-for-manufacturability approaches to achieve high yield and high performance in photonic integrated circuit design.

An Automated Setup for the Characterization of Time-Based Degradation Effects Including the Process Variability in 40-nm CMOS Transistors

This article reports a test chip design in commercial 40-nm process technology to characterize the level of time-based degradation in metal-oxide-semiconductor field-effect transistors (MOSFETs). The two phenomena that have been concentrated on are the bias temperature instability (BTI) and the hot carrier injection (HCI). Stress tests have been carried out on both n- and p-MOSFETs with large channel widths and shorter channel lengths, as practically observed in analog and radio frequency circuits. Reliability characterization has been extended to cover the body effect and the impact of process variations both at prestress and poststress stages. The results demonstrate that the designed test chip has been instrumental in observing the extent of degradation due to BTI and HCI. Furthermore, both the body effect and the poststress variability have been found to affect the transistor and circuit performance significantly.

An Automated Methodology for Logic Characterization Vehicle Design

Abstract A new product-like test chip developed by engineers at Carnegie Mellon University overcomes the current limitations in conventional test chip design. This article discusses the advantages of the new chip, called the CM-LCV, and presents experimental results showing how it achieves fault coverages comparable to or better than benchmarking designs.

Investigation of low temperature bonding process using indium bumps

Hybrid pixel detector modules are state of the art components of X-ray cameras in synchrotron radiation experiments. Temperature-sensitive, high-Z sensor materials like Germanium, Cadmium-Telluride, Cadmium-Zinc-Telluride and MCT-sensors require an especially low temperature bonding process. The investigation presented in this paper focuses on a low temperature compression bonding process using a ductile bump material, like indium, and a dedicated UBM surface that is able to form intermetallic compounds with this bump metal. The test samples are based on a test chip design with the size of the MEDIPIX3 readout chip and an identical number of bumps, arranged in a 256 × 256 bump matrix with 55 μm pitch in X- and Y-directions. In addition to the indium bumped test chip, two typical UBM-pad configurations were investigated on the corresponding interconnect side: a pad-defined electroplated Ni-Au-UBM and a passivation opening-defined, PVD-deposited NiV-Au pad. Daisy chain structures, 4-Point-probe resistance measurement structures and isolation test structures were implemented to characterize the influence of bonding pressure, bonding temperature and dwell time of bonding pressure on the electrical interconnection resistance. Good bonding results and a corresponding minimum electrical resistance of daisy chains and individual interconnects were achieved at temperatures of 80̂C and 100̂C. A minimum bonding pressure of 3.2 MPa was necessary to achieve reliable bonding results. Daisy chain failures occurred especially in the corner of the chips. After electrical characterization, pull tests were performed to investigate the corresponding bonding area. Pull test results showed a larger bonding area for the pad-defined, electroplated UBM pad configuration in comparison to the passivation opening defined bonding pad.

Single Event Transient and TID Study in 28 nm UTBB FDSOI Technology

Measuring single-event transient (SET) pulse widths is critical for developing proper mitigation schemes to single-event effects (SEE), especially for advanced technologies. This paper presents a test chip design implementing advanced techniques for measuring SETs implemented in a 28 nm Ultra-Thin Body and Box (UTBB) FDSOI technology. Experimental results of heavy ion and Co-60 irradiation experiments are presented. The heavy ion experiments confirm that this technology has very low SEE sensitivity. Laser test results show that pulse distortion (broadening) plays a key role when evaluating the effect of SETs. Total Ionizing Dose (TID) effects were also evaluated by measuring the Ring Oscillator (RO) frequencies and static current during heavy ion and Co-60 irradiation. Experimental results showed that the RO frequencies degraded up to 10% (heavy ion), and 40% (Co-60) after 1000 krad(Si) irradiation, but the logic in the chip functioned without error.

(Invited) SiGe and III-V Materials and Devices: New HEMT and LED Elements in 0.18-Micron CMOS Process and Design

We have established new methodologies, materials, processing, devices, and circuits for integrating III-V devices monolithically into CMOS circuits. Certain constraints were applied on this research from the start in order to converge on viable commercial strategies as the research moves closer to a path for new innovation in the semiconductor industry. Integration technology has been established for incorporating HEMTs and LEDs into CMOS integrated circuits, and both nitride-based and arsenic-phosphide-based materials are currently supported. Device models are inserted into standard foundry design libraries, allowing silicon technology efficiencies such as exploring various circuit designs before final physical silicon and fabrication-test feedback loops using test chip designs.

Silicon Odometers: Compact In Situ Aging Sensors for Robust System Design

Circuit reliability issues such as bias temperature instability, hot carrier injection, time-dependent dielectric breakdown, electromigration, and random telegraph noise have become a growing concern with technology scaling. Precise measurements of circuit degradation induced by these reliability mechanisms are a key aspect of robust design. This article reviews several unique test-chip designs that demonstrate the benefits of utilizing on-chip logic and a simple test interface to automate circuit aging experiments. This new class of compact on-chip sensors can reveal important aspects of circuit aging that would otherwise be impossible to measure, facilitate the collection of reliability data from systems deployed in the field, and eventually lead us down the path to real-time aging compensation in future processors.

Audio Telecom ADC Featuring Click-Free Gain Control Technique, Dithering Insertion, and Idle Tone Shifting

Applying pulsewidth modulation (PWM) to control the gain in audio codecs for mobile applications leads to several advantages, such as the smooth control of tuning parameters, smaller silicon area, and lower power consumption, as compared with other tuning techniques using programmable gain amplifiers and zero crossing detectors. The PWM has to be embedded into the main signal path, preferably in a closed-loop control scheme, in order to exploit its benefits. However, the insertion of dithering and offset controls in a gain setting loop poses the problem of controlling their effects in all gain conditions. This paper reports a novel technique aimed at solving the associated issues and limitations, and provides the experimental proof of the concept through the implementation of a test-chip design on silicon. In particular, this paper reports the design and experimental results of a delta-sigma analog-to-digital converter featuring a click-free gain control technique, dithering insertion, and idle-tone shifting, which has been implemented in a 40-nm complementary metal-oxide-semiconductor technology for commercial telecom audio codec applications.

High Speed Frequency-Mapping-Based Associative Memory Using Compact Multi-Bit Encoders and a Path-Selecting Scheme

A compact multi-bit encoding concept for nearest-distance search-speed improvement of scalable and reliable associative-memories utilizing a mapping operation of the distances into frequency space is reported. The distance differences are transformed into signal delays which are finally detected with a time-domain winner-take-all (WTA) circuit. Ring oscillators programmable in discrete frequency steps are used for the distance–frequency mapping. This implementation enables to decrease the effects of process-induced variations, because the step size is a constraint-free design parameter. To further improve the search reliability, frequency dividers are used to enlarge the size of the frequency steps. The multi-bit encoder achieves a substantial search-time reduction by optimizing the basic-ring oscillator delay for distance zero with a path-selecting scheme. The proposed multi-bit encoding concept has been evaluated with two test-chip designs in 180 nm complementary metal oxide semiconductor (CMOS) technology. Search-time reductions by a factor 1.7 in typical search cases and a compact circuit implementation are verified.

On-chip reliability monitors for measuring circuit degradation

Front-end-of-line reliability issues such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and Time Dependent Dielectric Breakdown (TDDB) have become more prevalent as electrical fields continue to increase in scaled devices. The rapid introduction of process improvements, such as high-k/metal gate stacks and strained silicon, has lead to new reliability issues including BTI in n-type devices. Precise measurements of the circuit degradation induced by these reliability mechanisms are a key aspect of robust design. This article will review a number of unique test chip designs pursued by circuit designers that demonstrate the benefits of utilizing on-chip logic and a simple test interface to automate circuit aging experiments. This new class of compact on-chip sensors can reveal important aspects of circuit aging that would otherwise be impossible to measure, and can lead us down the path to real-time aging compensation in future processors.

Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper describes a common framework of test chip design for logic technology development and routine process monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test structures including transistors, diodes, and resistors. To minimize the number of probe pads and maximize area utilization efficiency, a memory-addressing design scheme is implemented to select the device-under-test within the test chip. By adjusting channel width of transmission gates at the design stage, the input resistance of FC-TSA bit-cell can be parameterized and configured to satisfy the series resistance requirement of various test structures; moreover, the leakage current can be minimized with such a methodology to meet a 1-nA design specification. A 40<formula formulatype="inline"><tex Notation="TeX">$\,\times\,$</tex> </formula>20 FC-TSA has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The measurements of a set of transistor and process monitor test structures are reviewed and corresponding models discussed. </para>

ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis

Ever-increasing integrated circuit (IC) power densities and peak temperatures threaten reliability, performance, and economical cooling. To address these challenges, thermal analysis must be embedded within IC synthesis. However, this requires accurate three-dimensional chip-package heat flow analysis. This has typically been based on numerical methods that are too computationally intensive for numerous repeated applications during synthesis or design. Thermal analysis techniques must be both accurate and fast for use in IC synthesis. This paper presents a novel accurate incremental spatially and temporally adaptive chip-package thermal analysis technique called ISAC for use in IC synthesis and design. It is common for IC temperature variation to strongly depend on position and time. ISAC dynamically adapts spatial- and temporal-modeling granularities to achieve high efficiency while maintaining accuracy. Both steady-state and dynamic thermal analyses are accelerated by the proposed heterogeneous spatial-resolution adaptation and asynchronous thermal-element time-marching techniques. Each technique enables orders-of-magnitude improvement in performance while preserving accuracy when compared with other state-of-the-art adaptive steady-state and dynamic IC thermal analysis techniques. Experimental results indicate that these improvements are sufficient to make accurate dynamic and steady-state thermal analysis practical within the inner loops of IC synthesis algorithms. ISAC has been validated against reliable commercial thermal analysis tools using industrial and academic synthesis test cases and chip designs. It has been implemented as a software package suitable for integration in IC synthesis and design flows and has been publicly released

Test chip and substrate design for flip chip microelectronic package thermal measurements

PurposeThis paper's purpose is to review the design of a flip chip thermal test vehicle.Design/methodology/approachDesign requirements for different applications such as thermal characterization, assembly process optimization, and product burn‐in simulation are outlined and the design processes of different thermal test chip structures including the temperature sensor and passive heaters are described in detail. The design of fireball heater, a novel test chip structure used for evaluating the effectiveness of heat spreading of advanced thermal solutions, is also explained.FindingsDescribes the design considerations and processes of the package substrate and printed‐circuit board with special emphasis on the physical routing of the thermal test chip structures. These design processes are supported with thermal data from various finite‐element analyses carried out to evaluate the capability and limitations of thermal test vehicle design.Originality/valueThe validation and calibration procedures of a thermal test vehicle are presented in this paper.

Test Chip for the Development and Evaluation of Sensors for Measuring Stress in Metal Interconnects

The development of a new test chip is presented, containing structures for the direct measurement of stress in metallic interconnect layers associated with silicon integrated circuit technology. The rotation of the structures provides a simple method of differentiating between tensile and compressive stress. This test chip design has been used to fabricate working structures allowing the study of stresses in aluminum layers before and after sample sintering. The results are presented together with the design, fabrication, and measurement considerations that have arisen during the research. The problems experienced in removing the sacrificial layer material, necessary to release the structures, are discussed along with potential solutions. The sensor structure is suitable for fabrication within a CMOS facility and its inherent scalability makes it potentially suitable for in-line testing of state-of-the-art processes.

A crisis in oversight [Special section

This work presents the design and modeling of highspeed circuits. Modeling of high-speed circuits is usually divided into physical and behavioral representations. Physical modeling is the actual transistor level design of the high-speed chip or circuit for inter-chip communications and system level simulations. Behavioral modeling imitates the behavior of the circuit when various input/output conditions are encountered. Behavioral modeling is much faster than transistor level modeling because it does not include all the tiny details of transistors. Rather it focuses on the behavior of the circuit. But more accurate results are obtained from physical modeling because it does include all the tiny details that govern the model functionality. Physical modeling using SPICE gives accurate real life operation but requires a long simulation time. While behavioral modeling using input/output buffer information specification takes less simulation time. ASIC designers are using VHDL/Verilog to perform and test chip design on an FPGA for high volume production.

Calibration of resistance type die level temperature sensors using a single temperature technique

Thermal test chips are widely used to develop electronic packaging thermal solutions and to evaluate electronic package assembly processes. Temperature sensors are an integral component on thermal test chips. Unfortunately, each temperature sensor must be calibrated in order for them to be effective. Each calibration can take up to one hour to complete. In a time when increasing sample sizes and shorter development cycles are taxing current equipment and manpower resources, new calibration techniques must be established to keep development costs down. This paper discusses simplified calibration procedures, which can significantly reduce the time needed for temperature sensor calibration. The simplified calibration procedures utilize single-resistance measurements either at room temperature or at the anticipated test temperature. For four different test chip designs included in the current study, calibration error variations less than /spl plusmn/0.6/spl deg/C at a /spl plusmn/2/spl sigma/ confidence level are possible. The simplified calibration procedures can be applied to any resistor type temperature sensor that has a linear correlation between its electric resistive properties and temperature.

A test chip design for detecting thin-film cracking in integrated circuits : Stephen A. Gee, Martin R. Johnson and Kuan L. Chen. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18 (3), 478 (August 1995).

A test chip design for detecting thin-film cracking in integrated circuits : Stephen A. Gee, Martin R. Johnson and Kuan L. Chen. IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 18 (3), 478 (August 1995).

A test structure advisor and a coupled, library-based test structure layout and testing environment

A new test chip design environment, based on commercial tools, containing a test structure advisor and a coupled, library-based layout and testing environment has been developed that dramatically increases productivity. The test structure advisor analyzes cross sections of devices to recommend a comprehensive list of diagnostic and parametric test structures. These test structures can then be retrieved from the libraries of parameterized structures, customized, and placed in a design to rapidly generate customized test chips. Coupling of the layout and test environments enables the automatic generation of the vast majority of the parametric test software. This environment, which has been used to design test chips for a low-power/low-voltage CMOS process, a BiCMOS trench process, and a TFT process, results in an estimated tenfold increase in productivity. In addition, the redesign of five modules of Stanford's existing BiCMOS test chip, using parameterized test structures, showed an 8/spl times/ improvement in layout time alone.

Failure-analysis-based test chip design for quick yield improvement

A new design approach for a test chip developed to shorten the debugging cycle time in fabrication is described. This approach meets the requirements for failure analysis as well as parametric and statistical analyses. Particular attention is devoted to accurate defect density estimation and to locating individual defects. This is done by designing test structures suitable for both electrical measurements and failure analysis. A specially designed test chip, named YTEG, is used to evaluate 0.5-μm CMOS process technologies, and confirms the effectiveness of the chip.