Test Application Time Research Articles

An integrated DFT solution for power reduction in scan test applications by low power gating scan cell

Shrinking technologies to deep sub-microns has raised demands for high quality testing. However, excessive power during test application time serves as limiting factors for reliability in testing. To address these issues, we have proposed Integrated Low Power Gating (ILPG) Scan Cell to alleviate shift power consumption by modifying conventional master-slave scan cell. It is able to reduce power consumption inside the scan cell as well as to gate the redundant transitions propagation from scan chain to combinational part during shifting. Another low power gating scan cell for critical paths, called Critical Path Integrated Low Power Gating (CPILPG) Scan Cell, has been proposed. It speeds up the data launch operation in normal/capture mode compared to ILPG scan cell through the utilization of transmission gate. Both designs use a shorter shift path to improve critical path delay and reduce power in scan chain. This allows shift frequency increase further within maximum power budget. Hence, test application time is shortened. Our post-layout experiment results show an average power reduction of 15.12% for ILPG over conventional scan cell and up to 39.15% improvement compared to one of the most popular gating techniques. In addition, 51.42% and 43.94% improvements in CLK-to-shift delay over conventional scan cell are achieved for ILPG and CPILPG, respectively.

A Hybrid Delay Design-for-Testability for Nonseparable RTL Controller-Data Path Circuits

Path delay testing has become crucial nowadays due to the advancement in process technology. Only enhanced scan (ES) among the scan approaches provides a solution to test the path delay fault (PDF) with large area overhead and the long test application time. This paper proposes a hybrid DFT method for nonseparable controller-data path RTL circuits. A snooping system is introduced which reduces the test application time. It performs the PDF testing between the controller and data path, and for the not-Clear control lines in the data path. The proposed method shared primary inputs and outputs to overcome the extra pin. However, the area overhead for the proposed approach is slightly large for the circuit with a small bit-width data path, which reduced drastically by the increase in the bit-width. The proposed approach supports the at-speed testing and is based on the PDF model. The experimental results showed that the proposed approach reduces the area overhead and drastically reduces the test application time in comparison with the enhanced scan (ES) and hierarchical two-pattern testability (HTPT) approach. Moreover, the technique can achieve a fault coverage identical to that achieved by the ES technique.

Optimal Selective Count Compatible Runlength Encoding for SOC Test Data Compression

Test data volume amount is increased multi-fold due to the need of quality assurance of various parts of the circuit design at deep submicron level. Huge memory is required to store this enormous test data which not only increases the cost of the ATE but also the test application time. This paper presents an optimal selective count compatible run length (OSCCPRL) encoding scheme for achieving maximum compression for reduction of the test cost. OSCCPRL is a hybrid technique that amalgamates the benefits of other two techniques: 10 Coded run length (10 C) and Selective CCPRL (SCCPRL) proposed here. These techniques work on improvement of the 9 C and CCPRL techniques. In OSCCPRL, entire data is segmented in blocks and further compressed using inter block and intra block level merging techniques. SCCPRL technique is used for encoding the compatible blocks while the 10C is used to do encoding at sub block (half block length) level. In case, if no compatibility is found at block/sub block level then the unique pattern is held as such in the encoded data along with the necessary categorization bits. The decompression architecture is described and it is shown how by just the addition of few states of FSM, better test data compression can be achieved as compared to previous schemes. The simulation results performed for various ISCAS benchmarks circuits prove that the proposed OSCCPRL technique provides an average compression efficiency of around 80 %.

Access-in-turn test architecture for low-power test application

ABSTRACTThis paper presents a novel access-in-turn test architecture (AIT-TA) for testing of very large scale integrated (VLSI) designs. In the proposed scheme, each scan cell in a chain receives test data from shift-in line in turn while pushing its test response to the shift-out line. It solves the power problem of conventional scan architecture to a great extent and suppresses significantly the switching activity during shift and capture operation with acceptable hardware overhead. Thus, it can help to implement the test at much higher operation frequencies resulting shorter test application time. The proposed test approach enhances the architecture of conventional scan flip-flops and backward compatible with existing test pattern generation and simulation techniques. Experimental results obtained for some larger ISCAS’89 and ITC’99 benchmark circuits illustrate effectiveness of the proposed low-power test application scheme.

Testing Neighbouring Cell Leakage and Transition Induced Faults in DRAMs

Due to their high density, modern DRAMs are very susceptible to the interactions between adjacent cells, which in turn increases the difficulty and complexity of memory testing. In this work, we studied the interaction mechanisms among neighbouring DRAM cells in order to provide an efficient testing solution. According to the open literature, there are two mechanisms responsible for this interaction: leakage currents and cell state transitions. The frequently used Coupling Fault (CF) model is inadequate to model the combined effect of these mechanisms, while testing procedures using the Neighborhood Pattern Sensitive Fault (NPSF) model are not time efficient solutions. Towards this direction, we propose a new fault model, the Neighborhood Leakage and Transition Fault (NLTF) model for DRAMs, which effectively models the faulty behavior related to neighbouring cell interference. In addition, we developed a new test algorithm which is based on the NLTF model, and provides test application time reductions ranging from 68 to 87 percent with respect to the existing testing algorithms in the literature that are capable to cover the NLTFs. Finally, the proposed algorithm is extended to cover NLTFs in word-oriented DRAMs.

Test Data Compression for System-on-chip using Flexible Runs-aware PRL Coding

This paper presents a flexible runs-aware PRL coding method whose coding algorithm is simple and easy to implement. The internal 2-n-PRL coding iteratively codes 2n runs of compatible or inversely compatible patterns inside a single segment. The external N-PRL coding iteratively codes flexible runs of compatible or inversely compatible segments across multiple segments. The decoder architecture is concise. The benchmark circuits verify the flexible runs-aware PRL coding method, the experimental results show it obtains higher compression ratio and shorter test application time.

Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system‐on‐chip

Signature-based authentication is used often to authenticate hardware intellectual property (IP) when it is reused on a plug-and-play system-on-chip. A signature embedded in the functional/test component of a hardware IP can easily be verified as it can be generated and observed as functional/scan output of the hardware IP for a certain input key vector. An existing scan-based approach for embedding signature inserts signature through reordering of scan cells in a single scan (SS) chain. However, it is not applicable to the recent reconfigurable scan architectures having reduced test application time. We propose a scheme for embedding two distinct signatures separately in a reconfigurable scan architecture and verifying those without conflict from the packaged chip by using two distinct test modes of the reconfigurable architecture: namely, scan tree mode and SS mode. The two signatures may include one from logic IP source and the other from physical IP source. The overhead in both routing and power has been minimised in our scheme. Experimental results on design overhead and robustness for ISCAS89 benchmarks are very encouraging.

Applications of Mixed-Signal Technology in Digital Testing

For reducing the test application time and required tester pins per device, we propose the use of multi-valued logic (MVL) signals, which increases data rate between the device under test (DUT) and automatic test equipment (ATE). An MVL signal sends multiple bits of information per clock cycle on a physical channel. Conversion of signals between binary and MVL is accomplished by digital to analog and analog to digital converters available in the mixed-signal technology. To support MVL test application and avoid reliability issues, we add necessary modifications on ATE and DUT sides. Theoretical calculation and a prototype experiment demonstrate significant data rate increase. We integrate the proposed MVL technique into test methodologies involving reduced pin-count test (RPCT) for multi-core system-on-chip (SoC) and test compression. An actual automatic test equipment (ATE) based test of a DUT shows notable reduction in test application time with MVL test application.

Physical Aware Approaches for Speeding up Scan Shift Operation in SoC

System-on-Chip (SoC) designs have a number of flipflops and it requires a long scan test application time. Scan shift operation takes a significant portion of scan test application time. This paper presents physical aware approaches for speeding up a scan shift operation in SoC. To improve scan shift operation speed, we propose a layout aware flip-flop insertion and scan shift test aware physical implementation procedure. The proposed method effectively improves scan shift speed. The static timing analysis results from state-of-the-art SoC designs show that the scan shift operation is 4.1 times faster than the conventional method. The faster scan shift operation helps to shorten the scan test application time, and reduces test cost.

LFSR-Based Generation of Multicycle Tests

This paper describes a procedure for computing a multicycle test set whose scan-in states are compressed into seeds for a linear-feedback shift register, and whose primary input vectors are held constant during the application of a multicycle test. The goal of computing multicycle tests is to provide test compaction that reduces both the test application time and the test data volume. To avoid sequential test generation, the procedure uses a single-cycle test set to guide the computation of multicycle tests. The procedure optimizes every multicycle test, and increases the number of faults it detects, by adjusting its seed, primary input vector, and number of functional clock cycles. Optimizing the seed instead of the scan-in state avoids the computation of scan-in states for which seeds do not exist. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure.

DFT Architecture With Power-Distribution-Network Consideration for Delay-Based Power Gating Test

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality (TQ) loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers tradeoff flexibility between test application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase TQ when considering systematic variations. Through SPICE simulations, we show complete recovery of the TQ lost due to PDNs. The proposed method is robust, sustaining 80.3%–98.6% of the achieved TQ under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on TQ and offers a unified test solution for both ring and grid power gating styles.

Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction

Scan tree architecture has been proposed to reduce the test application time of full scan chain by placing multiple scan cells in parallel. Most existing techniques rely on non-compact test pattern sets to construct the scan tree. However, they produce inefficient scan tree when highly compact test sets with few don't cares are used. In this paper, the depth of the scan tree based on approximate compatibility relation for completely specified test data set is analyzed probabilistically by modeling its construction as a vertex coloring problem. The upper bound of edges-per-vertex is computed and demonstrated to be a prime factor that limits the efficiency of scan tree construction based on both compatible and approximately compatible test data between two flip-flops. Inverse compatibility and aggressive approximate compatibility are then proposed to increase the edges-per-vertex for vertex coloring. The Q′-SD connection between two adjacent scan cells is exploited to implement the inverse compatibility with no cost or timing impact. To maintain the fault coverage, the missing faults under the tree scan mode can be detected by switching the same base architecture into the linear scan mode with negligible hardware overhead as shown by the experimental results on ISCAS89, ISCAS99 and LGSynth93 benchmark circuits. On average, the scan tree generated by our method reduces the test time of the full scan chain by 56.65 percent, and that of the scan tree designed by the approximate compatibility method by 39.18 percent under the same compact test sets.

FPGA Implementation of Self-Testing Logic Gates, Adders and Multipliers

This study presents self-checking designs for arithmetic and logic circuits using Field Programmable Gate Array (FPGA) design. At present, we are implementing every circuit using VLSI technology because of its excellent features like low power, less area, wide implementation. Since finding error manually is a tedious process, self-checking method would be most wanted. Self-checking circuits are preferable to Automatic Testing Equipment (ATE) because they demand less hardware, low cost and takes very less test application time. The replica construction and pattern recognition are the two methods presented for self-checking logic gates. Self-checking single-bit full adder, 4-bit adder and 2-bit multiplier circuits are implemented and tested on EP2C20F484C7 Altera Cyclone-II FPGA device using Very High-Speed Integrated Circuits Hardware Description Language (VHDL) script. The test data input samples are applied through input switches and the Error/No Error results are obtained on the 7-segment display device. This study discuss in detail about basic self-checking methods with a experimental way. If the complexity of the circuit increases, the components used and the number of connections between the components increases. As a result, the probability of error occurrence increases for complex designs. But this error occurrence can be avoided to the maximum by using self-checking circuits at different build stages in the complex circuit model. The reliability of any system becomes very important especially in the area of applications such space technology, medical image analysis, military communications, etc.

A Power Efficient Test Data Compression Method on Count Compatible PRL Coding

A realistic test sets compression method is proposed to effectively reduce test data volume and test application time during system-on-chip (SoC) scan testing, count compatible pattern run-length (CCPRL) coding method counts the consecutive number of the equal to or contrary to the retained patterns, it modifies the compatible code of variable-length pattern run-length (VPRL) coding rules and adds a count code block to replace original rules for increasing compression ratio. Next, the decoder architecture and the state diagram of finite state machine (FSM) are designed. In addition, the power model of test vectors is analyzed, and the power consumption of scanned-in vectors is roughly evaluated. The six largest ISCAS'89 benchmark circuits verify the proposed coding method has a shorter codeword. Experiment results shows that all compression ratios have been increased as much as possible, test data decompression is lossless, less test application time is consumed, yet the peak power and average power consumption of scanned-in test vector needs to be further improved for modern circuit scan testing.

IMPACT OF FUNCTIONAL DELAY TEST COMPACTION ON TRANSITION FAULT COVERAGE

Compact test sets are very important for degrading the cost of testing the very large-scale integrated circuits by reducing the test application time. Small test sets also lessen the test storage requirements. The only way to compact functional delay fault tests is to enable multi-input transitions in test pattern pairs. The goal of the paper is to analyze the impact of multi-input transitions in test pattern pairs on the transition fault coverage. The performed research shows that the quality of functional delay fault MIT tests in regard of detection of structural level transition faults is higher than that of functional delay fault SIT tests. However, the application of MIT tests instead of SIT tests for transition fault detection may as well decrease the transition fault coverage. The reasons are in changed conditions of signal propagation from circuit input to circuit output. The possible ways to increase the quality of MIT tests are proposed in this work as well.

A Generalized Definition of Unnecessary Test Vectors in Functional Test Sequences

A class of static test compaction procedures for functional test sequences is based on the omission of unnecessary test vectors. According to the definition used by these procedures, a test vector is unnecessary if all the target faults continue to be detected after it is omitted. This article introduces a more general definition of unnecessary test vectors that allows additional ones to be omitted. According to this definition, a test vector is unnecessary if every target fault can be detected by a sequence that is obtained after omitting the vector, and possibly other vectors. The article develops a procedure for omitting test vectors based on this definition and discusses its effects on the storage requirements and test application time.

A Novel Massively Parallel Testing Method Using Multi-Root for High Reliability

Wafer testing (wafer sort) is used in the semiconductor industry to reduce test costs. High parallelism is important to reduce test application time. However, increasing parallelism is becoming more difficult because the elements that drive test costs are increases in the pin count of the system on chip (SOC), and required automated test equipment (ATE) channels. While the need for parallelism has been growing, a reliability problem in which fault distribution causes good devices under test (DUT) to be improperly tested is becoming a concern. To achieve high parallelism and reliability, we propose a novel, massively parallel testing method using multi-root. In addition, we develop a test setup for setting the root-DUT location and the path of all DUTs. Using the proposed wafer testing method, test data can be transferred between the ATE and dies using multi-roots. The experimental results using ITC 02 SOC benchmarks show that the proposed method can reduce test costs up to 90%, and achieve nearly 94.84% test reliability without affecting yield.

A Power Efficient BIST TPG Method on Don’t Care Bit Based 2-D Adjusting and Hamming Distance Based 2-D Reordering

A power efficient BIST TPG method is proposed to reduce test power dissipation during scan testing. Before the test patterns are injected into scan chain, the test set adopts a series of preprocessed strategies including don't care bit based 2-D adjusting, Hamming Distance based 2-D reordering and test cube matrix based two transpose, all steps will be orderly executed in interspersed way. The six largest ISCAS'89 benchmark circuits verify the proposed method. Experimental results show that the switching activities are effectively reduced when the test set is loaded for on-chip scan testing. ASDFR with MT-filling scheme ensures high compression ratio, the scan-in test power dissipation is further decreased by don't care bit based 2-D adjusting and Hamming Distance 2-D reordering. In addition, the BIST TPG method with less test application time and smaller algorithm complexity can be widely applied to actual chip design without adding extra decoder area overhead.

A Technique for Testing Network Connections in Parallel with Mesh Topology

Abstract. In this paper, we connections between switches in the mesh network topology in a parallel way we've tested. The method is based on a built-in self-test, the use of buffers FIFO Each of the switches, test all connections between switches is done in parallel, not only test application time, but the area overhead of the network is reduced.

A hybrid method for segmented test data compression

This paper presents a hybrid compression method for scan-based testing. Four distinctive compression techniques, i.e. frequency-directed run-length codes (FDR), inverting FDR, option coding technique, and optimal selective Huffman code are selected for compression of a given test set. To lift the potential compression limit, we properly cluster scan cells to classify test data as four subsets respectively, by majorities of 0s, 1s, Xs, and a roughly equal number of 0s and 1s to match specific properties of the compression techniques. Segments are then, respectively, compressed by the technique that fits best to achieve an overall good compression effect. Experimental results for the larger ISCAS’89 benchmark circuits show that up to 69.9% of average compression ratio and significant test application time reduction can be achieved.