Tesla V100 GPU Research Articles

GPU accelerated Staggered Update Procedure (SUP)

The advancement in programmable capability of graphics hardware has paved new opportunities in the domain of high performance computing (HPC). The computational fluid dynamics (CFD) community, being a significant user of HPC, has started exploiting the inherent data parallelism in the numerical solvers to be able to make efficient use of these many-core, high throughput accelerator based processors. In the present work, we examine the process of accelerating our CPU based Staggered Update Procedure (SUP) solver, i.e., a higher order accurate cell-centred finite volume solver by off-loading the computationally most expensive region of the code pertaining to the explicit residual computation. We have adopted OpenACC, a directive based programming model to expose parallelism in the code. The framework evolved for GPU porting in the context of SUP is also of value to those intending to port their CFD solvers based on classical finite volume methodology. The performance analysis is conducted using scalar convection–diffusion equations in both two- and three-dimensions. The findings demonstrate a speedup factor of 9 (in case of 2D) and 28 (in case of 3D) when considering the explicit residual alone, achieved with a single NVIDIA Tesla V100 GPU card. In addition, we could establish superior algorithmic scalability by the way of recovering near perfect serial performance, on the heterogeneous CPU+GPU architecture. Further, overall code acceleration can be achieved by porting other parts of the solver on GPU.

Codebase release 1.1 for GAPS

The Single Instruction, Multiple Thread (SIMT) paradigm of GPU programming does not support the branching nature of a parton shower algorithm by definition. However, modern GPUs are designed to schedule threads with diverging processes independently, allowing them to handle such branches. With regular thread synchronisation and careful treatment of the individual steps, one can simulate a parton shower on a GPU. We present a Sudakov veto algorithm designed to simulate parton branching on multiple events in parallel. We also release a CUDA C++ program that generates matrix elements, showers partons and computes jet rates and event shapes for LEP at 91.2 GeV on a GPU. To benchmark its performance, we also provide a near-identical C++ program designed to simulate events serially on a CPU. While the consequences of branching are not absent, we demonstrate that a GPU can provide the throughput of a many-core CPU. As an example, we show that the time taken to shower 10^6106 events on one NVIDIA TESLA V100 GPU is equivalent to that of 295 Intel Xeon E5-2620 CPU cores.

An algorithm to parallelise parton showers on a GPU

The Single Instruction, Multiple Thread (SIMT) paradigm of GPU programming does not support the branching nature of a parton shower algorithm by definition. However, modern GPUs are designed to schedule threads with diverging processes independently, allowing them to handle such branches. With regular thread synchronisation and careful treatment of the individual steps, one can simulate a parton shower on a GPU. We present a Sudakov veto algorithm designed to simulate parton branching on multiple events in parallel. We also release a CUDA C++ program that generates matrix elements, showers partons and computes jet rates and event shapes for LEP at 91.2 GeV on a GPU. To benchmark its performance, we also provide a near-identical C++ program designed to simulate events serially on a CPU. While the consequences of branching are not absent, we demonstrate that a GPU can provide the throughput of a many-core CPU. As an example, we show that the time taken to shower 10^6106 events on one NVIDIA TESLA V100 GPU is equivalent to that of 295 Intel Xeon E5-2620 CPU cores.

Automated reporting of cervical biopsies using artificial intelligence.

When detected at an early stage, the 5-year survival rate for people with invasive cervical cancer is 92%. Being aware of signs and symptoms of cervical cancer and early detection greatly improve the chances of successful treatment. We have developed an Artificial Intelligence (AI) algorithm, trained and evaluated on cervical biopsies for automated reporting of digital diagnostics. The aim is to increase overall efficiency of pathological diagnosis and to have the performance tuned to high sensitivity for malignant cases. Having a tool for triage/identifying cancer and high grade lesions may potentially reduce reporting time by identifying areas of interest in a slide for the pathologist and therefore improving efficiency. We trained and validated our algorithm on 1738 cervical WSIs with one WSI per patient. On the independent test set of 811 WSIs, we achieved 93.4% malignant sensitivity for classifying slides. Recognising a WSI, with our algorithm, takes approximately 1.5 minutes on the NVIDIA Tesla V100 GPU. Whole slide images of different formats (TIFF, iSyntax, and CZI) can be processed using this code, and it is easily extendable to other formats.

IDNet: Information Decomposition Network for Fast Panoptic Segmentation.

Traditional CNN-based pipelines for panoptic segmentation decompose the task into two subtasks, i.e., instance segmentation and semantic segmentation. In this way, they extract information with multiple branches, perform two subtasks separately and finally fuse the results. However, excessive feature extraction and complicated processes make them time-consuming. We propose IDNet to decompose panoptic segmentation at information level. IDNet only extracts two kinds of information and directly completes panoptic segmentation task, saving the efforts to extract extra information and to fuse subtasks. By decomposing panoptic segmentation into category information and location information and recomposing them with a serial pipeline, the process for panoptic segmentation is simplified greatly and unified with regard to stuff and things. We also adopt two correction losses specially designed for our serial pipeline, guaranteeing the overall predicting performance. As a result, IDNet strikes a better balance between effectiveness and efficiency, achieving the fastest inference speed of 24.2 FPS at a resolution of 800×1333 on a Tesla V100 GPU and a PQ of 43.8, which is comparable in one-stage CNN-based methods. The code will be released at https://github.com/AronLin/IDNet.

CHIP-KNNv2: AConfigurable andHigh-PerformanceK-NearestNeighbors Accelerator on HBM-based FPGAs

The k-nearest neighbors (KNN) algorithm is an essential algorithm in many applications, such as similarity search, image classification, and database query. With the rapid growth in the dataset size and the feature dimension of each data point, processing KNN becomes more compute and memory hungry. Most prior studies focus on accelerating the computation of KNN using the abundant parallel resource on FPGAs. However, they often overlook the memory access optimizations on FPGA platforms and only achieve a marginal speedup over a multi-thread CPU implementation for large datasets.In this article, we design and implement CHIP-KNN: an HLS-based, configurable, and high-performance KNN accelerator. CHIP-KNN optimizes the off-chip memory access on modern HBM-based FPGAs such as the AMD/Xilinx Alveo U280 FPGA board. CHIP-KNN is configurable for all essential parameters used in the algorithm, including the size of the search dataset, the feature dimension and data type representation of each data point, the distance metric, and the number of nearest neighbors - K. In terms of design architecture, we explore and discuss the tradeoffs between two design versions: CHIP-KNNv1 (Ping-Pong buffer based) and CHIP-KNNv2 (streaming-based). Moreover, we investigate the routing congestion issue in our accelerator design, implement hierarchical structures to shorten critical paths, and integrate an open-source floorplanning optimization tool called TAPA/AutoBridge to eliminate the place-and-route issues. To explore the design space and balance the computation and memory access performance, we also build an analytical performance model. Given a user configuration of the KNN parameters, our tool can automatically generate TAPA HLS C code for the optimal accelerator design and the corresponding host code, on the HBM-based FPGA platform.Our experimental results on the Alveo U280 show that, compared to a 48-thread CPU implementation, CHIP-KNNv2 achieves a geomean performance speedup of 15×, with a maximum speedup of 45×. Additionally, we show that CHIP-KNNv2 achieves up to 2.1× performance speedup over CHIP-KNNv1 while increasing configurability. Compared with the state-of-the-art Facebook AI Similarity Search (FAISS) [23] GPU implementation running on a Nvidia Tesla V100 GPU, CHIP-KNNv2 achieves an average latency reduction of 30.6× while requiring 34.3% of GPU power consumption.

Accelerating Graph Convolutional Networks Through a PIM-Accelerated Approach

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Graph convolutional networks</i> (GCNs) are promising to enable machine learning on graph data. GCNs show potential vertex-level and intra-vertex parallelism for GPU acceleration, but their irregular memory accesses arising in aggregation operations and the inherent sparsity for vertex features of graphs cause inefficiencies on the GPU. In this paper, we present gPIM, which aims to accelerate GCNs inference through a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">processing-in-memory</i> (PIM) enabled architecture. gPIM is expected to perform compute-intensive combination on the GPU while aggregation and memory-bound combination are offloaded to the PIM-featured <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">hybrid memory cubes</i> (HMCs). To maximize the efficiency of such GPU-HMC architecture, gPIM is novel with two key designs: 1) A GCN-induced graph partitioning that minimizes communication overheads between cubes, 2) A programmer-transparent performance estimation mechanism that predicts the performance bound of operations accurately for workload offloading. Experimental results show that gPIM significantly outperforms Intel Xeon E5-2680v3 CPU (8,979.52×), NVIDIA Tesla V100 GPU (96.01×), and a state-of-the-art GCN accelerator AWB-GCN (4.18×).

GPU implementation of the discrete unified gas kinetic scheme for low-speed isothermal flows

In this paper, two GPU parallel algorithms are proposed for the discrete unified gas kinetic scheme (DUGKS) for simulating low-speed isothermal flows. Algorithm-I uses a two-level fine-grain technique for the parallelization of physical spatial space, while Algorithm-II adopts this technique for both physical spatial and particle velocity spaces. To evaluate the performance of the proposed algorithms, several typical benchmark problems are simulated, including the two-dimensional (2D) and three-dimensional (3D) lid-driven cavity flows, the micro channel and cavity flows. Numerical results show that our GPU algorithms can achieve satisfactory computational efficiency. For Algorithm-I, the speedup can reach 250 and 338 on a Tesla V100 GPU card for the 2D and 3D continuum cavity flows, respectively, and a hundredfold acceleration can be obtained for the rarefied cases. While for Algorithm-II, a speedup of about 70 can be attained for rarefied cases. However, it is not applied to continuum problems that only require a small number of velocity points. Moreover, comparisons between the two GPU algorithms are also conducted for the rarefied flows with various grid meshes and velocity directions. The results show that Algorithm-I performs better when physical mesh size is large, while Algorithm-II can provide higher efficiency for a coarser mesh with medium number of discrete velocities. Special attention is also paid to comparisons between Algorithm-I and MPI parallelization with 128 CPU cores based on physical space discretization approach, and it is found that Algorithm-I has a clear advantage on V100 GPU when dealing with sparse physical grids in both continuum and rarefied cases.

Layered mixed-precision training: A new training method for large-scale AI models

How to efficiently and quickly train large-scale AI models has become a hot topic in recent deep learning. Mixed-precision training is an effective technique to speed up training and reduce memory usage. At present, the automatic mixed-precision training method mainly uses half-precision (FP16) for the matrix operations of forward and backward propagation of the entire model and accumulates the FP32 weight copies to avoid rounding errors. However, this method is not optimized for each layer individually, leading to poor convergence in large-scale model training because different layers have different data patterns. Therefore, this paper proposes a layered mixed-precision training method, which can flexibly adjust training precisions according to the contribution of each layer to the training effect. Applying the layered mixed-precision method, the ResNet model achieves a 1.9× speedup compared to the baseline and a lower percentage of accuracy loss. In addition, this paper combines the layered mixed-precision method with distributed training strategies. Combining data parallel training, the model achieves a 3.74× speedup by using four Tesla V100 GPUs. The applicability of the layered mixed-precision method in model parallel training has been verified. Combining optimized pipeline parallel training, the model achieves a 3.26× speedup by using three Tesla V100 GPUs.

MPU: Memory-centric SIMT Processor via In-DRAM Near-bank Computing

With the growing number of data-intensive workloads, GPU, which is the state-of-the-art single-instruction-multiple-thread (SIMT) processor, is hindered by the memory bandwidth wall. To alleviate this bottleneck, previously proposed 3D-stacking near-bank computing accelerators benefit from abundant bank-internal bandwidth by bringing computations closer to the DRAM banks. However, these accelerators are specialized for certain application domains with simple architecture data paths and customized software mapping schemes. For general-purpose scenarios, lightweight hardware designs for diverse data paths, architectural supports for the SIMT programming model, and end-to-end software optimizations remain challenging.To address these issues, we propose Memory-centric Processing Unit (MPU), the first SIMT processor based on 3D-stacking near-bank computing architecture. First, to realize diverse data paths with small overheads, MPU adopts a hybrid pipeline with the capability of offloading instructions to near-bank compute-logic. Second, we explore two architectural supports for the SIMT programming model, including a near-bank shared memory design and a multiple activated row-buffers enhancement. Third, we present an end-to-end compilation flow for MPU to support CUDA programs. To fully utilize MPU’s hybrid pipeline, we develop a backend optimization for the instruction offloading decision. The evaluation results of MPU demonstrate 3.46× speedup and 2.57× energy reduction compared with an NVIDIA Tesla V100 GPU on a set of representative data-intensive workloads.

Progressively refined deep joint registration segmentation (ProRSeg) of gastrointestinal organs at risk: Application to MRI and cone-beam CT.

Adaptive radiation treatment (ART) for locally advanced pancreatic cancer (LAPC) requires consistently accurate segmentation of the extremely mobile gastrointestinal (GI) organs at risk (OAR) including the stomach, duodenum, large and small bowel. Also, due to lack of sufficiently accurate and fast deformable image registration (DIR), accumulated dose to the GI OARs is currently only approximated, further limiting the ability to more precisely adapt treatments. Develop a 3-D Progressively refined joint Registration-Segmentation (ProRSeg) deep network to deformably align and segment treatment fraction magnetic resonance images (MRI)s, then evaluate segmentation accuracy, registration consistency, and feasibility for OAR doseaccumulation. ProRSeg was trained using five-fold cross-validation with 110 T2-weighted MRI acquired at five treatment fractions from 10 different patients, taking care that same patient scans were not placed in training and testing folds. Segmentation accuracy was measured using Dice similarity coefficient (DSC) and Hausdorff distance at 95th percentile (HD95). Registration consistency was measured using coefficient of variation (CV) in displacement of OARs. Statistical comparison to other deep learning and iterative registration methods were done using the Kruskal-Wallis test, followed by pair-wise comparisons with Bonferroni correction applied for multiple testing. Ablation tests and accuracy comparisons against multiple methods were done. Finally, applicability of ProRSeg to segment cone-beam CT (CBCT) scans was evaluated on a publicly available dataset of 80 scans using five-foldcross-validation. ProRSeg processed 3D volumes (128 × 192 × 128) in 3 s on a NVIDIA Tesla V100 GPU. It's segmentations were significantly more accurate ( ) than compared methods, achieving a DSC of 0.94 ±0.02 for liver, 0.88±0.04 for large bowel, 0.78±0.03 for small bowel and 0.82±0.04 for stomach-duodenum from MRI. ProRSeg achieved a DSC of 0.72±0.01 for small bowel and 0.76±0.03 for stomach-duodenum from public CBCT dataset. ProRSeg registrations resulted in the lowest CV in displacement (stomach-duodenum : 0.75%, : 0.73%, and : 0.81%; small bowel : 0.80%, : 0.80%, and : 0.68%; large bowel : 0.71%, : 0.81%, and : 0.75%). ProRSeg based dose accumulation accounting for intra-fraction (pre-treatment to post-treatment MRI scan) and inter-fraction motion showed that the organ dose constraints were violated in four patients for stomach-duodenum and for three patients for small bowel. Study limitations include lack of independent testing and ground truth phantom datasets to measure dose accumulationaccuracy. ProRSeg produced more accurate and consistent GI OARs segmentation and DIR of MRI and CBCTs compared to multiple methods. Preliminary results indicates feasibility for OAR dose accumulation usingProRSeg.

Efficient parallelization for 3D-3V sparse grid Particle-In-Cell: Single GPU architectures

In the present paper, an efficient General Purpose Graphical Processing Unit (GPGPU)-based implementation of sparse grid Particle-In-Cell (PIC) methods is proposed. The parallelization, implementing novel strategies specific to sparse-PIC methods and tailored to GPU architectures, provides speed-ups1 as large as 100 on a single Tesla V100 GPU, with respect to sequential Computing Processing unit (CPU) execution; and a four order of magnitude reduction of the computational time in comparison with a standard PIC sequential CPU simulation. In addition, the simple implementation of the parallelization with the OpenACC framework offers portability to a large class of accelerators.

Heterogeneous acceleration algorithms for shallow cumulus convection scheme over GPU clusters

The physical process of atmospheric cumulus convection plays a crucial role in climate modeling, and its complex computational process severely restricts the development of high-resolution climate models. Accelerating the cumulus convective process calculation in climate models is a significant challenge. Traditional CPU-accelerated computing is increasingly unable to meet the growing demand for computing resources from high-resolution climate models. Therefore, developing an efficient cumulus convection scheme is quite valuable and necessary. In response to this demand, this paper selects the University of Washington shallow cumulus (UWshcu) model as the research object and proposes its parallel algorithms suitable for large-scale, heterogeneous, high-performance computing systems: (1) the single GPU acceleration algorithm based on CUDA C, namely GPU-UWshcu; (2) the multi-NVIDIA GPUs acceleration algorithm based on the MPI+CUDA hybrid programming model, namely CGPUs-UWshcu; (3) the multi-AMD GPUs acceleration algorithm based on MPI+HIP, namely HGPUs-UWshcu; (4) the multiple CPUs+GPUs acceleration algorithm based on MPI+OpenMP+HIP, namely MOH-UWshcu. Experimental results show that these algorithms are efficient and have good scalability. GPU-UWshcu achieves a speedup of 74.39× on a single Tesla V100 GPU compared with the serial algorithm running on an Intel Xeon E5-2680 v2 CPU core, and CGPUs-UWshcu achieves a 151.22× speedup on 16 Tesla V100 GPUs compared to a single Intel Xeon E5-2630 v4 CPU (10 cores). On the ORISE supercomputer, HGPUs-UWshcu uses 1024 AMD GPUs to achieve a 664.65× speedup compared to a single CPU (32 cores), with a parallel efficiency of 68.91% compared to using 32 GPUs. Compared to using the same number of CPU cores, MOH-UWshcu uses 8192 CPU cores+1024 GPUs to achieve a speedup of 4.98×, with 55.22 TFLOPS in double precision.

Acceleration of the data-parallel lower-upper relaxation time-integration method on GPU for an unstructured CFD solver

The acceleration of CFD solvers on GPUs allows for large speedups, which enable more complex and detailed simulations. However, not all numerical methods can be efficiently executed in a massively parallel fashion. The Runge–Kutta (RK) and Lower-Upper Symmetric Gauss–Seidel (LU-SGS) time-integration methods are widely used on GPUs and multicore CPUs, respectively; however, the RK method suffers from low convergence speed, while the LU-SGS method is not adapted to a many-core environment. In this paper, we propose to accelerate the matrix-free version of the Data-Parallel Lower-Upper Relaxation (DP-LUR) time-integration method on the unstructured solver FaSTAR, developed by JAXA. The DP-LUR method outperformed the RK and LU-SGS methods on an NVIDIA Tesla V100 GPU when tested on the ONERA M6 and NASA CRM geometries, and reached up to 3.83% of the performance peak of one device.

High-speed implementation of rainbow table method on heterogeneous multi-device architecture

Heterogeneous multi-device architecture has been widely used to solve computationally intensive problems. This paper proposes a high-speed implementation of the rainbow table method based on perfect table in a CPU and GPU based computing system. Firstly, we introduce a memory optimization method to reduce the size of the rainbow table. Then, we show how to parallelize each phase of the rainbow table method using as many devices as possible to achieve optimal performance. We conduct a series of comparative experiments with different cryptographic hash functions on a heterogeneous architecture powered by an Intel Xeon 8176M CPU and two NVIDIA Tesla V100 GPUs. Compared with the state-of-the-art third-party tools, Cryptohaze and RainbowCrack, our implementation can reduce the size of the rainbow table by at least 57.1%, and we can achieve significant speedup: 2.03× and 131.3× speedup in the precomputation phase (table generation); 1.97× and 1.44× speedup in the online phase (searching the pre-image of a hash value), respectively.

Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks

This work introduces Remarn, a reconfigurable multi-threaded multi-core accelerator supporting both spatial and temporal co-execution of Recurrent Neural Network (RNN) inferences. It increases processing capabilities and quality of service of cloud-based neural processing units (NPUs) by improving their hardware utilization and by reducing design latency, with two innovations. First, a custom coarse-grained multi-threaded RNN/Long Short-Term Memory (LSTM) hardware architecture, switching tasks among threads when RNN computational engines meet data hazards. Second, the partitioning of this hardware architecture into multiple full-fledged sub-accelerator cores, enabling spatially co-execution of multiple RNN/LSTM inferences. These innovations improve the exploitation of the available parallelism to increase runtime hardware utilization and boost design throughput. Evaluation results show that a dual-threaded quad-core Remarn NPU achieves 2.91 times higher performance while only occupying 5.0% more area than a single-threaded one on a Stratix 10 FPGA. When compared with a Tesla V100 GPU implementation, our design achieves 6.5 times better performance and 15.6 times higher power efficiency, showing that our approach contributes to high performance and energy-efficient FPGA-based multi-RNN inference designs for datacenters.

Segment Linking: A Highly Parallelizable Track Reconstruction Algorithm for HL-LHC

The High Luminosity upgrade of the Large Hadron Collider (HL-LHC) will produce particle collisions with up to 200 simultaneous proton-proton interactions. These unprecedented conditions will create a combinatorial complexity for charged-particle track reconstruction that demands a computational cost that is expected to surpass the projected computing budget using conventional CPUs. Motivated by this and taking into account the prevalence of heterogeneous computing in cutting-edge High Performance Computing centers, we propose an efficient, fast and highly parallelizable bottom-up approach to track reconstruction for the HL-LHC, along with an associated implementation on GPUs, in the context of the Phase 2 CMS outer tracker. Our algorithm, called Segment Linking (or Line Segment Tracking), takes advantage of localized track stub creation, combining individual stubs to progressively form higher level objects that are subject to kinematical and geometrical requirements compatible with genuine physics tracks. The local nature of the algorithm makes it ideal for parallelization under the Single Instruction, Multiple Data paradigm, as hundreds of objects can be built simultaneously. The computing and physics performance of the algorithm has been tested on an NVIDIA Tesla V100 GPU, already yielding efficiency and timing measurements that are on par with the latest, multi-CPU versions of existing CMS tracking algorithms.

Real-time masked face classification and head pose estimation for RGB facial image via knowledge distillation

Recently, human head pose estimation and masked face classification are two essential problems in facial analysis. It is necessary to design a compact model to resolve both tasks in order to reduce the computational cost when deploying face recognition-based applications such as camera surveillance systems, AI cameras while maintaining accuracy. In this work, we proposed a lightweight multi-task model called MHPNet that simultaneously addresses both head pose estimation and masked face classification problems. Because of the lack of datasets with available labels for both tasks, we first train teacher models independently on two labelled datasets 300 W-LPA and MAFA to extract the head pose and masked soft label. After that, we design architecture with ResNet18 backbone and two branches for two tasks and train our proposed model with the predictions of teacher models on joint datasets via the knowledge distillation process. To evaluate the effectiveness of our model, we use AFLW2000 and BIWI datasets for head pose estimation problems and MAFA datasets for masked face classification problems. Experiment results show that our proposed model significantly improves the accuracy compared to the state-of-the-art head pose estimation methods and achieves remarkable performance on masked face dataset. Furthermore, our model has the real-time speed of ∼400 FPS when inferring on a Tesla V100 GPU device. Source codes and datasets are available at https://github.com/chientv99/maskpose.

DynamAP: Architectural Support for Dynamic Graph Traversal on the Automata Processor

Dynamic graph traversals (DGTs) currently are widely used in many important application domains, especially in this big-data era that urgently demands high-performance graph processing and analysis. Unlike static graph traversals, DGTs in real-world application scenarios require not only fast traversal acceleration itself but also, more importantly, a runtime strategy that can effectively accommodate the ever-evolving nature of the graph structure updates followed by a diverse range of graph traversal algorithms . Because of these special features, state-of-the-art designs on conventional compute-centric architectures (e.g., CPU and GPU) struggle to provide sufficient acceleration for DGT processing due to the dominating irregular memory access patterns in graph traversal algorithms and inefficient platform-specific update mechanisms. In this article, we explore the algorithmic features and runtime requirements of real-world DGTs and identify their unique opportunities of acceleration on the recent Micron Automata Processor (AP), an in-situ memory-centric pattern-matching architecture. These features include the natural mapping between traversal algorithms’ path exploration pattern to classic non-deterministic finite automata processing, AP’s architectural and compilation support for DGTs’ evolving traversal operations, and its inherent hardware fitness. However, despite these benefits, enabling highly efficient DGT execution on AP is non-trivial and faces several major challenges. To tackle them, we propose DynamAP , the first AP framework design that enables fast processing for general DGTs. DynamAP is oblivious to periodical traversal algorithm changes and can address the significant overhead caused by frequent graph updates and AP recompilation through our novel hybrid macro designs and associated efficient updating strategies. We evaluate DynamAP against the current DGT designs on a CPU, GPU, and AP with a range of widely adopted DGT algorithms and real-world graphs. For a single update request , our DynamAP achieves an average speedup of 21.3x (up to 39.2x ) over the state-of-the-art implementation on host-AP architecture; an average speedup of 9.2x (up to 14.7x ) and 1.7x (up to 2.8x ) over two highly optimized DGT design frameworks on a 64-GB Intel(R) Xeon CPU and a 32-GB NVIDIA Tesla V100 GPU. DynamAP also maintains high performance and resource utilization for high graph update ratios, and can significantly benefit natural graphs that present a high average vertex degree.

Critique of “MemXCT: Memory-Centric X-Ray CT Reconstruction With Massive Parallelization” by SCC Team From Georgia Tech

For the 2020 Student Cluster Competition, we reproduced results from “MemXCT: Memory-Centric X-ray CT Reconstruction with Massive Parallelization” (Hidayetoğlu <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al.</i> ). Reproducibility is of critical importance to the scientific community, not just to verify correctness of results but also to see how easily others can understand and work with the given methods. MemXCT is an approach for image reconstruction in X-ray ptychography, which has a broad range of applications in materials science. MemXCT is not the only X-ray tomography algorithm, though; as opposed to compute-centric algorithms, it is designed to scale better by optimizing for memory bandwidth and memory latency. MemXCT also applies several key optimizations in order to ease memory pressure. In this article, we test the performance and strong scaling of MemXCT on 1 to 256 AMD CPU cores (1-4 nodes) and 1-16 Nvidia V100 GPUs (1-4 nodes). We confirm the impact of MemXCT’s optimizations. Still, we find that the performance of some important loops in the MemXCT kernel is much lower on the AMD processors (with AVX2) of our CPU nodes compared to the Intel CPUs (with AVX-512) used in the original article. We also confirm MemXCT performance on Tesla V100 GPUs, as reported in the article.